EPCOS S1D13A05B00B200

S1D13A05 LCD/USB Companion Chip
Hardware Functional Specification
Document Number: X40A-A-001-07
Status: Revision 7.7
Issue Date: 2012/02/27
© SEIKO EPSON CORPORATION 2002 - 2012. Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Features . . . . . . . . . .
2.1 Integrated Frame Buffer
2.2 CPU Interface . . . .
2.3 Display Support . . . .
2.4 Display Modes . . . .
2.5 Display Features . . .
2.6 Clock Source . . . . .
2.7 USB Device . . . . .
2.8 2D Acceleration . . .
2.9 Miscellaneous . . . .
3
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Typical System Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Pins . . . . . . . . . . . . . . . . .
4.1 Pinout Diagrams . . . . . . .
4.1.1 PFBGA 121-pin . . . . . . .
4.2 Pin Descriptions . . . . . . .
4.2.1 Host Interface . . . . . . . .
4.2.2 LCD Interface . . . . . . . .
4.2.3 Clock Input . . . . . . . . .
4.2.4 Miscellaneous . . . . . . . .
4.2.5 Power And Ground . . . . .
4.3 Summary of Configuration Options
4.4 Host Bus Interface Pin Mapping .
4.5 LCD Interface Pin Mapping . . .
5
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
A.C. Characteristics . . . . . . . .
6.1 Clock Timing . . . . . . . .
6.1.1 Input Clocks . . . . . . . . .
6.1.2 Internal Clocks . . . . . . .
6.2 RESET# Timing . . . . . . .
6.3 CPU Interface Timing . . . . .
6.3.1 Generic #1 Interface Timing
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Hardware Functional Specification
Issue Date: 2012/02/27
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S1D13A05
X40A-A-001-07
Revision 7.7
Page 4
Epson Research and Development
Vancouver Design Center
6.3.2 Generic #2 Interface Timing . . . . . . . . . . . . . . .
6.3.3 Hitachi SH-3 Interface Timing . . . . . . . . . . . . .
6.3.4 Hitachi SH-4 Interface Timing . . . . . . . . . . . . .
6.3.5 Motorola MC68K #1 Interface Timing . . . . . . . . .
6.3.6 Motorola MC68K #2 Interface Timing . . . . . . . . .
6.3.7 Motorola REDCAP2 Interface Timing . . . . . . . . .
6.3.8 Motorola Dragonball Interface Timing with DTACK .
6.3.9 Motorola Dragonball Interface Timing w/o DTACK . .
6.4 LCD Power Sequencing . . . . . . . . . . . . . . .
6.4.1 Passive/TFT Power-On Sequence . . . . . . . . . . . .
6.4.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . .
6.5 Display Interface . . . . . . . . . . . . . . . . . .
6.5.1 Generic STN Panel Timing . . . . . . . . . . . . . . .
6.5.2 Single Monochrome 4-Bit Panel Timing . . . . . . . .
6.5.3 Single Monochrome 8-Bit Panel Timing . . . . . . . .
6.5.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . .
6.5.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . .
6.5.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . .
6.5.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . .
6.5.8 Generic TFT Panel Timing . . . . . . . . . . . . . . .
6.5.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . .
6.5.10 Sharp HR-TFT Panel Timing . . . . . . . . . . . . . .
6.5.11 Casio TFT Panel Timing . . . . . . . . . . . . . . . .
6.5.12 TFT Type 2 Panel Timing . . . . . . . . . . . . . . . .
6.5.13 TFT Type 3 Panel Timing . . . . . . . . . . . . . . . .
6.5.14 TFT Type 4 Panel Timing . . . . . . . . . . . . . . . .
6.6 USB Timing . . . . . . . . . . . . . . . . . . . .
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7
Clocks . . . . . . . . . . .
7.1 Clock Descriptions . .
7.1.1 BCLK . . . . . .
7.1.2 MCLK . . . . . .
7.1.3 PCLK . . . . . .
7.1.4 PWMCLK . . . .
7.2 Clock Selection . . .
7.3 Clocks versus Functions
8
Registers . . . . . . . . . . . . . . . . .
8.1 Register Mapping . . . . . . . . .
8.2 Register Set . . . . . . . . . . . .
8.3 LCD Register Descriptions (Offset = 0h)
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S1D13A05
X40A-A-001-07
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Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
Vancouver Design Center
Page 5
8.3.1 Read-Only Configuration Registers . . . . . . . . .
8.3.2 Clock Configuration Registers . . . . . . . . . . .
8.3.3 Panel Configuration Registers . . . . . . . . . . . .
8.3.4 Look-Up Table Registers . . . . . . . . . . . . . .
8.3.5 Display Mode Registers . . . . . . . . . . . . . . .
8.3.6 Picture-in-Picture Plus (PIP+) Registers . . . . . .
8.3.7 Miscellaneous Registers . . . . . . . . . . . . . . .
8.3.8 Extended Panel Registers . . . . . . . . . . . . . .
8.4 USB Registers (Offset = 4000h) . . . . . . . . . .
8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h) .
8.6 2D Accelerator (BitBLT) Data Register Descriptions . .
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2D Accelerator (BitBLT) Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.2 BitBLT Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
10 Frame Rate Calculation
11 Display Data Formats
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12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13 SwivelView™ . . . . . . . . . . . .
13.1 Concept . . . . . . . . . . .
13.2 90° SwivelView™ . . . . . .
13.2.1 Register Programming . . .
13.3 180° SwivelView™ . . . . . .
13.3.1 Register Programming . . .
13.4 270° SwivelView™ . . . . . .
13.4.1 Register Programming . . .
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14 Picture-in-Picture Plus (PIP+)
14.1 Concept . . . . . . . .
14.2 With SwivelView Enabled
14.2.1 SwivelView 90° . . .
14.2.2 SwivelView 180° . .
14.2.3 SwivelView 270° . .
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15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16 USB Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.1 USB Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 6
Epson Research and Development
Vancouver Design Center
19 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13A05 LCD/USB Companion
Chip. Included in this document are timing diagrams, AC and DC characteristics, register
descriptions, and power management descriptions. This document is intended for two
audiences: Video Subsystem Designers and Software Developers.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
www.erd.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
1.2 Overview Description
The S1D13A05 is an LCD/USB solution designed for seamless connection to a wide
variety of microprocessors. The S1D13A05 integrates a USB slave controller and an LCD
graphics controller with an embedded 256K byte SRAM display buffer. The LCD
controller supports all standard panel types and multiple TFT types eliminating the need for
an external timing control IC. The S1D13A05 includes a Hardware Acceleration Engine to
greatly improve screen drawing functions and the built-in USB controller provides revision
1.1 compliance for applications requiring a USB client. This high level of integration
provides a low cost, low power, single chip solution to meet the demands of embedded
markets requiring USB client support, such as Mobile Communications devices and Palmsize PCs.
The S1D13A05 utilizes a guaranteed low-latency CPU architecture that provides support
for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data
path, write buffer and the Hardware Acceleration Engine provide high performance
bandwidth into display memory allowing for fast display updates.
Additionally, products requiring a rotated display can take advantage of the SwivelViewTM
feature which provides hardware rotation of the display memory transparent to the software
application. The S1D13A05 also provides support for “Picture-in-Picture Plus” (a variable
size Overlay window).
The S1D13A05, with its integrated USB client, provides impressive support for Palm OS®
handhelds. However, its impartiality to CPU type or operating system makes it an ideal
display solution for a wide variety of applications.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 8
Epson Research and Development
Vancouver Design Center
2 Features
2.1 Integrated Frame Buffer
• Embedded 256K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Hitachi SH-4 / SH-3.
Motorola M68xxx (REDCAP2, DragonBall, ColdFire).
Motorola DragonBall SZ Support (66MHz).
Motorola “REDCAP2” - no WAIT# signal.
Generic MPU bus interface with programmable ready (WAIT#).
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register
address space.
• The complete 256K byte display buffer is directly and contiguously available through
the 18-bit address bus.
2.3 Display Support
• Single-panel, single drive passive displays.
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• Extended TFT interfaces (Type 2, 3, 4)
• ‘Direct’ support for 18-bit Sharp HR-TFT LCD (or compatible interfaces).
• ‘Direct’ support for the Casio TFT LCD (or compatible interfaces).
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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2.4 Display Modes
• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades on monochrome passive LCD panels.
• Up to 64K colors on passive panels.
• Up to 64K colors on active matrix LCD panels.
• Example resolutions:
320x320 at a color depth of 16 bpp
160x160 at a color depth of 16 bpp (2 pages)
160x240 at a color depth of 16 bpp
2.5 Display Features
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
• Picture-in-Picture Plus (PIP+): displays a variable size window overlaid over background image.
• Pixel Doubling: independent control of both horizontal and vertical pixel doubling.
• example usage: 160x160 8 bpp can be expanded to 320x320 8 bpp without any additional memory.
• supports all color depths.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen
updates.
2.6 Clock Source
• Three independent clock inputs: CLKI, CLKI2 and USBCLK.
• Flexible clock source selection:
• internal Bus Clock (BCLK) selected from CLKI, CLKI/2, or CLKI2
• internal Memory Clock (MCLK) selected from BCLK or BCLK divide ratio
(REG[04h)
• internal Pixel Clock (PCLK) selected from CLKI, CLKI2, MCLK, or BCLK. PCLK
can also be divided down from source
• Single clock input possible if USB support not required.
2.7 USB Device
• USB Client, revision 1.1 compliant.
• Dedicated clock input: USBCLK.
• 48MHz crystal oscillator for USBCLK.
Hardware Functional Specification
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2.8 2D Acceleration
• 2D BitBLT engine including:
Write BitBLT
Move BitBLT
Solid Fill BitBLT
Pattern Fill BitBLT
Move BitBLT with Color Expansion
Transparent Write BitBLT
Transparent Move BitBLT
Read BitBLT
Color Expansion BitBLT
2.9 Miscellaneous
• Software initiated Video Invert.
• Software initiated Power Save mode.
• General Purpose Input/Output pins are available.
• IO Operates at 3.3 volts ± 10%.
• Core operates at 2.0 volts ± 10% or 2.5 volts ± 10%.
• 121-pin PFBGA package.
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Hardware Functional Specification
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3 Typical System Implementation Diagrams
3.1 Typical System Diagrams.
Oscillator
CLKI2
IOVDD
BS#
VSS
A[27:18]
Decoder
CSn#
AB0
FPDAT[15:0]
FPFRAME
M/R#
CS#
FPLINE
A[17:1]
AB[17:1]
FPSHIFT
D[15:0]
DB[15:0]
DRDY
WE0#
WE0#
WE1#
WE1#
RD0#
RD#
RD1#
RD/WR#
WAIT#
S1D13A05
16-bit
Single
FPFRAME LCD
Display
D[15:0]
FPLINE
FPSHIFT
MOD
Bias Power
Generic #1
BUS
GPIO0
WAIT#
BUSCLK
CLKI
RESET#
RESET#
Figure 3-1: Typical System Diagram (Generic #1 Bus)
.
Oscillator
CLKI2
IOVDD
BS#
RD/WR#
A[27:18]
Decoder
CSn#
FPDAT[8:0]
M/R#
FPFRAME
CS#
FPLINE
A[17:0]
AB[17:0]
FPSHIFT
D[15:0]
DB[15:0]
DRDY
WE#
WE0#
BHE#
WE1#
RD#
WAIT#
S1D13A05
D[8:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
9-bit
TFT
Display
Bias Power
Generic #2
BUS
GPIO0
RD#
WAIT#
BUSCLK
CLKI
RESET#
RESET#
Figure 3-2: Typical System Diagram (Generic #2 Bus)
Hardware Functional Specification
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.
Oscillator
A[25:18]
Decoder
CSn#
A[17:1]
AB0
M/R#
FPDAT12
CS#
FPDAT[9:0]
FPFRAME
AB[17:1]
D[15:0]
FPLINE
DB[15:0]
WE0#
FPSHIFT
WE0#
WE1#
WE1#
BS#
BS#
RD/WR#
DRDY
D11
D10
12-bit
TFT
Display
D[9:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
S1D13A05
GPIO0
RD/WR#
RD#
FPDAT15
Bias Power
VSS
CLKI2
SH-4
BUS
RD#
RDY#
WAIT#
CKIO
CLKI
RESET#
RESET#
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
.
Oscillator
A[25:18]
CSn#
Decoder
AB0
M/R#
AB[17:1]
D[15:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WAIT#
CKIO
RESET#
FPFRAME
CS#
A[17:1]
WE0#
FPDAT[17:0]
FPLINE
FPSHIFT
WE0#
WE1#
BS#
DRDY
S1D13A05
D[17:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
18-bit
TFT
Display
Bias Power
VSS
CLKI2
SH-3
BUS
GPO0
RD/WR#
RD#
WAIT#
CLKI
RESET#
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
S1D13A05
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.
Oscillator
MC68K #1
BUS
CLKI2
IOVDD
RD#
WE0#
A[23:18]
FC0, FC1
Decoder
FPDAT[17:0]
FPFRAME
FPLINE
M/R#
FPSHIFT
Decoder
CS#
A[17:1]
AB[17:1]
D[15:0]
DB[15:0]
LDS#
AB0
UDS#
WE1#
AS#
S1D13A05
D[17:0]
SPS
LP
18-bit
HR-TFT
Display
CLK
GPIO0
PS
GPIO1
CLS
GPIO2
REV
GPIO3
SPL
BS#
R/W#
RD/WR#
DTACK#
WAIT#
CLK
CLKI
RESET#
RESET#
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
.
Oscillator
A[31:18]
FC0, FC1
Decoder
M/R#
Decoder
CS#
CLKI2
MC68K #2
BUS
FPDAT[17:0]
A[17:0]
FPFRAME
FPLINE
AB[17:0]
D[31:16]
FPSHIFT
DB[15:0]
DS#
WE1#
AS#
BS#
R/W#
RD/WR#
SIZ1
RD#
SIZ0
WE0#
DSACK1#
WAIT#
CLK
S1D13A05
D[17:0]
SPS
LP
18-bit
HR-TFT
Display
CLK
GPIO0
PS
GPIO1
CLS
GPIO2
REV
GPIO3
SPL
CLKI
RESET#
RESET#
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
Hardware Functional Specification
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.
Oscillator
CLKI2
IOVDD
BS#
FPDAT[7:4]
A[21:18]
M/R#
Decoder
CSn
D[3:0]
FPSHIFT
FPSHIFT
CS#
A[17:1]
D[15:0]
FPLINE
DB[15:0]
R/W
RD/WR#
OE
FPFRAME
FPFRAME
AB[17:1]
FPLINE
DRDY
S1D13A05
4-bit
Single
LCD
Display
MOD
Bias Power
REDCAP2
BUS
GPIO0
RD#
EB1
WE0#
EB0
WE1#
CLK
CLKI
RESET_OUT
RESET#
AB0
VSS
*Note: CSn# can be any of CS0-CS4
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
.
IOVDD
BS#
FPDAT[7:0]
RD/WR#
A[25:18]
FPSHIFT
M/R#
Decoder
CSX
FPFRAME
CS#
A[17:1]
FPLINE
AB[17:1]
D[15:0]
DB[15:0]
LWE
WE0#
UWE
WE1#
OE
DRDY
S1D13A05
D[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
8-bit
Single
LCD
Display
Bias Power
MC68EZ328/
MC68VZ328
DragonBall
BUS
CLKI2
Oscillator
GPIO0
RD#
WAIT#
DTACK
CLKO
CLKI
RESET
RESET#
AB0
VSS
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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3.2 USB Interface
USB Socket
S1D13A05
150kΩ
USBDETECT
(GPIO5)
VBus
300kΩ
USBPUP
(GPIO4)
Full Speed Device
IOVDD
1.5kΩ
20Ω
USBDP
(GPIO7)
DP
20Ω
USBDM
(GPIO6)
DM
300kΩ
NNCD5.6LG
Overvoltage
Protection
ESD
Protection
VSS
GND
Figure 3-9: USB Typical Implementation
Hardware Functional Specification
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4 Pins
4.1 Pinout Diagrams
4.1.1 PFBGA 121-pin
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4 5 6 7 8
BOTTOM VIEW
9
10 11
Figure 4-1: Pinout Diagram - PFBGA 121-pin
Table 4-1: PFBGA 121-pin Mapping
L
NC
IOVDD
DB7
DB3
DB0
GPIO7
GPIO3
K
GPO0
VSS
DB8
DB4
DB1
GPIO6
GPIO2
IRQ
J
GPO1
DB9
DB6
DB5
DB2
GPO3
GPIO1
USBCLK
H
DB12
DB11
DB10
DB13
GPO2
IOVDD
GPIO4
GPO5
FPLINE
FPSHIFT
FPDAT0
G
WAIT#
DB15
DB14
IOVDD
VSS
GPIO5
FPDAT5
FPDAT1
FPDAT2
FPDAT3
FPDAT4
F
RESET#
VSS
RD/WR#
WE1#
CLKI
GPO4
FPDAT8
FPDAT6
VSS
FPDAT7
IOVDD
E
RD#
BS#
M/R#
CS#
WE0#
AB13
TESTEN
FPDAT9
FPDAT12
FPDAT11
FPDAT10
D
AB0
AB1
AB2
AB8
AB12
AB17
CNF3
FPDAT13
FPDAT16
FPDAT15
FPDAT14
AB9
AB16
CNF2
CNF5
CNF6
FPDAT17
GPO8
GPIO0
IOVDD
COREVDD
NC
DRDY
VSS
GPO6
FPFRAME COREVDD
GPO7
C
USBOSCO COREVDD
AB3
AB6
B
USBOSCI
VSS
AB5
GPO10
AB10
AB14
CNF1
CNF4
CLKI2
VSS
GPO9
A
NC
COREVDD
AB4
AB7
AB11
AB15
CNF0
NC
PWMOUT
IOVDD
NC
1
2
3
4
5
6
7
8
9
10
11
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X40A-A-001-07
Hardware Functional Specification
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4.2 Pin Descriptions
Key:
I
O
IO
P
CI
LI
LB2A
LB3P
LO3
LB3M
T1
Hi-Z
CUS
=
=
=
=
=
=
=
=
=
=
=
=
=
Input
Output
Bi-Directional (Input/Output)
Power pin
CMOS input
LVTTLa input
LVTTL IO buffer ([email protected])
Low noise LVTTL IO buffer ([email protected])
Low noise LVTTL Output buffer ([email protected])
Low noise LVTTL IO buffer with input mask ([email protected])
Test mode control input with pull-down resistor (typical value of 50KΩ at 3.3V)
High Impedance
Custom Cell Type
a
LVTTL is Low Voltage TTL.
4.2.1 Host Interface
Table 4-2: Host Interface Pin Descriptions
Pin Name
PFBGA
Pin #
I/O type
(see key
above)
RESET#
State
Description
This input pin has multiple functions.
AB0
D1
LI
⎯
AB[17:1]
D6,C6,A6,
B6,E6,D5,
A5,B5,C5,
D4,A4,C4,
B3,A3,C3,
D3,D2
CI
⎯
•
•
•
•
•
•
•
For Generic #1, this pin is not used and should be connected to VSS.
For Generic #2, this pin inputs system address bit 0 (A0).
For SH-3/SH-4, this pin is not used and should be connected to VSS.
For MC68K #1, this pin inputs the lower data strobe (LDS#).
For MC68K #2, this pin inputs system address bit 0 (A0).
For REDCAP2, this pin is not used and should be connected to VSS.
For DragonBall, this pin is not used and should be connected to VSS.
System address bus bits 17-1.
Input data from the system data bus.
DB[15:0]
G2, G3,
H4, H1,
H2, H3,
J2, K3, L3,
J3, J4, K4,
L4, J5, K5,
L5
LB2A
Hi-Z
•
•
•
•
•
For Generic #1, these pins are connected to D[15:0].
For Generic #2, these pins are connected to D[15:0].
For SH-3/SH-4, these pins are connected to D[15:0].
For MC68K #1, these pins are connected to D[15:0].
For MC68K #2, these pins are connected to D[31:16] for a 32-bit device
(e.g. MC68030) or D[15:0] for a 16-bit device (e.g. MC68340).
• For REDCAP2, these pins are connected to D[15:0].
• For DragonBall, these pins are connected to D[15:0].
Hardware Functional Specification
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Table 4-2: Host Interface Pin Descriptions
Pin Name
PFBGA
Pin #
I/O type
(see key
above)
RESET#
State
Description
This input pin has multiple functions.
WE0#
E5
LI
⎯
• For Generic #1, this pin inputs the write enable signal for the lower data
byte (WE0#).
• For Generic #2, this pin inputs the write enable signal (WE#)
• For SH-3/SH-4, this pin inputs the write enable signal for data byte 0
(WE0#).
• For MC68K #1, this pin must be tied to IO VDD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For REDCAP2, this pin inputs the byte enable signal for the D[7:0] data
byte (EB1).
• For DragonBall, this pin inputs the byte enable signal for the D[7:0] data
byte (LWE).
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the upper data
byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the high data
byte (BHE#).
• For SH-3/SH-4, this pin inputs the write enable signal for data byte 1
(WE1#).
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For REDCAP2, this pin inputs the byte enable signal for the D[15:8] data
byte (EB0).
• For DragonBall, this pin inputs the byte enable signal for the D[15:8]
data byte (UWE).
WE1#
F4
LI
⎯
CS#
E4
CI
⎯
Chip select input.
M/R#
E3
LI
⎯
This input pin is used to select between the display buffer and register
address spaces of the S1D13A05. M/R# is set high to access the display
buffer and low to access the registers.
This input pin has multiple functions.
BS#
E2
LI
⎯
•
•
•
•
•
•
•
For Generic #1, this pin must be tied to IO VDD.
For Generic #2, this pin must be tied to IO VDD.
For SH-3/SH-4, this pin inputs the bus start signal (BS#).
For MC68K #1, this pin inputs the address strobe (AS#).
For MC68K #2, this pin inputs the address strobe (AS#).
For REDCAP2, this pin must be tied to IO VDD.
For DragonBall, this pin must be tied to IO VDD.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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Table 4-2: Host Interface Pin Descriptions
Pin Name
PFBGA
Pin #
I/O type
(see key
above)
RESET#
State
Description
This input pin has multiple functions.
RD/WR#
F3
LI
⎯
• For Generic #1, this pin inputs the read command for the upper data
byte (RD1#).
• For Generic #2, this pin must be tied to IO VDD.
• For SH-3/SH-4, this pin inputs the RD/WR# signal. The S1D13A05
needs this signal for early decode of the bus cycle.
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For REDCAP2, this pin inputs the R/W signal.
• For DragonBall, this pin must be tied to IO VDD.
This input pin has multiple functions.
RD#
E1
LI
⎯
• For Generic #1, this pin inputs the read command for the lower data
byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
• For SH-3/SH-4, this pin inputs the read signal (RD#).
• For MC68K #1, this pin must be tied to IO VDD.
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For REDCAP2, this pin inputs the output enable (OE).
• For DragonBall, this pin inputs the output enable (OE).
During a data transfer, this output pin is driven active to force the system to
insert wait states. It is driven inactive to indicate the completion of a data
transfer. WAIT# is released to the high impedance state after the data
transfer is complete. Its active polarity is configurable.
•
•
•
•
•
WAIT#
G1
LB2A
Hi-Z
For Generic #1, this pin outputs the wait signal (WAIT#).
For Generic #2, this pin outputs the wait signal (WAIT#).
For SH-3 mode, this pin outputs the wait request signal (WAIT#).
For SH-4 mode, this pin outputs the device ready signal (RDY#).
For MC68K #1, this pin outputs the data transfer acknowledge signal
(DTACK#).
• For MC68K #2, this pin outputs the data transfer and size acknowledge
bit 1 (DSACK1#).
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer acknowledge signal
(DTACK).
Note: This pin should be tied to the inactive voltage level as selected by
CNF5, using a pull-up or pull-down resistor. If CNF5 = 1, the WAIT# pin
should be tied low using a pull-down resistor. If CNF5 = 0, the WAIT# pin
should be tied high using a pull-up resistor. If WAIT# is not used, this pin
should be tied either high or low using a pull-up or pull-down resistor.
RESET#
F1
LI
⎯
Active low input to set all internal registers to the default state and to force all
signals to their inactive states.
Hardware Functional Specification
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4.2.2 LCD Interface
Table 4-3: LCD Interface Pin Descriptions
Pin Name
PFBGA Pin#
C10,D9,D10,
D11,D8,E9,
E10,E11,
FPDAT[17:0] E8,F7,F10,
F8,G7,G11,
G10,G9,G8,
H11
I/O type
(see key
above)
RESET#
State
LB3P
0
Description
Panel Data bits 17-0.
This output pin has multiple functions.
FPFRAME
J9
LB3P
0
•
•
•
•
•
Frame Pulse
SPS for HR-TFT
GSRT for Casio
STV for TFT Type 2
STV for TFT Type 3
This output pin has multiple functions.
FPLINE
H9
LB3P
0
•
•
•
•
•
Line Pulse
LP for HR-TFT
GPCK for Casio
STB for TFT Type 2
LP for TFT Type 3
This output pin has multiple functions.
FPSHIFT
H10
LB3P
0
•
•
•
•
•
Shift Clock
DCLK for HR-TFT
CLK for Casio
CLK for TFT Type 2
CPH for TFT Type 3
This output pin has multiple functions.
DRDY
K9
LO3
0
GPO0
K1
LO3
0
GPO1
J1
LO3
0
•
•
•
•
•
•
LCD backplane bias signal (MOD) for all other LCD panels
2nd shift clock (FPSHIFT2) for passive LCD with Format 1 interface
Display enable (DRDY) for TFT panels
INV for TFT Type 2/3
DRDY for TFT Type 4
General Purpose Output
This is a general purpose output
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as VCOM
• General purpose output bit otherwise
This output pin has multiple functions.
GPO2
H5
LO3
0
GPO3
J6
LO3
0
• When in TFT Type 3 mode, operates as XOEV
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as CMD
• General purpose output bit otherwise
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Table 4-3: LCD Interface Pin Descriptions
Pin Name
PFBGA Pin#
I/O type
(see key
above)
RESET#
State
Description
This output pin has multiple functions.
GPO4
F6
LO3
0
GPO5
H8
LO3
0
• When in TFT Type 3 mode, operates as PCLK1
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as PCLK2
• General purpose output bit otherwise
This output pin has multiple functions.
GPO6
K11
LO3
0
GPO7
J11
LO3
0
• When in TFT Type 3 mode, operates as XRESH
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as XRESV
• General purpose output bit otherwise
This output pin has multiple functions.
GPO8
C11
LO3
0
GPO9
B11
LO3
0
• When in TFT Type 3 mode, operates as XOHV
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as XSTBY
• General purpose output bit otherwise
This output pin has multiple functions.
GPO10
B4
LO3
0
• When in TFT Type 3 mode, operates as PMDE
• General purpose output bit otherwise
This pin has multiple functions.
GPIO0
L8
LB3M
⎯
•
•
•
•
•
PS for HR-TFT
POL for Casio
VCLK for TFT Type 2
CPV for TFT Type 3
General purpose IO pin 0 (GPIO0)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
GPIO1
J7
LB3M
⎯
•
•
•
•
•
CLS for HR-TFT
GRES for Casio
AP for TFT Type 2
OE for TFT Type 3
General purpose IO pin 1 (GPIO1)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
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Table 4-3: LCD Interface Pin Descriptions
Pin Name
PFBGA Pin#
I/O type
(see key
above)
RESET#
State
Description
This pin has multiple functions.
GPIO2
K7
LB3M
⎯
•
•
•
•
REV for HR-TFT
FRP for Casio
POL for TFT Type 2/3
General purpose IO pin 2 (GPIO2)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
GPIO3
L7
LB3M
⎯
•
•
•
•
•
SPL for HR-TFT
STH for Casio
STH for TFT Type 2
EIO for TFT Type 3
General purpose IO pin 3 (GPIO3)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
GPIO4
H7
LB3M
⎯
• USBPUP
• General purpose IO pin 4 (GPIO4)
This pin is Hi-Z after every RESET and must either be configured as an
output using REG[64h] or be pulled high or low externally to avoid
unnecessary current drain.
This pin has multiple functions.
GPIO5
G6
LB3M
⎯
• USBDETECT
• General purpose IO pin 5 (GPIO5)
This pin always defaults as an input. When not used as a USBDETECT
pin, it must either be configured as an output using REG[64h] or be pulled
high or low externally to avoid unnecessary current drain.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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Vancouver Design Center
Page 23
Table 4-3: LCD Interface Pin Descriptions
Pin Name
PFBGA Pin#
I/O type
(see key
above)
RESET#
State
Description
This pin has multiple functions.
GPIO6
K6
CUS
⎯
• USBDM
• General purpose IO pin 6 (GPIO6)
When not used as a USB connection, this pin defaults to a Hi-Z state after
every RESET and must either be configured as an output using REG[64h]
or be pulled high or low externally to avoid unnecessary current drain.
This pin has multiple functions.
GPIO7
L6
CUS
⎯
• USBDP
• General purpose IO pin 7
When not used as a USB connection, this pin defaults to a Hi-Z state after
every RESET and must either be configured as an output using REG[64h]
or be pulled high or low externally to avoid unnecessary current drain.
IRQ
K8
LO3
0
This output pin is the IRQ pin for USB. When IRQ is activated, an active
high pulse is generated and stays high until the IRQ is serviced by
software at REG[404Ah] or REG[404Ch].
This pin has multiple functions.
PWMOUT
A9
LO3
0
• PWM Clock output
• General purpose output
Hardware Functional Specification
Issue Date: 2012/02/27
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X40A-A-001-07
Revision 7.7
Page 24
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4.2.3 Clock Input
Table 4-4: Clock Input Pin Descriptions
Pin Name
PFBGA
Pin#
I/O type
(see key
above)
RESET#
State
CLKI
F5
CI
—
CLKI2
B9
CI
—
Description
Typically used as input clock source for bus clock and memory clock
Optionally used as input clock source for pixel clock
Used as input clock source for USB.
USBCLK
USBOSCI
J8
CI
B1
—
I
Note: If this pin is not connected to an input clock source, this pin
must be connected to VSS.
USB Crystal Oscillator feedback input from crystal.
For an example implementation circuit using a crystal oscillator, see
Section 16.1, “USB Oscillator Circuit” on page 179.
—
Note: If this pin is not connected to a USB Crystal Oscillator, this pin
must be connected to VSS.
USBOSCO
C1
O
USB Crystal Oscillator output to crystal.
For an example implementation circuit using a crystal oscillator, see
Section 16.1, “USB Oscillator Circuit” on page 179.
—
4.2.4 Miscellaneous
Table 4-5: Miscellaneous Pin Descriptions
Pin Name
PFBGA
Pin#
I/O type (see
key above)
RESET#
State
CNF[6:0]
C9,C8,B8,
D7,C7,B7,
A7
CI
—
TESTEN
E7
T1
⎯
Description
These inputs are used to configure the S1D13A05 - see Table 4-7:
“Summary of Power-On/Reset Options,” on page 25.
Note: These pins are used for configuration of the S1D13A05 and
must be connected directly to IO VDD or VSS.
Test Enable input used for production test only (has type 1 pull-down
resistor with a typical value of 50KΩ at 3.3V).
Note: This pin must be left un-connected.
4.2.5 Power And Ground
Table 4-6: Power And Ground Pin Descriptions
I/O type
RESET#
(see key
State
above)
Pin Name
PFBGA
Pin#
IOVDD
L2,G4,H6,
L9,A10,F11
P
—
IO power supply.
COREVDD
A2,C2,L10,
J10
P
—
Core power supply.
VSS
B2,F2,K2,
G5,F9,B10,
K10
P
—
GND for IOVDD and COREVDD.
Description
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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Page 25
4.3 Summary of Configuration Options
These pins are used for configuration of the S1D13A05 and must be connected directly to
IOVDD or VSS. The state of CNF[6:0] are latched on the rising edge of RESET#. Changing
state at any other time has no effect.
Table 4-7: Summary of Power-On/Reset Options
Power-On/Reset State
S1D13A05
Configuration
Input
1 (connected to IO VDD)
0 (connected to VSS)
Select host bus interface as follows:
CNF4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
CNF4,CNF[2:0]
CNF3
CNF5
(see note)
CNF6
CNF2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
CNF1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
CNF0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Host Bus
SH-4/SH-3 interface, Big Endian
SH-4/SH-3 interface, Little Endian
MC68K #1, Big Endian
Reserved
MC68K #2, Big Endian
Reserved
Generic #1, Big Endian
Generic #1, Little Endian
Reserved
Generic #2, Little Endian
REDCAP2, Big Endian
Reserved
DragonBall (MC68EZ328/VZ328/SZ328), Big Endian
Reserved
Reserved
Reserved. Must be set to 1.
WAIT# is active high
WAIT# is active low
CLKI to BCLK divide ratio 2:1
CLKI to BCLK divide ratio 1:1
Note
If CNF5 = 1, the WAIT# pin should be tied low using a pull-down resistor. If CNF5 = 0,
the WAIT# pin should be tied high using a pull-up resistor. If WAIT# is not used, this
pin should be tied either high or low using a pull-up or pull-down resistor.
Hardware Functional Specification
Issue Date: 2012/02/27
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X40A-A-001-07
Revision 7.7
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4.4 Host Bus Interface Pin Mapping
Table 4-8: Host Bus Interface Pin Mapping
Generic #2
Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
A[17:1]
A[17:1]
A[17:1]
A[17:1]
A[17:1]
A[17:1]
S1D13A05
Pin Name
Generic #1
AB[17:1]
A[17:1]
AB0
A01
A0
A0
LDS#
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]2
D[15:0]
D[15:0]
CSn
CSX
CLKO
CS#
External Decode
1
CSn#
M/R#
CLKI
BS#
External Decode
1
A01
External Decode
BUSCLK
BUSCLK
Connected to IOVDD
CKIO
CLK
CLK
CLK
Connected to IOVDD
BS#
AS#
AS#
RD/WR#
R/W#
R/W#
R/W
Connected to
IOVDD
RD/WR#
RD1#
Connected to
IOVDD
RD#
RD0#
RD#
RD#
Connected to
IOVDD
SIZ1
OE
OE
WE0#
WE0#
WE#
WE0#
Connected to
IOVDD
SIZ0
EB1
LWE
WE1#
WE1#
BHE#
WE1#
UDS#
DS#
EB0
UWE
WAIT#
WAIT#
WAIT#
WAIT#/
RDY#
DTACK#
DSACK1#
N/A
DTACK
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET_OUT
RESET
Note
1
A0 for these busses is not used internally by the S1D13A05 and should be connected
to VSS.
2 If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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Page 27
4.5 LCD Interface Pin Mapping
Table 4-9: LCD Interface Pin Mapping
Monochrome Passive
Panel
Pin Name
Color Passive Panel
Single
4-bit
Color TFT Panel
Single
Generic TFT (TFT Type 1)
Format 2
8-bit
16-Bit
TFT Type 4
USB
3
18-bit
18-bit
18-bit
18-bit
SPS
GSRT
STV
STV
FPFRAME
⎯
FPLINE
FPLINE
LP
GPCK
STB
LP
FPLINE
⎯
FPSHIFT
FPSHIFT
DCLK
CLK
CLK
CPH
FPSHIFT
⎯
driven 0
no connect
INV
INV
DRDY
⎯
MOD
18-bit
TFT Type 31
18-bit
FPSHIFT
2
12-bit
TFT Type 21
FPFRAME
MOD
9-bit
Casio
TFT1
FPFRAME
DRDY
8-bit
Format 1
8-bit
4-bit
Sharp
HR-TFT1
DRDY
FPDAT0
driven 0
D0
driven 0
D0 (B5)2
D0 (G3)2
D0 (R6)2
R2
R3
R5
R5
R5
R5
R5
R5
⎯
FPDAT1
driven 0
D1
driven 0
D1 (R5)2
D1 (R3)2
D1 (G5)2
R1
R2
R4
R4
R4
R4
R4
R4
⎯
FPDAT2
driven 0
D2
driven 0
D2 (G4)2
D2 (B2)2
D2 (B4)2
R0
R1
R3
R3
R3
R3
R3
R3
⎯
FPDAT3
driven 0
D3
driven 0
D3 (B3)2
D3 (G2)2
D3 (R4)2
G2
G3
G5
G5
G5
G5
G5
G5
⎯
FPDAT4
D0
D4
D0 (R2)2
D4 (R3)2
D4 (R2)2
D8 (B5)2
G1
G2
G4
G4
G4
G4
G4
G4
⎯
FPDAT5
D1
D5
D1 (B1)2
D5 (G2)2
D5 (B1)2
D9 (R5)2
G0
G1
G3
G3
G3
G3
G3
G3
⎯
FPDAT6
D2
D6
D2 (G1)2
D6 (B1)2
D6 (G1)2
D10 (G4)2
B2
B3
B5
B5
B5
B5
B5
B5
⎯
FPDAT7
D3
D7
D3 (R1)2
D7 (R1)2
D7 (R1)2
D11 (B3)2
B1
B2
B4
B4
B4
B4
B4
B4
⎯
FPDAT8
driven 0
driven 0
driven 0
driven 0
driven 0
D4 (G3)2
B0
B1
B3
B3
B3
B3
B3
B3
⎯
FPDAT9
driven 0
driven 0
driven 0
driven 0
driven 0
D5 (B2)2
driven 0
R0
R2
R2
R2
R2
R2
R2
⎯
FPDAT10
driven 0
driven 0
driven 0
driven 0
driven 0
D6 (R2)2
driven 0
driven 0
R1
R1
R1
R1
R1
R1
⎯
FPDAT11
driven 0
driven 0
driven 0
driven 0
driven 0
D7 (G1)2
driven 0
driven 0
R0
R0
R0
R0
R0
R0
⎯
FPDAT12
driven 0
driven 0
driven 0
driven 0
driven 0
D12 (R3)2
driven 0
G0
G2
G2
G2
G2
G2
G2
⎯
FPDAT13
driven 0
driven 0
driven 0
driven 0
driven 0
D13 (G2)2
driven 0
driven 0
G1
G1
G1
G1
G1
G1
⎯
FPDAT14
driven 0
driven 0
driven 0
driven 0
driven 0
D14 (B1)2
driven 0
driven 0
G0
G0
G0
G0
G0
G0
⎯
FPDAT15
driven 0
driven 0
driven 0
driven 0
driven 0
D15 (R1)2
driven 0
B0
B2
B2
B2
B2
B2
B2
⎯
FPDAT16
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B1
B1
B1
B1
B1
B1
⎯
FPDAT17
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B0
B0
B0
B0
B0
B0
⎯
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
PS
POL
VCLK
CPV
GPIO0
⎯
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
CLS
GRES
AP
OE
GPIO1
⎯
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
REV
FRP
POL
POL
GPIO2
⎯
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
SPL
STH
STH
EIO
GPIO3
⎯
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
USBPUP
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
USBDETECT
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
USBDM
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
USBDP
GPO0
⎯
GPO0 (General Purpose Output)
GPO1
GPO1
VCOM
GPO1
⎯
GPO2
GPO2
XOEV
GPO2
⎯
GPO3
GPO3
CMD
GPO3
⎯
GPO4
GPO4
PCLK1
GPO4
⎯
GPO5
GPO5
PCLK2
GPO5
⎯
GPO6
GPO6
XRESH
GPO6
⎯
GPO7
GPO7
XRESV
GPO7
⎯
GPO8
GPO8
XOHV
GPO8
⎯
GPO9
GPO9
XSTBY
GPO9
⎯
GPO10
GPO10
PMDE
GPO10
⎯
PWMOUT
PWMOUT
⎯
Note
1
GPIO pins which are used by the HR-TFT, Casio, TFT Type 2, and TFT Type
3 interfaces, must be configured as outputs using REG[64h] bits 23-16 after every
RESET or power-up.
2
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.5, “Display Interface” on page 52.
3 The S1D13A05 also supports the 9-bit and 12-bit variations of the Type 4 TFT panel.
Hardware Functional Specification
Issue Date: 2012/02/27
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X40A-A-001-07
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5 D.C. Characteristics
Note
When applying Supply Voltages to the S1D13A05, Core VDD must be applied to the
chip before, or simultaneously with IO VDD, or damage to the chip may result.
Table 5-1: Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Core VDD
Supply Voltage
VSS - 0.3 to 3.0
V
IO VDD
Supply Voltage
VSS - 0.3 to 4.0
V
VIN
Input Voltage
VSS - 0.3 to IO VDD + 0.5
V
VOUT
Output Voltage
VSS - 0.3 to IO VDD + 0.5
V
TSTG
Storage Temperature
-65 to 150
°C
TSOL
Solder Temperature/Time
260 for 10 sec. max at lead
°C
Table 5-2: Recommended Operating Conditions
Symbol
Parameter
Core VDD
Supply Voltage
IO VDD
Supply Voltage
VIN
Input Voltage
TOPR
Operating Temperature
Condition
VSS = 0 V
Min
Typ
Max
Units
1.8 (note 1) 2.0 (note 1) 2.2 (note 1)
V
VSS = 0 V
2.25
2.5
2.75
V
VSS = 0 V
3.0
3.3
3.6
V
VSS
IO VDD
V
VSS
CORE VDD
-40
25
°C
85
1. When Core VDD is 2.0V ± 10%, the MCLK must be less than or equal to 30MHz (MCLK ≤ 30MHz)
Table 5-3: Electrical Characteristics for VDD = 3.3V typical
Symbol
IDDS
IIZ
IOZ
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
RPD
CI
CO
CIO
High Level Input Voltage
Low Level Input Voltage
Pull Down Resistance
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin Capacitance
Condition
Quiescent Conditions
Min
Typ
-1
-1
VDD = min
IOH =
-3mA (Type 1)
-6mA (Type 2)
VDD = min
IOL =
3mA (Type 1)
6mA (Type 2)
LVTTL Level, VDD = max
LVTTL Level, VDD = min
VIN = VDD
S1D13A05
X40A-A-001-07
Max
170
1
1
VDD - 0.4
V
0.4
V
0.8
120
10
10
10
V
V
kΩ
pF
pF
pF
2.0
20
Units
μA
μA
μA
50
Hardware Functional Specification
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6 A.C. Characteristics
Conditions: IO VDD = 3.3V ± 10%
TA = -40° C to 85° C
Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)
CL = 50pF (Bus/MPU Interface)
CL = 0pF (LCD Panel Interface)
6.1 Clock Timing
6.1.1 Input Clocks
Clock Input Waveform
t
PWH
t
PWL
90%
V
IH
VIL
10%
t
tr
f
TOSC
Figure 6-1: Clock Input Requirements
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol
Parameter
Min
Max
Units
100
MHz
fOSC
Input Clock Frequency (CLKI)
TOSC
Input Clock period (CLKI)
1/fOSC
ns
tPWH
Input Clock Pulse Width High (CLKI)
4.5
ns
tPWL
Input Clock Pulse Width Low (CLKI)
4.5
ns
tf
Input Clock Fall Time (10% - 90%)
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
Hardware Functional Specification
Issue Date: 2012/02/27
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X40A-A-001-07
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Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Symbol
Parameter
Min
Max
Units
66
MHz
fOSC
Input Clock Frequency (CLKI)
TOSC
Input Clock period (CLKI)
tPWH
Input Clock Pulse Width High (CLKI)
3
ns
tPWL
Input Clock Pulse Width Low (CLKI)
3
ns
1/fOSC
ns
tf
Input Clock Fall Time (10% - 90%)
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
Table 6-3: Clock Input Requirements for CLKI2
Symbol
Parameter
fOSC
Input Clock Frequency (CLKI2)
TOSC
Input Clock period (CLKI2)
tPWH
tPWL
Min
Max
Units
66
MHz
1/fOSC
ns
Input Clock Pulse Width High (CLKI2)
3
ns
Input Clock Pulse Width Low (CLKI2)
3
ns
tf
Input Clock Fall Time (10% - 90%)
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
ns
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered
when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Page 31
6.1.2 Internal Clocks
Table 6-4: Internal Clock Requirements
Symbol
Parameter
Min
Bus Clock frequency
fBCLK
Max
Units
66
MHz
COREVDD = 2.0V
30
MHz
COREVDD = 2.5V
50
MHz
fMCLK
Memory Clock frequency (see note 1)
fPCLK
Pixel Clock frequency
50
MHz
fPWMCLK
PWM Clock frequency
66
MHz
1. MCLK is derived from BCLK, therefore when BCLK is greater than 50MHz, MCLK must be divided using
REG[04h] bits 5-4.
Note
For further information on internal clocks, refer to Section 7, “Clocks” on page 85.
6.2 RESET# Timing
t1
RESET#
Figure 6-2 S1D13A05 RESET# Timing
Table 6-5 S1D13A05 RESET# Timing
Symbol
t1
Parameter
Active Reset Pulse Width
Hardware Functional Specification
Issue Date: 2012/02/27
Min
Max
Units
1
—
CLKI
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6.3 CPU Interface Timing
6.3.1 Generic #1 Interface Timing
TCLK
CLK
t5
t1
A[16:1], M/R#
t6
t2
CS#
t15
t7
t3
t8
WE0#, WE1#, RD0#, RD1#
t9
t10
t4
WAIT#
t12
t11
valid
D[15:0] (write)
t13
t14
valid
D[15:0] (read)
Figure 6-3: Generic #1 Interface Timing
S1D13A05
X40A-A-001-07
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Table 6-6: Generic #1 Interface Timing
Symbol
Parameter
fCLK
Bus clock frequency
TCLK
Bus clock period
Min
Max
Unit
50
MHz
1/fCLK
ns
t1
A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
0
ns
t2
CS# setup to CLK rising edge
0
ns
t3
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
0
ns
t4
RD0#, RD1# or WE0#, WE1# state change to WAIT# driven low
3
t5
A[16:1], M/R# and CS# hold from RD0#, RD1#, WE0#, WE1# rising
edge
0
ns
t6
CS# deasserted to reasserted
0
ns
t7
WAIT# rising edge to RD0#, RD1#, WE0#, WE1# rising edge
0
ns
t8
WE0#, WE1#, RD0#, RD1# deasserted to reasserted
1
t9
CLK rising edge to WAIT# rising edge
5
t10
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# high
impedance
t11
D[15:0] setup to 4th rising CLK edge after CS#=0 and WE0#,
WE1#=0
1
TCLK
t12
D[15:0] hold from WE0#, WE1# rising edge (write cycle)
0
ns
t13
D[15:0] valid to WAIT# rising edge (read cycle)
0.5
TCLK
t14
D[15:0] hold from RD0#, RD1# rising edge (read cycle)
2
ns
t15
Cycle Length
6
TCLK
8
ns
TCLK
14
ns
5
ns
Table 6-7: Generic #1 Interface Truth Table for Little Endian
WE0#
WE1#
RD0#
RD1#
D[15:8]
D[7:0]
Comments
0
0
1
1
valid
valid
16-bit write
0
1
1
1
-
valid
8-bit write; data on low byte (even byte address1)
1
0
1
1
valid
-
8-bit write; data on high byte (odd byte address1)
1
1
0
0
valid
valid
16-bit read
1
1
0
1
-
valid
8-bit read; data on low byte (even byte address1)
1
1
1
0
valid
-
8-bit read; data on high byte (odd byte address1)
Table 6-8: Generic #1 Interface Truth Table for Big Endian
WE0#
WE1#
RD0#
RD1#
D[15:8]
D[7:0]
Comments
0
0
1
1
valid
valid
16-bit write
0
1
1
1
-
valid
8-bit write; data on low byte (odd byte address1)
1
0
1
1
valid
-
1
1
0
0
valid
valid
16-bit read
1
1
0
1
-
valid
8-bit read; data on low byte (odd byte address1)
1
1
1
0
valid
-
8-bit write; data on high byte (even byte address1)
8-bit read; data on high byte (even byte address1)
1. Because A0 is not used internally, all addresses are seen by the S1D13A05 as even addresses (16-bit word
address aligned on even byte addresses).
Hardware Functional Specification
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6.3.2 Generic #2 Interface Timing
TBUSCLK
BUSCLK
t5
t1
A[16:0], M/R#, BHE#
t6
t2
CS#
t15
t7
t3
t8
WE#, RD#
t9
t10
t4
WAIT#
t12
t11
D[15:0] (write)
valid
t13
t14
valid
D[15:0] (read)
Figure 6-4: Generic #2 Interface Timing
S1D13A05
X40A-A-001-07
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Table 6-9: Generic #2 Interface Timing
Symbol
Parameter
fBUSCLK
Bus clock frequency
TBUSCLK
Bus clock period
Min
Max
Unit
50
MHz
1/fBUSCLK
ns
t1
A[16:0], M/R#, BHE# setup to first BUSCLK rising edge where CS# =
0 and either RD# = 0 or WE# = 0
0
ns
t2
CS# setup to BUSCLK rising edge
0
ns
t3
RD#, WE# setup to BUSCLK rising edge
0
ns
t4
RD# or WE# state change to WAIT# driven low
3
t5
A[16:0], M/R#, BHE# and CS# hold from RD#, WE# rising edge
0
ns
t6
CS# deasserted to reasserted
0
ns
t7
WAIT# rising edge to RD#, WE# rising edge
0
ns
t8
WE#, RD# deasserted to reasserted
1
TBUSCLK
5
9
ns
t9
WAIT# rising edge after BUSCLK rising edge
t10
Rising edge of either RD# or WE# to WAIT# high impedance
14
ns
7
ns
t11
D[15:0] setup to 4th rising BUSCLK edge after CS#=0 and WE#=0
1
TBUSCLK
t12
D[15:0] hold from WE# rising edge (write cycle)
0
ns
t13
D[15:0] valid to WAIT# rising edge setup (read cycle)
0.5
TBUSCLK
t14
D[15:0] hold from RD# rising edge (read cycle)
2
ns
t15
Cycle Length
6
TBUSCLK
Table 6-10: Generic #2 Interface Truth Table for Little Endian
WE#
RD#
BHE#
A0
D[15:8]
D[7:0]
Comments
0
1
0
0
valid
valid
16-bit write
0
1
1
0
-
valid
8-bit write at even address
8-bit write at odd address
0
1
0
1
valid
-
1
0
0
0
valid
valid
16-bit read
1
0
1
0
-
valid
8-bit read at even address
1
0
0
1
valid
-
8-bit read at odd address
Hardware Functional Specification
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6.3.3 Hitachi SH-3 Interface Timing
TCKIO
CKIO
t1
t8
A[16:1], M/R#, RD/WR#
t17
t9
t2 t3
BS#
t4
CSn#
t10
t11
t5
WEn#, RD#
t13
t12
t6
WAIT#
t14
t7
D[15:0] (write)
t15
t16
D[15:0] (read)
Figure 6-5: Hitachi SH-3 Interface Timing
Note
A minimum of one software wait state is required.
S1D13A05
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Table 6-11: Hitachi SH-3 Interface Timing
Symbol
fCKIO
Parameter
Min
Bus clock frequency
Unit
66
MHz
1/fCKIO
ns
t1
A[16:1], RD/WR# setup to CKIO
0
ns
t2
BS# setup
0
ns
t3
BS# hold
9
ns
t4
CSn# setup
0
ns
t5
WEn#, RD# setup to next CKIO after BS# low
0
ns
t6
Falling edge CSn# to WAIT# driven low
4
t7
D[15:0] setup to 3rd CKIO rising edge after BS# deasserted
(write cycle)
1
ns
t8
WE#, RD# deasserted to A[16:1], M/R#, RD/WR# deasserted
0
ns
t9
Rising edge of WAIT# to BS# falling
TCKIO + 16
ns
t10
CKIO rising edge before WAIT# deasserted to WEn#, RD# asserted
for next cycle
2
TCKIO
t11
Rising edge of WAIT# to WE#, RD# deasserted
0
ns
t12
WAIT# rising edge after CKIO rising edge
5
t13
Rising edge of CSn# to WAIT# high impedance
TCKIO
Bus clock period
Max
9
ns
14
ns
6
ns
t14
D[15:0] hold from WEn# deasserted (write cycle)
0
ns
t15
D[15:0] setup to WAIT# rising edge (read cycle)
0.5
TCKIO
t16
Rising edge of RD# to D[15:0] high impedance (read cycle)
3
t17
Cycle Length
5
7
ns
TCKIO
1. The S1D13A05 requires 2ns of write data hold time.
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6.3.4 Hitachi SH-4 Interface Timing
TCKIO
CKIO
t1
t8
A[16:1], RD/WR#, M/R#
t18
t9
t2 t3
BS#
t4
CSn#
t10
t11
t5
WEn#, RD#
t14
t12
t6
t13
RDY
t7
t15
D[15:0] (write)
t16
t17
D[15:0] (read)
Figure 6-6: Hitachi SH-4 Interface Timing
Note
A minimum of one software wait state is required.
S1D13A05
X40A-A-001-07
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Table 6-12: Hitachi SH-4 Interface Timing
Symbol
fCKIO
Parameter
Min
Bus clock frequency
Unit
66
MHz
1/fCKIO
ns
t1
A[16:1], M/R#, RD/WR# setup to CKIO
0
ns
t2
BS# setup
0
ns
t3
BS# hold
9
ns
t4
CSn# setup
0
ns
t5
WEn#, RD# setup to 1st CKIO rising edge after BS# low
0
ns
t6
Falling edge CSn# to RDY driven high
3
t7
D[15:0] setup to 3rd CKIO rising edge after BS# deasserted
(write cycle)
1
ns
t8
WE#,RD# deasserted to A[16:1],M/R#,RD/WR# deasserted
0
ns
t9
RDY falling edge to BS# falling
TCKIO + 11
ns
t10
CKIO rising edge before RDY deasserted to WEn#, RD# asserted
for next cycle
2
TCKIO
t11
RDY falling edge to WE#,RD# deasserted
0
ns
t12
RDY falling edge after CKIO rising edge
5
14
ns
t13
Rising edge CSn# to RDY rising edge
4
10
ns
t14
CKIO falling edge to RDY tristate
4
12
t15
D[15:0] hold from WEn# deasserted (write cycle)
0
ns
t16
D[15:0] valid setup to RDY falling edge (read cycle)
0.5
TCKIO
t17
Rising edge of RD# to D[15:0] high impedance (read cycle)
2
t18
Cycle Length
4
TCKIO
Bus clock period
Max
Hardware Functional Specification
Issue Date: 2012/02/27
7
7
ns
ns
ns
TCKIO
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6.3.5 Motorola MC68K #1 Interface Timing
TCLK
CLK
t3
t1
A[16:1], R/W#, M/R#
t13
t3
t1
CS#
t4
t1
AS#
t1
t5
UDS#, LDS#, (A0)
t8
t6
t2
t7
DTACK#
t9
t10
D[15:0] (write)
t11
t12
D[15:0] (read)
Figure 6-7: Motorola MC68K #1 Interface Timing
S1D13A05
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Table 6-13: Motorola MC68K#1 Interface Timing
Symbol
fCLK
Parameter
Min
Bus clock frequency
Unit
50
MHz
1/fCLK
ns
t1
A[16:1], M/R#, R/W# and CS# and AS# and UDS#, LDS# setup to
first CLK rising edge
1
ns
t2
CS# and AS# asserted to DTACK# driven
2
t3
A[16:1], M/R#, R/W# and CS# hold from AS# rising edge
0
ns
t4
AS# rising edge to CLK falling edge
1
ns
t5
DTACK# falling edge to UDS#, LDS# rising edge
0
ns
t6
CLK rising edge to DTACK# falling edge
5
t7
AS# rising edge to DTACK# rising edge
3
t8
1st CLK falling edge after AS# deasserted to DTACK# high
impedance
t9
D[15:0] valid to 4th CLK rising edge where CS# = 0, AS# = 0 and
either UDS# = 0 or LDS# = 0 (write cycle)
1
TCLK
t10
D[15:0] hold from DTACK# falling edge (write cycle)
0
ns
t11
D[15:0] valid setup time to DTACK# goes low (read cycle)
0.5
TCLK
t12
UDS#, LDS# rising edge to D[15:0] high impedance (read cycle)
2
ns
t13
Cycle Length
7
TCLK
TCLK
Bus clock period
Max
Hardware Functional Specification
Issue Date: 2012/02/27
7
ns
14
ns
9
ns
0.5 TCLK +
12
ns
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6.3.6 Motorola MC68K #2 Interface Timing
TCLK
CLK
t3
t1
A[16:1], M/R#, R/W#, SIZ[1:0]
t15
t4
t1
CS#
t5
t1
t6
AS#
t1
t7
DS#
t10
t9
t8
t2
DSACK1#
t11
t12
valid
D[31:16] (write)
t13
t14
valid
D[31:16] (read)
Figure 6-8: Motorola MC68K #2 Interface Timing
S1D13A05
X40A-A-001-07
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Table 6-14: Motorola MC68K#2 Interface Timing
Symbol
fCLK
Parameter
Min
Bus clock frequency
Unit
50
MHz
1/fCLK
ns
t1
A[16:0], M/R#, R/W#, SIZ[1:0] and CS# and AS# and DS# setup to
first CLK rising edge
0
ns
t2
CS# and AS# asserted low to DSACK1# driven
2
TCLK
Bus clock period
Max
7
ns
t3
A[16:1], M/R#, R/W#, SIZ[1:0] hold from AS# rising edge
0
ns
t4
CS# hold from AS# rising edge
0
ns
t5
DS# rising edge to AS# rising edge
0
ns
t6
AS# setup to CLK falling edge
1
ns
t7
DSACK1# falling edge to DS# rising edge
0
t8
CLK rising edge to DSACK1# falling edge
5
14
ns
t9
AS# rising edge to DSACK1# rising edge
3
9
ns
t10
1st CLK falling edge after AS# deasserted to DSACK1# high
impedance
TCLK + 3
ns
t11
D[15:0] setup to 4th CLK rising edge after CS#=0, AS#=0, DS#=0,
and DSACK1#=0
1
TCLK
t12
D[15:0] hold from DSACK1# falling edge
0
ns
t13
D[15:0] valid setup to DSACK1# falling edge (read cycle)
0.5
t14
DS# rising edge to D[15:0] high impedance (read cycle)
2
t15
Cycle Length
7
Hardware Functional Specification
Issue Date: 2012/02/27
ns
TCLK
9
ns
TCLK
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6.3.7 Motorola REDCAP2 Interface Timing
TCKO
CKO
t8
t1
A[16:1], R/W#, CS#
t12
t9
t2
EBO#, EB1# (write)
t3
D[15:0] (write)
t4
valid
t10
t5
EB0#, EB1#, OE# (read)
t7
t6
t11
D[15:0] (read)
valid
Figure 6-9: Motorola Redcap2 Interface Timing
S1D13A05
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Table 6-15: Motorola Redcap2 Interface Timing
Symbol
Parameter
fCKO
Bus clock frequency
TCKO
Bus clock period
Min
Max
Unit
17
MHz
1/fCKO
ns
t1
A[16:1], R/W, CSn# setup to CKO rising edge
0
ns
t2
EB0,EB1 setup to CKO rising edge (write)
0
ns
t3
D[15:0] input setup to 4th CKO rising edge after CSn# and EB0 or
EB1 asserted low (write cycle)
1
TCKO
t4
D[15:0] input hold from 4th CKO rising edge after CSn# and EB0 or
EB1 asserted low (write cycle)
7
ns
t5
EB0,EB1,OE setup to CKO rising edge (read cycle)
0
ns
t6a
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK (read cycle)
6TCKO+17
ns
t6b
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK ÷ 2 (read cycle)
9TCKO+17
ns
t6c
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK ÷ 3 (read cycle)
12TCKO+17
ns
t6d
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK ÷ 4 (read cycle)
15TCKO+17
ns
t7
EB0,EB1,OE falling edge to D[15:0] driven (read cycle)
2
9
ns
t8
A[16:1], R/W, CSn hold from CKO rising edge
0
ns
t9
EB0, EB1 setup to CKO rising edge (write cycle)
1
ns
t10
CKO falling edge to EB0, EB1, OE deasserted (read)
0
ns
t11
OE, EB0, EB1 deasserted to D[15:0] output high impedance (read)
2
t12
Cycle Length (note 1)
8
ns
TCKO
1. The cycle length for the REDCAP interface is fixed at 10 TCKO.
2. The Read and Write 2D BitBLT functions are not available when using the REDCAP interface.
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6.3.8 Motorola Dragonball Interface Timing with DTACK
TCLKO
CLKO
t1
t3
A[16:1]
t13
t1
t4
t1
t4
CSX#
t5
UWE#, LWE# (write)
t1
OE# (read)
t6
D[15:0] (write)
t7
Valid
t8
D[15:0] (read)
t9
Valid
t12
t2
t10
t11
DTACK#
Figure 6-10: Motorola Dragonball Interface Timing with DTACK
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Table 6-16: Motorola Dragonball Interface Timing with DTACK
Symbol
Parameter
fCLKO
Clock frequency
TCLKO
Clock period
Min
Max
Unit
66 (note 1)
MHz
1/fCLKO
ns
t1
A[16:1], CSX, UWE, LWE, OE setup to CLKO rising edge
1
ns
t2
CSX asserted low to DTACK driven
2
t3
A[16:1] hold from CSX rising edge
0
t4
DTACK falling edge to UWE, LWE and CSX rising edge
0
ns
t5
UWE, LWE deasserted to reasserted
1
TCLKO
t6
D[15:0] valid to fourth CLKO rising edge where CSX = 0 and UWE
= 0 or LWE = 0 (write cycle)
1
TCLKO
t7
D[15:0] hold from DTACK falling edge (write cycle)
7
ns
ns
0
ns
0.5
TCLKO
t8
D[15:0] valid setup to DTACK falling edge (read cycle)
t9
2
6
ns
t10
CSX rising edge to D[15:0] high impedance (read cycle)
CLKO rising edge to DTACK# falling edge
5
14
ns
t11
CSX rising edge to DTACK rising edge
3
9
ns
t12
t13
First CLKO falling edge after deassertion of CSX# to DTACK#
high impedance
Cycle Length
0.5TCLKO + 4 0.5TCLKO + 8
8
ns
TCLKO
1. The MC68SZ328 with a maximum clock frequency of 66MHz is supported.
The MC68VZ328 with a maximum clock frequency of 33MHz is supported.
The MC68EZ328 with a maximum clock frequency of 16MHz is supported.
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6.3.9 Motorola Dragonball Interface Timing w/o DTACK
TCLKO
CLKO
t1
t5
A[16:1]
t7
t1
CSX#
t1
t5
UWE#, LWE# (write)
t1
t5
OE#
t2
t5
D[15:0] (write)
t4
t6
t3
D[15:0] (read)
Figure 6-11: Motorola Dragonball Interface Timing w/o DTACK
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Table 6-17: Motorola Dragonball Interface Timing w/o DTACK
Symbol
Parameter
fCLKO
Bus clock frequency
TCLKO
Bus clock period
Min
Max
Unit
33 (note 1)
MHz
1/fCLKO
ns
t1
A[16:1] and CSX# and UWE#, LWE# and OE# setup to CLKO
rising edge
1
ns
t2
D[15:0] valid to 4th CLK rising edge where CSX# = 0 and UWE# =
0 or LWE# = 0 (write cycle)
1
TCLKO
t3
CSX# and OE# asserted low to D[15:0] driven (read cycle)
2
t4a
8
ns
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK (read cycle)
7
TCLKO
t4b
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK ÷ 2 (read cycle)
10
TCLKO
t4c
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK ÷ 3 (read cycle) (see note 2)
13
TCLKO
t5
A[16:1] and UWE#, LWE# and OE# and D[15:0] (write) hold from
CSX# rising edge
0
t6
CSX# rising edge to D[15:0] high impedance
2
t7
Cycle Length (see note 3)
ns
8
ns
TCLKO
1. The MC68VZ328 with a maximum clock frequency of 33MHz is supported.
The MC68EZ328 with a maximum clock frequency of 16MHz is supported.
2. The MC68EZ328 does not support the MCLK = BCLK ÷ 3 and MCLK = BCLK ÷ 4 options.
The MC68VZ328 does not support the MCLK = BCLK ÷ 4 option.
3. The cycle length for the Dragonball w/o DTACK interface is fixed at 10 TCLKO.
4. The Read and Write 2D BitBLT functions are not available when using the Dragonball w/o DTACK interface.
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6.4 LCD Power Sequencing
6.4.1 Passive/TFT Power-On Sequence
GPIO0*
t1
Power Save Mode Enable**
(REG[14h] bit 4)
t2
LCD Signals***
*It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[14h] bit 4) to 0.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-12: Passive/TFT Power-On Sequence Timing
Table 6-18: Passive/TFT Power-On Sequence Timing
Symbol
Parameter
t1
LCD signals active to LCD bias active
t2
Power Save Mode disabled to LCD signals active
Min
Max
Note 1
Note 1
0
1
Units
BCLK
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
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6.4.2 Passive/TFT Power-Off Sequence
t1
GPIO0*
Power Save Mode Enable**
(REG[14h] bit 4)
t2
LCD Signals***
*It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[14h] bit 4) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-13: Passive/TFT Power-Off Sequence Timing
Table 6-19: Passive/TFT Power-Off Sequence Timing
Symbol
Parameter
t1
LCD bias deactivated to LCD signals inactive
t2
Power Save Mode enabled to LCD signals low
Min
Max
Note 1
Note 1
0
1
Units
BCLK
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Hardware Functional Specification
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6.5 Display Interface
The timing parameters required to drive a flat panel display are shown below. Timing
details for each supported panel type are provided in the remainder of this section.
HT
HDPS
HPS
HPW
VPS
VDPS
VPW
HDP
VDP
VT
Figure 6-14: Panel Timing Parameters
Table 6-20: Panel Timing Parameter Definition and Register Summary
Symbol
HT
HDP1
HDPS
HPS
HPW
VT
VDP
VDPS
VPS
VPW
Description
Horizontal Total
Horizontal Display Period1
Derived From
((REG[20h] bits 6-0) + 1) x 8
((REG[24h] bits 6-0) + 1) x 8
For STN panels: ((REG[28h] bits 9-0) + 22)
Horizontal Display Period Start Position
For TFT panels: ((REG[28h] bits 9-0) + 5)
FPLINE Pulse Start Position
(REG[2Ch] bits 9-0) + 1
FPLINE Pulse Width
(REG[2Ch] bits 22-16) + 1
Vertical Total
(REG[30h] bits 9-0) + 1
Vertical Display Period
(REG[34h] bits 9-0) + 1
Vertical Display Period Start Position
REG[38h] bits 9-0
FPFRAME Pulse Start Position
REG[3Ch] bits 9-0
FPFRAME Pulse Width
(REG[3Ch] bits 18-16) + 1
Units
Ts
Lines (HT)
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
2. The following formulas must be valid for all panel timings:
HDPS + HDP < HT
VDPS + VDP < VT
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6.5.1 Generic STN Panel Timing
VT (= 1 Frame)
VPW
FPFRAME
VDP
FPLINE
MOD1 (DRDY)
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
1 PCLK
2
MOD (DRDY)
HDPS
HDP
FPDAT[17:0]
Figure 6-15: Generic STN Panel Timing
VT
= Vertical Total
= [(REG[30h] bits 9-0) + 1] lines
VPS
= FPFRAME Pulse Start Position
= 0 lines, because REG[3Ch] bits 9-0 = 0
VPW
= FPFRAME Pulse Width
= [(REG[3Ch] bits 18-16) + 1] lines
VDPS
= Vertical Display Period Start Position = 0 lines, because REG[38h] bits 9-0 = 0
VDP
= Vertical Display Period
= [(REG[34h] bits 9-0) + 1] lines
HT
= Horizontal Total
= [((REG[20h] bits 6-0) + 1) x 8] pixels
HPS
= FPLINE Pulse Start Position
= [(REG[2Ch] bits 9-0) + 1] pixels
HPW
= FPLINE Pulse Width
= [(REG[2Ch] bits 22-16) + 1] pixels
HDPS
= Horizontal Display Period Start Position= 22 pixels, because REG[28h] bits 9-0 = 0
HDP
= Horizontal Display Period
= [((REG[24h] bits 6-0) + 1) x 8] pixels
*For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
*HPS should comply with the following formula:
HPS > HDP + 22
HPS + HPW < HT
*Panel Type Bits (REG[0Ch] bits 1-0) = 00b (STN)
*FPFRAME Pulse Polarity Bit (REG[3Ch] bit 23) = 1 (active high)
*FPLINE Polarity Bit (REG[2Ch] bit 23) = 1 (active high)
*MOD1 is the MOD signal when REG[0Ch] bits 21-16 = 0 (MOD toggles every FPFRAME)
*MOD2 is the MOD signal when REG[0Ch] bits 21-16 = n (MOD toggles every n FPLINE)
Hardware Functional Specification
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6.5.2 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
Invalid
1-1
1-5
1-317
Invalid
FPDAT6
FPDAT5
Invalid
1-2
1-6
1-318
Invalid
Invalid
1-3
1-7
1-319
Invalid
FPDAT4
Invalid
1-4
1-8
1-320
Invalid
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 6-16: Single Monochrome 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
t13
1
FPDAT[7:4]
2
Figure 6-17: Single Monochrome 4-Bit Panel A.C. Timing
Table 6-21: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
4
2
2
1
2
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
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6.5.3 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE479 LINE480
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
Invalid
1-1
1-9
1-633
Invalid
FPDAT6
Invalid
1-2
1-10
1-634
Invalid
FPDAT5
FPDAT4
FPDAT3
Invalid
1-3
1-11
1-635
Invalid
Invalid
1-4
1-12
1-636
Invalid
Invalid
1-5
1-13
1-637
Invalid
FPDAT2
Invalid
1-6
1-14
1-638
Invalid
FPDAT1
FPDAT0
Invalid
1-7
1-15
1-639
Invalid
Invalid
1-8
1-16
1-640
Invalid
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 6-18: Single Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
t13
1
FPDAT[7:0]
2
Figure 6-19: Single Monochrome 8-Bit Panel A.C. Timing
Table 6-22: Single Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 4
8
4
4
4
4
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 4, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
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6.5.4 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
.5Ts
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
Notes:
FPDAT4
.5Ts
.5Ts
Invalid
1-R1
.5Ts
.5Ts
1-G2
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
HNDP
2.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
1-B3
1-B319
Invalid
Invalid
1-G1
1-B2
1-R4
1-R320
Invalid
Invalid
1-B1
1-R3
1-G4
1-G320
Invalid
Invalid
1-R2
1-G3
1-B4
1-B320
Invalid
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-20: Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
t13
1
FPDAT[7:4]
2
Figure 6-21: Single Color 4-Bit Panel A.C. Timing
Table 6-23: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 0.5
1
0.5
0.5
0.5
0.5
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 1.5), if negative add t3min
= HDPS - (HPS + t4min) + 1, if negative add t3min
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6.5.5 Single Color 8-Bit Panel Timing (Format 1)
VNDP
VDP
FPFRAME
FPLINE
FPDAT[7:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE239
LINE240
Invalid
2Ts
2Ts
LINE1
LINE2
FPLINE
HDP
2Ts
FPSHIFT
2Ts
2Ts
4Ts
2Ts
2Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
HNDP
2Ts
2Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
FPSHIFT2
2Ts
2Ts
4Ts
2Ts
2Ts
2Ts
1R316
2Ts
2Ts
FPDAT7
Invalid
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1R316
Invalid
FPDAT6
Invalid
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1B316
Invalid
FPDAT5
FPDAT4
FPDAT3
Invalid
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1G317
Invalid
Invalid
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1R318
Invalid
Invalid
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1B318
Invalid
FPDAT2
Invalid
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1G319
Invalid
FPDAT1
Invalid
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1R320
Invalid
FPDAT0
Invalid
1-B5
1-R6
1-R11
1-G11
1-G16
1-B16
1B320
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-22: Single Color 8-Bit Panel Timing (Format 1)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
Data Timing
FPLINE
t6a
t6b
t7a
t8
t9
t14
t11
t10
FPSHIFT
t7b
FPSHIFT2
t12 t13 t12 t13
1
FPDAT[7:0]
2
Figure 6-23: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 6-24: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
t1
t2
t3
t4
t6a
t6b
t7a
t7b
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t6amin
t6bmin
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT2 falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPSHIFT2 falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT rising, FPSHIFT2 falling edge
FPSHIFT2, FPSHIFT period
FPSHIFT2, FPSHIFT pulse width low
FPSHIFT2, FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT2, FPSHIFT falling edge
FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6a + t4
t6b + t4
t14 + 2
4
2
2
1
1
note 8
Typ
Max
6
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - (HDP + HDPS), if negative add t3min
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
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6.5.6 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
2Ts
FPSHIFT
Ts
Ts
2Ts
2Ts
Ts
Ts
2Ts
HNDP
2Ts
Ts
Ts
Ts
2Ts
Ts
Ts
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
Invalid
1-R1
1-B3
1-G6
Ts
1-G318
Invalid
Invalid
1-G1
1-R4
1-B6
1-B318
Invalid
Invalid
Invalid
1-B1
1-G4
1-R7
1-R319
Invalid
1-R2
1-B4
1-G7
1-G319
Invalid
Invalid
1-G2
1-R5
1-B7
1-B319
Invalid
FPDAT2
Invalid
1-B2
1-G5
1-R8
1-R320
Invalid
FPDAT1
Invalid
1-R3
1-B5
1-G8
1-G320
Invalid
FPDAT0
Invalid
1-G3
1-R6
1-B8
1-B320
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-24: Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
t13
1
FPDAT[7:0]
2
Figure 6-25: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 6-25: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
2
1
1
1
1
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 1, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
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6.5.7 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE479
LINE480
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
3Ts
FPSHIFT
2Ts
3Ts
3Ts
2Ts
3Ts
3Ts
3Ts
HNDP
3Ts
3Ts
2Ts
3Ts
3Ts
1-G635
Invalid
1-G12
1-G636
Invalid
1-B7
1-R13
1-R637
Invalid
1-R3
1-G8
1-B13
1-B637
Invalid
1-B3
1-R9
1-G14
1-G638
Invalid
1-G4
1-B9
1-R15
1-R639
Invalid
Invalid
1-R5
1-G10
1-B15
1-B639
Invalid
Invalid
1-B5
1-R11
1-G16
1-G640
Invalid
FPDAT11
FPDAT10
FPDAT9
FPDAT8
Invalid
1-G1
1-B6
1-R12
1-R636
Invalid
Invalid
1-R2
1-G7
1-B12
1-B636
Invalid
Invalid
1-B2
1-R8
1-G13
1-G637
Invalid
Invalid
1-G3
1-B8
1-R14
1-R638
Invalid
FPDAT3
Invalid
1-R4
1-G9
1-B14
1-B638
Invalid
FPDAT2
Invalid
1-B4
1-R10
1-G15
1-G639
Invalid
FPDAT1
Invalid
1-G5
1-B10
1-R16
1-R640
Invalid
FPDAT0
Invalid
1-R6
1-G11
1-B16
1-B640
Invalid
FPDAT15
FPDAT14
FPDAT13
FPDAT12
FPDAT7
FPDAT6
Invalid
1-R1
3Ts
3Ts
2Ts
1-G6
1-B11
Invalid
1-B1
1-R7
Invalid
1-G2
Invalid
Invalid
Invalid
FPDAT5
FPDAT4
3Ts
2Ts
2Ts
3Ts
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 640x480 panel
Figure 6-26: Single Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
t13
1
FPDAT[15:0]
2
Figure 6-27: Single Color 16-Bit Panel A.C. Timing
Table 6-26: Single Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[15:0] setup to FPSHIFT rising edge
FPDAT[15:0] hold to FPSHIFT rising edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 3
5
2
2
2
2
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
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6.5.8 Generic TFT Panel Timing
VT (= 1 Frame)
VPS
VPW
FPFRAME
VDP
VDPS
FPLINE
DRDY
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
DRDY
HDPS
FPDAT[17:0]
HDP
invalid
invalid
Figure 6-28: Generic TFT Panel Timing
VT
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
= Vertical Total
= [(REG[30h] bits 9-0) + 1] lines
= FPFRAME Pulse Start Position
= (REG[3Ch] bits 9-0) lines
= FPFRAME Pulse Width
= [(REG[3Ch] bits 18-16) + 1] lines
= Vertical Display Period Start Position= (REG[38h] bits 9-0) lines
= Vertical Display Period
= [(REG[34h] bits 9-0) + 1] lines
= Horizontal Total
= [((REG[20h] bits 6-0) + 1) x 8] pixels
= FPLINE Pulse Start Position
= [(REG[2Ch] bits 9-0) + 1] pixels
= FPLINE Pulse Width
= [(REG[2Ch] bits 22-16) + 1] pixels
= Horizontal Display Period Start Position= [(REG[28h] bits 9-0) + 5] pixels
= Horizontal Display Period
= [((REG[24h] bits 6-0) + 1) x 8] pixels
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
*Panel Type Bits (REG[0Ch] bits 1-0) = 01 (TFT)
*FPLINE Pulse Polarity Bit (REG[2Ch] bit 23) = 0 (active low)
*FPFRAME Polarity Bit (REG[3Ch] bit 23) = 0 (active low)
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6.5.9 9/12/18-Bit TFT Panel Timing
VNDP2
VDP
VNDP1
FPFRAME
FPLINE
FPDAT[17:0]
LINE240
LINE1
LINE480
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
FPDAT[17:0]
invalid
1-1
1-2
1-320
invalid
Note: DRDY is used to indicate the first pixel
Example Timing for 18-bit 320x240 panel
Figure 6-29: 18-Bit TFT Panel Timing
VDP
VNDP
VNDP1
VNDP2
HDP
HNDP
HNDP1
HNDP2
= Vertical Display Period
= VDP Lines
= Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
= Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
= Vertical Non-Display Period 2
= VDPS - VPS Lines
= Horizontal Display Period
= HDP Ts
= Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
= Horizontal Non-Display Period 1
= HDPS - HPS Ts
= Horizontal Non-Display Period 2
= HPS - (HDP + HDPS) Ts
if negative add VT
if negative add HT
if negative add HT
Hardware Functional Specification
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t1
t2
FPFRAME
t3
FPLINE
t4
FPLINE
t5
t8
t7
t6
DRDY
t9
t12
t13
t10 t11
t14
FPSHIFT
t15 t16
FPDAT[17:0]
invalid
1
2
319
320
invalid
Note: DRDY is used to indicate the first pixel
Figure 6-30: TFT A.C. Timing
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Table 6-27: TFT A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
1. Ts
2. t6min
3. t8min
Parameter
FPFRAME cycle time
FPFRAME pulse width low
FPFRAME falling edge to FPLINE falling edge phase difference
FPLINE cycle time
FPLINE pulse width low
FPLINE Falling edge to DRDY active
DRDY pulse width
DRDY falling edge to FPLINE falling edge
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
FPLINE setup to FPSHIFT falling edge
DRDY to FPSHIFT falling edge setup time
DRDY hold from FPSHIFT falling edge
Data setup to FPSHIFT falling edge
Data hold from FPSHIFT falling edge
= pixel clock period
= HDPS - HPS
= HPS - (HDP + HDPS)
Min
VT
VPW
HPS
HT
HPW
note 2
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Typ
Max
250
Units
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
if negative add HT
if negative add HT
Hardware Functional Specification
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6.5.10 Sharp HR-TFT Panel Timing
t1
t2
FPSHIFT
(DCLK)
Ts
FPDAT[17:0]
(OB[5:0],
OG[5:0],
OR[5:0])
t3
1 2 3
last
t4
GPIO3
(SPL)
t5
t6
FPLINE
(LP)
t7
GPIO1
(CLS)
t8
PS1
t10
GPIO0
(PS)
t9
t9
t9
t9
t9
PS2
t11
PS3
t12
t12
GPIO2
(REV)
Figure 6-31: Sharp HR-TFT Panel Horizontal Timing
Table 6-28: Sharp HR-TFT Panel Horizontal Timing
Symbol
Parameter
Horizontal total period
FPSHIFT (DCLK) active
Horizontal display period
GPIO3 (SPL) pulse width
FPLINE (LP) pulse width
FPLINE (LP) falling edge to GPIO3 (SPL) rising edge
GPIO1 (CLS) pulse width
GPIO1 (CLS) falling edge to GPIO0 (PS1) rising edge
GPIO0 (PS2) toggle width
GPIO0 (PS2) first falling edge to GPIO0 (PS2) first rising edge
GPIO0 (PS3) pulse width
GPIO2 (REV) toggle position to FPLINE (LP) rising edge
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
1. Ts
2. t1typ
3. t2typ
4. t3typ
Min
8
9
8
1
2
0
0
0
0
0
0
Typ
note 2
note 3
note 4
1
note 5
note 6
note 7
note 8
note 9
note 10
note 11
note 12
Max
1024
1025
1024
256
511
63
127
255
127
31
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= [(REG[20h] bits 6-0) + 1] * 8
= [((REG[24h] bits 6-0) + 1) * 8] + 1
= [(REG[24h] bits 6-0) + 1] * 8
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5. t5typ
6. t6typ
7. t7typ
8. t8typ
9. t9typ
10. t10typ
11. t11typ
12. t12typ
Page 71
= (REG[2Ch] bits 22-16) + 1
= (REG[28h] bits 9-0) - (REG[2Ch] bits 22-16) + 2
= (REG[A0h] bits 8-0)
= (REG[A4h] bits 5-0)
= (REG[ACh] bits 6-0)
= (REG[A8h] bits 7-0)
= (REG[B0h] bits 6-0)
= (REG[B4h] bits 4-0)
t1
t2
FPFRAME
(SPS)
t4 t3
t3 t4 t3
FPLINE
(LP)
t5
t6
Vertical Display Period
FPDAT[17:0]
(OB[5:0],
OG[5:0],
OR[5:0])
Line 1
Last
t7
Driving period for PS3
Driving period for PS3
Driving period for PS1 or PS2
Figure 6-32: Sharp HR-TFT Panel Vertical Timing
Table 6-29: Sharp HR-TFT Panel Vertical Timing
Symbol
Parameter
Min
Typ
Max
t1
FPFRAME (SPS) pulse width
1
note 3
8
t2
Vertical total period
1
1024
t3
FPFRAME (SPS) rising/falling edge to FPLINE (LP) rising edge
t4
FPLINE (LP) rising edge to FPFRAME (SPS) rising/falling edge
Vertical display start position
Vertical display period
Extra driving period for GPIO0 (PS1/2)
note 4
1
(note 5)
note 5
note 6
note 7
note 8
t5
t6
t7
1. Lines
2. Ts
3. t1typ
4. t2typ
5. t3typ
6. t5typ
7. t6typ
8. t7typ
0
0
1
0
Units
Lines
(note 1)
Lines
Ts (note 2)
1023
1023
1024
7
Ts
Lines
Lines
Lines
= 1 Horizontal Line
= pixel clock period
= (REG[3Ch] bits 18-16) + 1
= (REG[30h] bits 9-0) + 1
The FPFRAME (SPS) rising/falling edge can occur before or after FPLINE (LP) rising edge depending
on the value stored in the FPLINE Pulse Start Position bits (REG[2Ch] bits 9-0). To obtain the case
indicated by t3, set the FPLINE Pulse Start Position bits to 0 and the FPFRAME (SPS) rising/falling
edge will occur 1 Ts before the FPLINE (LP) rising edge. To obtain the case indicated by t4, set the
FPLINE Pulse Start Position bits to a value between 1 and the Horizontal Total - 1. Then t4 = (Horizontal
Total Period - 1) - (REG[2Ch] bits 9-0)
= (REG[38h] bits 9-0)
= (REG[34h] bits 9-0) + 1
= (REG[B8h] bits 2-0)
Hardware Functional Specification
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6.5.11 Casio TFT Panel Timing
Vertical Timing
FPFRAME
(GSRT)
t1
FPLINE
(GPCK)
t2
Horizontal Timing
t3
FPLINE
(GPCK)
t4
FPSHIFT
(CLK)
t5
t6
FPDAT[17:0]
t7
t8
GPIO3
(STH)
GPIO0
(POL)
GPIO1
(GRES)
t10
t9
t11
GPIO2
(FRP)
Figure 6-33: Casio TFT Horizontal Timing
Table 6-30: Casio TFT Horizontal Timing
Symbol
Parameter
Horizontal pulse start position
Horizontal total
Horizontal pulse width
Pixel clock period
Horizontal display period start position
Horizontal display period
FPLINE (GPCK) rising edge to GPIO3 (STH) rising edge
GPIO3 (STH) pulse width
FPLINE (GPCK) rising edge to GPIO1 (GRES) falling edge
GPIO1 (GRES) falling edge to FPLINE (GPCK) rising edge
FPLINE (GPCK) rising edge to GPIO2 (FRP) toggle point
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
1.
2.
3.
4.
5.
Ts
t1typ
t2typ
t3typ
t4typ
Min
1
8
1
4
8
0
0
1
0
Typ
note 2
note 3
note 4
note 5
note 6
note 7
note 8
1
note 9
note 10
note 11
Max
1024
1024
128
1027
1024
63
63
64
127
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= [(REG[2Ch] bits 9-0) + 1)
= [(REG[20h] bits 6-0) + 1) * 8
= [(REG[2Ch] bits 22-16) + 1
= depends on the pixel clock (PCLK)
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6.
7.
8.
9.
10.
11.
t5typ
t6typ
t7typ
t9typ
t10typ
t11typ
Page 73
= (REG[28h] bits 9-0) + 4
= [(REG[24h] bits 6-0) + 1] * 8
= (REG[C0h] bits 29-24)
= (REG[C0h] bits 5-0)
= (REG[C0h] bits 13-8) + 1
= (REG[C0h] bits 22-16)
t3
FPFRAME
(GSRT)
t2
t1
FPLINE
(GPCK)
GPIO1
(GRES)
GPIO2
(FRP)
GPIO0
(POL)
t4
t5
FPDAT[17:0]
Figure 6-34: Casio TFT Vertical Timing
Table 6-31: Casio TFT Vertical Timing
Symbol
t1
t2
t3
t4
t5
1.
2.
3.
4.
5.
6.
Lines
t1typ
t2typ
t3typ
t4typ
t5typ
Parameter
Vertical total
Vertical pulse start
Vertical pulse width
Vertical display period start position
Vertical display period
Min
1
0
1
1
1
Typ
note 2
note 3
note 4
note 5
note 6
Max
1024
1023
8
1024
1024
Units
lines (note 1)
lines
lines
lines
lines
= 1 Horizontal Line
= (REG[30h] bits 9-0) + 1
= (REG[3Ch] bits 9-0)
= (REG[3Ch] bits 18-16) + 1
= (REG[38h] bits 9-0) + 1
= (REG[34h] bits 9-0) + 1
Hardware Functional Specification
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6.5.12 TFT Type 2 Panel Timing
t1
t2
FPLINE
(STB)
GPIO0
(VCLK)
t3
t4
t5
t6
GPIO3
(STH)
FPSHIFT
(CLK)
t7
D[17:0]
t8
1
DRDY
(INV)
2
Last
t9
t11
t10
GPIO1
(AP)
t12
GPIO2
(POL)
Figure 6-35: TFT Type 2 Horizontal Timing
Table 6-32: TFT Type 2 Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Parameter
Horizontal total period
FPLINE (STB) pulse width
GPIO0 (VCLK) rising edge to FPLINE (STB) rising edge
FPLINE (STB) rising edge to GPIO0 (VCLK) falling edge
FPLINE (STB) rising edge to GPIO3 (STH) rising edge
GPIO3 (STH) pulse width
Data setup time
Data hold time
Horizontal display period
FPLINE (STB) rising edge to GPIO1 (AP) rising edge
GPIO1 (AP) pulse width
FPLINE (STB) rising edge to GPIO2 (POL) toggle position
S1D13A05
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Min
1
7
7
0.5
0.5
8
40
20
Typ
note 2
5
note 3
note 4
note 5
1
Max
1024
note 6
note 7
note 8
10
1024
90
270
16
16
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
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1. Ts
2. t1typ
3. t3typ
= pixel clock period
= [(REG[20h] bits 6-0) + 1] * 8
= (REG[BCh] bits 1-0)
Selected from 7, 9, 12 or 16 Ts
4. t4typ = (REG[BCh] bits 4-3)
Selected from 7, 9, 12 or 16 Ts
5. t5typ = (REG[28h] bits 9-0) + 3 Ts
6. t9typ = [(REG[24h] bits 6-0) + 1] * 8
7. t10typ = (REG[BCh] bits 9-8)
Selected from 40, 52, 68 or 90 Ts
8. t11typ = (REG[BCh] bits 13-11)
Selected from 20, 40, 80, 120, 150, 190, 240 or 270 Ts
t1
t2
FPFRAME
(STV)
t3
GPIO3
(STH)
t4
t5
Line1
D[17:0]
Line2
Last
GPIO2
(POL)
(Odd Frame)
GPIO2
(POL)
(Even Frame)
GPIO2
(POL)
(Alternate Timing)
Figure 6-36: TFT Type 2 Vertical Timing
Table 6-33: TFT Type 2 Vertical Timing
Symbol
t1
t2
t3
t4
t5
1.
2.
3.
4.
Ts
Lines
t4typ
t5typ
Parameter
Vertical total period
FPFRAME (STV) pulse width
GPIO3 (STH) rising edge to FPFRAME (STV) rising edge
Vertical display start position
Vertical display period
Min
8
0
1
Typ
1
0
note 3
note 4
Max
1024
1024
1024
Units
Lines
Lines
Ts (note 1)
Lines (note 2)
Ts
= pixel clock period
= 1 Horizontal Line
= (REG[38h] bits 9-0)
= (REG[34h] bits 9-0)
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6.5.13 TFT Type 3 Panel Timing
t1
t2
FPLINE
(LP)
t3
t4
GPIO3
(EIO)
FPSHIFT
(CPH)
t5
D[17:0]
t7
t6
1
DRDY
(INV)
t8
2
t10
t9
GPIO1
(OE)
t11
GPIO2
(POL)
t12
GPO1
(VCOM)
t13
t14
GPIO0
(CPV)
Figure 6-37: TFT Type 3 Horizontal Timing
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Table 6-34: TFT Type 3 Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
3.
4.
6.
7.
8.
9.
10.
7.
Ts
t1typ
t2typ
t3typ
t4typ
t8typ
t9typ
t10typ
t11typ
t12typ
t14typ
Parameter
Horizontal total period
FPLINE (LP) pulse width
FPLINE (LP) rising edge to GPIO3 (EIO) rising edge
GPIO3 (EIO) pulse width
GPIO3 (EIO) rising edge to 1st data
Data setup time
Data hold time
Horizontal display period
FPLINE (LP) rising edge to GPIO1 (OE) rising edge
GPIO1 (OE) pulse width
FPLINE (LP) rising edge to GPIO2 (POL) toggle position
FPLINE (LP) rising edge to GPO1 (VCOM) toggle position
FPLINE (LP) rising edge to GPIO0 (CPV) rising edge
GPIO0 (CPV) pulse width
Min
8
1
Typ
Max
1024
256
1
1
0.5
0.5
8
0
0
0
0
1024
512
512
512
512
0
0
512
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= [(REG[20h] bits 6-0) + 1] * 8
= (REG[2Ch] bits 22-16) + 1
= (REG[28h] bits 9-0) + 4 Ts
= Selected from 0, 1, 2 Ts
= [(REG[24h] bits 6-0) + 1] * 8
= (REG[D8h] bits 15-8) * 2
= (REG[D8h] bits 23-16) * 2
= (REG[D8h] bits 31-24) * 2
= (REG[DCh] bits 7-0) * 2
= (REG[DCh] bits 15-8) * 2
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t1
t2
FPFRAME
(STV)
t3
t3
GPIO0
(CPV)
FPLINE
(LP)
D[17:0]
t4
t5
Line1
Line2
Last
t5
GPIO1
(OE)
t6 t7
GPO2
(XOEV)
GPIO2
(POL)
(Odd Frame)
GPO1
(VCOM)
(Odd Frame)
GPIO2
(POL)
(Even Frame)
GPO1
(VCOM)
(Even Frame)
Figure 6-38: TFT Type 3 Vertical Timing
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Table 6-35: TFT Type 3 Vertical Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
1.
2.
2.
3.
4.
Ts
t4typ
t5typ
t6typ
t7typ
Parameter
Vertical total period
FPFRAME (STV) pulse width
GPIO0 (CPV) rising edge to FPFRAME (STV) rising (falling) edge
Vertical display start position
Vertical display period
GPO2 (XOEV) rising edge to GPIO0 (CPV) rising edge
GPIO0 (CPV) rising edge to GPO2 (XOEV) falling edge
Min
1
Typ
Max
1024
1
0.5
1
1
0
0
1024
512
512
Units
Lines
Lines
Lines
Lines
Lines
Ts
Ts
= pixel clock period
= (REG[38h] bits 9-0)
= (REG[34h] bits 9-0) + 1
= (REG[DCh] bits 23-16) * 2
= (REG[DCh] bits 31-24) * 2
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6.5.14 TFT Type 4 Panel Timing
VNDP2
VDP
VNDP1
FPFRAME
FPLINE
FPDAT[17:0]
LINE480
LINE1
LINE480
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
FPDAT[17:0]
invalid
1-1
1-2
1-640
invalid
Note: DRDY is used to indicate the first pixel
Example Timing for 12-bit 640x480 panel
Figure 6-39: TFT Type 4 Panel Timing
VDP
VNDP
VNDP1
VNDP2
HDP
HNDP
HNDP1
HNDP2
= Vertical Display Period
= VDP Lines
= Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
= Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
= Vertical Non-Display Period 2
= VDPS - VPS Lines
= Horizontal Display Period
= HDP Ts
= Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
= Horizontal Non-Display Period 1
= HDPS - (HPS + 1) + 5 Ts
= Horizontal Non-Display Period 2
= (HPS + 1) - (HDP + HDPS + 5) Ts
if negative add VT
if negative add HT
if negative add HT
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t1
t2
FPFRAME
t3
FPLINE
t4
FPLINE
t5
t6
t9
t7
t8
DRDY
t10
t13
t15
t14
t11 t12
FPSHIFT
t16 t17
FPDAT[17:0]
invalid
1
2
639
640
invalid
Note: DRDY is used to indicate the first pixel
Figure 6-40: TFT Type 4 A.C. Timing
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Table 6-36: TFT Type 4 A.C. Timing
Symbol
Parameter
FPFRAME cycle time
FPFRAME pulse width low
FPFRAME falling edge to FPLINE falling edge phase difference
FPLINE cycle time
FPLINE pulse width low
FPLINE Falling edge to DRDY active
DRDY active to data setup
DRDY pulse width
DRDY falling edge to FPLINE falling edge
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
FPLINE setup to FPSHIFT falling edge
DRDY to FPSHIFT falling edge setup time
DRDY hold from FPSHIFT falling edge
Data setup to FPSHIFT falling edge
Data hold from FPSHIFT falling edge
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
1. Ts
2. t6min
3. t8min
= pixel clock period
= HDPS - (HPS + 1) + 5
= (HPS + 1) - (HDP + HDPS + 5)
Min
VT
VPW
HPS + 1
HT
HPW
note 2
Typ
250
8
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Max
Units
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
if negative add HT
if negative add HT
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6.6 USB Timing
Data Signal Rise and Fall Time
Figure 6-41 Data Signal Rise and Fall Time
Figure 6-42 Differential Data Jitter
Figure 6-43 Differential to EOP Transition Skew and EOP Width
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Figure 6-44 Receiver Jitter Tolerance
Table 6-37 USB Interface Timing
Symbol
Parameter
USBFREQ
USB Clock Frequency
TPERIOD
USB Clock Period
TR
Conditions
Waveform
Typ
Max
48
CL = 50 pF
Notes 1,2
Figure 6-41
TRFM
Rise/Fall time matching
(TR/ TF)
Figure 6-41
VCRS
Output Signal Crossover Voltage
Unit
MHz
1
------------------------USBFREQ
Figure 6-41
Rise & Fall Times
TF
Min
4
20
4
20
90
110
%
1.3
2.0
V
28Note 5
ns
44
Ω
11.97
12
12.03
Mbs
Figure 6-42
-3.5
0
3.5
ns
Source Differential Driver Jitter for
Notes 3,4
Paired Transitions
Figure 6-42
-4.0
0
4.0
ns
TDEOP
Differential to EOP Transition
Skew
Note 4
Figure 6-43
-2
0
5
ns
TEOPT
Source EOP Width
Note 4
Figure 6-43
160
167
175
ns
TJR1
Receiver Data Jitter Tolerance to
Next Transition
Note 4
Figure 6-44
-18.5
0
18.5
ns
TJR2
Receiver Data Jitter Tolerance for
Note 4
Paired Transitions
Figure 6-44
-9
0
9
ns
TEOPR1
EOP Width at Receiver;
Must reject as EOP
Note 4
Figure 6-43
40
ns
TEOPR2
EOP Width at Receiver;
Must accept as EOP
Note 4
Figure 6-43
80
ns
ZDRV
Driver Output Resistance
TDRATE
Data Rate
TDDJ1
Source Differential Driver Jitter to
Notes 3,4.
Next Transition
TDDJ2
1
2
3
4
5
Steady State Drive
Measured from 10% to 90% of the data signal.
The rising and falling edges should be smoothly transitioning (monotonic).
Timing difference between the differential data signals.
Measured at crossover point of differential data signals.
20 Ω is placed in series to meet this USB specification. The actual driver output impedance is 15 Ω.
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7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI or CLKI2 (see REG[04h] bit 0). If CLKI is
selected as the source, BCLK can be a divided version (÷1, ÷2) of CLKI. CLKI is typically
derived from the host CPU bus clock.
The source clock options for BCLK may be selected as in the following table.
Table 7-1: BCLK Clock Selection
Source Clock Options
BCLK Selection
CLKI
CNF6 = 0
CLKI ÷ 2
CNF6 = 1
Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the
CPU bus clock (not a divided version of CLKI) e.g. SH-3, SH-4.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The
S1D13A05 is designed with efficient power saving control for clocks (clocks are turned off
when not used); reducing the frequency of MCLK does not necessarily save more power.
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the
CPU cycle latency and so reduces screen update performance. For a balance of power
saving and performance, the MCLK should be configured to have a high enough frequency
setting to provide sufficient screen refresh as well as acceptable CPU cycle latency.
Note
The maximum frequency of MCLK is 50MHz (30MHz if running CORE VDD at 2.0V ±
10%). As MCLK is derived from BCLK, when BCLK is greater than 50MHz, MCLK
must be divided using REG[04h] bits 5-4.
The source clock options for MCLK may be selected as in the following table.
Table 7-2: MCLK Clock Selection
Source Clock Options
MCLK Selection
BCLK
REG[04h] bits 5-4 = 00
BCLK ÷ 2
REG[04h] bits 5-4 = 01
BCLK ÷ 3
REG[04h] bits 5-4 = 10
BCLK ÷ 4
REG[04h] bits 5-4 = 11
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7.1.3 PCLK
PCLK is the internal clock used to control the panel. It should be chosen to match the
optimum frame rate of the panel. See Section 10, “Frame Rate Calculation” on page 162
for details on the relationship between PCLK and frame rate.
Some flexibility is possible in the selection of PCLK. Firstly, panels typically have a range
of permissible frame rates. Secondly, it may be possible to choose a higher PCLK
frequency and tailor the horizontal non-display period to bring down the frame-rate to its
optimal value.
The source clock options for PCLK may be selected as in the following table.
Table 7-3: PCLK Clock Selection
Source Clock Options
PCLK Selection
MCLK
REG[08h] bits 7-0 = 00h
MCLK ÷2
MCLK ÷3
MCLK ÷4
MCLK ÷8
REG[08h] bits 7-0 = 10h
REG[08h] bits 7-0 = 20h
REG[08h] bits 7-0 = 30h
REG[08h] bits 7-0 = 40h
BCLK
REG[08h] bits 7-0 = 01h
BCLK ÷2
REG[08h] bits 7-0 = 11h
BCLK ÷3
REG[08h] bits 7-0 = 21h
BCLK ÷4
REG[08h] bits 7-0 = 31h
BCLK ÷8
REG[08h] bits 7-0 = 41h
CLKI
REG[08h] bits 7-0 = 02h
CLKI ÷2
REG[08h] bits 7-0 = 12h
CLKI ÷3
REG[08h] bits 7-0 = 22h
CLKI ÷4
CLKI ÷8
REG[08h] bits 7-0 = 32h
CLKI2
REG[08h] bits 7-0 = 03h
REG[08h] bits 7-0 = 42h
CLKI2 ÷2
REG[08h] bits 7-0 = 13h
CLKI2 ÷3
REG[08h] bits 7-0 = 23h
CLKI2 ÷4
RREG[08h] bits 7-0 = 33h
CLKI2 ÷8
REG[08h] bits 7-0 = 43h
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There is a relationship between the frequency of MCLK and PCLK that must be
maintained.
Table 7-4: Relationship between MCLK and PCLK
SwivelView Orientation
Color Depth (bpp)
MCLK to PCLK Relationship
16
fMCLK ≥ fPCLK
8
fMCLK ≥ fPCLK ÷ 2
4
fMCLK ≥ fPCLK ÷ 4
2
fMCLK ≥ fPCLK ÷ 8
1
fMCLK ≥ fPCLK ÷16
16/8/4/2/1
fMCLK ≥ 1.25fPCLK
SwivelView 0° and 180°
SwivelView 90° and 270°
7.1.4 PWMCLK
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK may be selected as in the following table.
Table 7-5: PWMCLK Clock Selection
Source Clock Options
PWMCLK Selection
CLKI
REG[70h] bits 2-1 = 00
CLKI2
REG[70h] bits 2-1 = 01
MCLK
REG[70h] bits 2-1 = 10
PCLK
REG[70h] bits 2-1 = 11
For further information on controlling PWMCLK, see “PWM Clock Configuration
Register” on page 121..
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7.2 Clock Selection
The following diagram provides a logical representation of the S1D13A05 internal clocks
used for the LCD controller.
CLKI
0
÷2
0
1
BCLK
1
CNF61
REG[04h] bit 0
REG[04h] bits 5-4
00
÷2
01
÷3
10
÷4
11
MCLK
00
01
000
10
CLKI2
11
REG[08h] bits 1,0
÷2
001
÷3
010
÷4
011
÷8
1xx
PCLK
00
REG[08h] bits 6-4
01
PWMCLK
10
11
REG[70h] bits 2-1
Figure 7-1: Clock Selection
Note
1
CNF6 must be set at RESET#.
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7.3 Clocks versus Functions
Table 7-6: “S1D13A05 Internal Clock Requirements”, lists the internal clocks required for
the following S1D13A05 functions.
Table 7-6: S1D13A05 Internal Clock Requirements
Function
Bus Clock
(BCLK)
Memory Clock
(MCLK)
Pixel Clock
(PCLK)
PWM Clock
(PWMCLK)
USB Clock
(USBCLK)
Register Read/Write
Required
Not Required
Not Required
Not Required1
Not Required
Memory Read/Write
Required
Required
Not Required
Not Required1
Not Required
Look-Up Table Register
Read/Write
Required
Required
Not Required
Not Required1
Not Required
Software Power Save
Required
Not Required
Not Required
Not Required1
Not Required
1
LCD Output
Required
Required
Required
Not Required
Not Required
USB Register Read/Write
Required
Not Required
Not Required
Not Required
Required
Note
1
PWMCLK is an optional clock (see Section 7.1.4, “PWMCLK” on page 87).
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8 Registers
This section discusses how and where to access the S1D13A05 registers. It also provides
detailed information about the layout and usage of each register.
8.1 Register Mapping
The S1D13A05 registers are memory-mapped. When the system decodes the input pins as
CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by
AB[17:0] and is mapped as follows.
Table 8-1: S1D13A05 Register Mapping
M/R#
Address
Size
Function
1
00000h to 40000h
256K bytes
SRAM memory
0
0000h to 00E3h
227 bytes
Configuration registers
0
4000h to 4054h
84 bytes
USB registers
0
8000h to 8019h
25 bytes
2D Acceleration Registers
0
10000h to 1FFFEh
65536 bytes (64K bytes)
2D Accelerator Data Port
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8.2 Register Set
The S1D13A05 register set is as follows.
Table 8-2: S1D13A05 Register Set
Register
Pg
Register
Pg
LCD Register Descriptions (Offset = 0h)
Read-Only Configuration Registers
REG[00h] Product Information Register
93
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register
94
REG[08h] Pixel Clock Configuration Register
95
Panel Configuration Registers
REG[0Ch] Panel Type & MOD Rate Register
96
REG[14h] Power Save Configuration Register
REG[10h] Display Settings Register
97
100
Look-Up Table Registers
REG[18h] Look-Up Table Write Register
101
REG[1Ch] Look-Up Table Read Register
102
Display Mode Registers
REG[20h] Horizontal Total Register
103
REG[24h] Horizontal Display Period Register
103
REG[28h] Horizontal Display Period Start Position Register
104
REG[2Ch] FPLINE Register
104
REG[30h] Vertical Total Register
105
REG[34h] Vertical Display Period Register
106
REG[38h] Vertical Display Period Start Position Register
106
REG[3Ch] FPFRAME Register
107
REG[40h] Main Window Display Start Address Register
108
REG[44h] Main Window Line Address Offset Register
108
REG[48h] Extended Panel Type Register
108
Picture-in-Picture Plus (PIP+) Registers
REG[50h] PIP+ Window Display Start Address Register
110
REG[54h] PIP+ Window Line Address Offset Register
110
REG[58h] PIP+ Window X Positions Register
111
REG[5Ch] PIP+ Window Y Positions Register
113
Miscellaneous Registers
REG[60h] Reserved
115
REG[64h] GPIO Status and Control Register
115
REG[68h] GPO Status and Control Register
119
REG[70h] PWM Clock Configuration Register
121
REG[74h] PWMOUT Duty Cycle Register
122
REG[80h] Scratch Pad A Register
123
REG[84h] Scratch Pad B Register
123
REG[88h] Scratch Pad C Register
123
Extended Panel Registers
REG[A0h] HR-TFT CLS Width Register
124
REG[A4h] HR-TFT PS1 Rising Edge Register
124
REG[A8h] HR-TFT PS2 Rising Edge Register
124
REG[ACh] HR-TFT PS2 Toggle Width Register
125
REG[B0h] HR-TFT PS3 Signal Width Register
125
REG[B4h] HR-TFT REV Toggle Point Register
125
REG[B8h] HR-TFT PS1/2 End Register
126
REG[BCh] Type 2 TFT Configuration Register
126
REG[C0h] Casio TFT Timing Register
129
REG[D8h] Type 3 TFT Configuration 0 Register
128
REG[DCh] Type 3 TFT Configuration 1 Register
129
REG[E0h] Type 3 TFT PCLK Divide Register
130
REG[E4h] Type 3 TFT Partial Mode Display Control Register
131
REG[E8h] Type 3 TFT Partial Area 0 Positions Register
132
REG[ECh] Type 3 TFT Partial Area 1 Positions Register
132
REG[F0h] Type 3 TFT Partial Area 2 Positions Register
133
REG[F4h] Type 3 TFT Command Store Register
133
REG[F8h] Type 3 TFT Miscellaneous Register
134
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Table 8-2: S1D13A05 Register Set
Register
Pg
Register
Pg
USB Register Descriptions (Offset = 4000h)
REG[4000h] Control Register
135
REG[4002h] Interrupt Enable Register 0
136
REG[4004h] Interrupt Status Register 0
137
REG[4006h] Interrupt Enable Register 1
138
REG[4008h] Interrupt Status Register 1
138
REG[4010h] Endpoint 1 Index Register
139
REG[4012h] Endpoint 1 Receive Mailbox Data Register
139
REG[4018h] Endpoint 2 Index Register
139
REG[401Ah] Endpoint 2 Transmit Mailbox Data Register
140
REG[401Ch] Endpoint 2 Interrupt Polling Interval Register
140
REG[4020h] Endpoint 3 Receive FIFO Data Register
140
REG[4022h] Endpoint 3 Receive FIFO Count Register
140
REG[4024h] Endpoint 3 Receive FIFO Status Register
141
REG[4026h] Endpoint 3 Maximum Packet Size Register
141
REG[4028h] Endpoint 4 Transmit FIFO Data Register
141
REG[402Ah] Endpoint 4 Transmit FIFO Count Register
142
REG[402Ch] Endpoint 4 Transmit FIFO Status Register
142
REG[402Eh] Endpoint 4 Maximum Packet Size Register
142
REG[4030h] Endpoint 4 Maximum Packet Size Register
142
REG[4032h] USB Status Register
143
REG[4034h] Frame Counter MSB Register
144
REG[4036h] Frame Counter LSB Register
144
REG[4038h] Extended Register Index
144
REG[403Ah] Extended Register Data
144
REG[403Ah], Index[00h] Vendor ID MSB
145
REG[403Ah], Index[01h] Vendor ID LSB
145
REG[403Ah], Index[02h] Product ID MSB
145
REG[403Ah], Index[03h] Product ID LSB
145
145
REG[403Ah], Index[04h] Release Number MSB
145
REG[403Ah], Index[05h] Release Number LSB
REG[403Ah], Index[06h] Receive FIFO Almost Full Threshold
146
REG[403Ah], Index[07h] Transmit FIFO Almost Empty Threshold 146
REG[403Ah], Index[08h] USB Control
146
REG[403Ah], Index[09h] Maximum Power Consumption
146
REG[403Ah], Index[0Ah] Packet Control
147
REG[403Ah], Index[0Bh] Reserved
148
REG[403Ah], Index[0Ch] FIFO Control
148
REG[4040h] USBFC Input Control Register
148
REG[4042h] Reserved
149
REG[4044h] Pin Input Status / Pin Output Data Register
149
REG[4046h] Interrupt Control Enable Register 0
149
REG[4048h] Interrupt Control Enable Register 1
150
REG[404Ah] Interrupt Control Status/Clear Register 0
150
REG[404Ch] Interrupt Control Status/Clear Register 1
151
REG[404Eh] Interrupt Control Masked Status Register 0
152
REG[4050h] Interrupt Control Masked Status Register 1
152
REG[4052h] USB Software Reset Register
152
REG[4054h] USB Wait State Register
152
2D Acceleration (BitBLT) Register Descriptions (Offset = 8000h)
REG[8000h] BitBLT Control Register
153
REG[8004h] BitBLT Status Register
154
REG[8008h] BitBLT Command Register
155
REG[800Ch] BitBLT Source Start Address Register
157
REG[8010h] BitBLT Destination Start Address Register
157
REG[8014h] BitBLT Memory Address Offset Register
158
REG[8018h] BitBLT Width Register
158
REG[801Ch] BitBLT Height Register
158
REG[8020h] BitBLT Background Color Register
159
REG[8024h] BitBLT Foreground Color Register
159
2D Acceleration (BitBLT) Data Register Descriptions (Offset = 10000h)
AB16-AB0 = 10000h-1FFFEh, 2D Accelerator (BitBLT) Data Memory Mapped Region Register
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8.3 LCD Register Descriptions (Offset = 0h)
Unless specified otherwise, all register bits are set to 0 during power-on.
8.3.1 Read-Only Configuration Registers
Product Information Register
REG[00h]
Default = 2Dxx402Dh
Product Code bits 5-0
31
30
29
28
Read Only
Revision Code
bits 1-0
27
26
25
24
n/a
23
CNF[6:0] Status
22
Display Buffer Size bits 7-0
15
14
13
12
11
21
20
19
18
3
2
Product Code bits 5-0
10
9
8
7
6
5
4
17
16
Revision Code
bits 1-0
1
0
bits 31-26
Product Code
These read-only bits indicate the product code. The product code is 001011 (0Bh).
bits 25-24
Revision Code
These are read-only bits that indicates the revision code. The revision code is 01.
bits 22-16
CNF[6:0] Status
These read-only status bits return the status of the configuration pins CNF[6:0]. CNF[6:0]
are latched at the rising edge of RESET#.
Note
For a functional description of each configuration bit (CNF[6:0]), see Section 4.3,
“Summary of Configuration Options” on page 25.
bits 15-8
Display Buffer Size Bits [7:0]
This is a read-only register that indicates the size of the SRAM display buffer measured in
4K byte increments. The S1D13A05 display buffer is 256K bytes and therefore this register returns a value of 64 (40h).
Value of this register = display buffer size ÷ 4K bytes
= 256K bytes ÷ 4K bytes
= 64 (40h)
bits 7-2
Product Code
These read-only bits indicate the product code. The product code is 001011 (0Bh).
bits 1-0
Revision Code
These are read-only bits that indicates the revision code. The revision code is 01.
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8.3.2 Clock Configuration Registers
Memory Clock Configuration Register
REG[04h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
14
bits 5-4
13
12
11
20
19
MCLK Divide
Select bits 1-0
n/a
15
21
10
9
8
7
6
5
18
17
16
BCLK
Source
Select
1
0
n/a
4
3
2
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Table 8-3: MCLK Divide Selection
bit 0
MCLK Divide Select Bits
BCLK to MCLK Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
BCLK Source Select
When this bit = 0, the source of the Bus Clock (BCLK) is input pin CLKI or a divided
down version of CLKI. CLKI may be divided down using the CLKI to BCLK divide
select configuration pin CNF6.
When this bit = 1, the source of the Bus Clock (BCLK) is input pin CLKI2.
Note
Changing this bit allows the BCLK source to be switched in a glitch-free manner.
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Pixel Clock Configuration Register
REG[08h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
n/a
15
bits 6-4
14
13
12
11
22
21
20
19
PCLK Divide Select bits 2-0
10
9
8
7
6
5
4
18
n/a
3
2
17
16
PCLK Source
Select bits 1-0
1
0
PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
Table 8-4: PCLK Divide Selection
bits 1-0
PCLK Divide Select Bits
PCLK Source to PCLK Frequency Ratio
000
1:1
001
2:1
010
3:1
011
4:1
1XX
8:1
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
Table 8-5: PCLK Source Selection
PCLK Source Select Bits
PCLK Source
00
MCLK
01
BCLK
10
CLKI
11
CLKI2
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8.3.3 Panel Configuration Registers
Panel Type & MOD Rate Register
REG[0Ch]
Default = 00000000h
Read/Write
FPSHIFT
n/a
31
30
29
28
27
26
25
14
13
12
24
HR-TFT
PS
Mode
n/a
15
n/a
Invert
11
10
9
MOD Rate bits 5-0
23
Panel
Data
Format
Select
22
Color/
Mono
Panel
Select
7
6
8
21
20
Panel Data Width
bits 1-0
5
19
18
17
Reserv
ed
n/a
Panel Type
bits 1-0
3
2
4
1
16
0
bit 24
FPSHIFT Invert
This bit inverts the FPSHIFT signal used by active panels. For passive panels, this bit has
no effect.
When this bit is 0, FPSHIFT is unchanged.
When this bit is 1, FPSHIFT is inverted.
bits 21-16
MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
bit 8
HR-TFT PS Mode
This bit is for HR-TFT panels only.
This bit selects the timing used for the PS signal. The alternate PS timings (PS1, PS2,
PS3) result in additional power savings on the HR-TFT Panel.
When this bit = 0, the PS signal uses PS1 timing.
When this bit = 1, the PS signal uses PS2 timing.
bit 7
Panel Data Format Select
When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC
timing see Section 6.5.5, “Single Color 8-Bit Panel Timing (Format 1)” on page 60.
When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC
timing see Section 6.5.6, “Single Color 8-Bit Panel Timing (Format 2)” on page 62.
bit 6
Color/Mono Panel Select
When this bit = 0, a monochrome LCD panel is selected.
When this bit = 1, a color LCD panel is selected.
bits 5-4
Panel Data Width Bits [1:0]
These bits select the data width size of the LCD panel.
Table 8-6: Panel Data Width Selection
Panel Data Width Bits [1:0]
Passive Panel Data Width
Size
Active Panel Data Width Size
00
4-bit
9-bit
01
8-bit
12-bit
10
16-bit
18-bit
11
Reserved
Reserved
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bit 3
Reserved.
This bit must be set to 0.
bits 1-0
Panel Type Bits[1:0]
These bits select the panel type.
Table 8-7: LCD Panel Type Selection
Panel Type Bits [1:0]
Panel Type
00
STN
01
TFT
10
Reserved
11
HR-TFT
Display Settings Register
REG[10h]
Default = 00000000h
Read/Write
Pixel
n/a
31
Pixel
Doubling Doubling
Display
Blank
Dithering
Disable
Display
Blank
Polarity
SW
Video
Invert
Vertical
Horiz.
30
29
28
27
26
25
24
23
22
21
20
14
13
12
11
10
9
8
7
6
5
4
n/a
15
bit 25
+
PIP
Window
Enable
n/a
SwivelView Mode
Select
19
18
17
Bits-per-pixel Select
(actual value: 1, 2, 4, 8 or 16 bpp)
3
2
1
16
0
Pixel Doubling Vertical Enable
This bit controls the pixel doubling feature for the vertical dimension or height of the
panel (i.e. 160 pixel high data doubled to 320 pixel high panel).
When this bit = 1, pixel doubling in the vertical dimension (height) is enabled.
When this bit = 0, there is no hardware effect.
Note
Pixel Doubling is not supported in SwivelView 90° or SwivelView 270° modes.
bit 24
Pixel Doubling Horizontal Enable
This bit controls the pixel doubling feature for the horizontal dimension or width of the
panel (i.e. 160 pixel wide data doubled to 320 pixel wide panel)
When this bit = 1, pixel doubling in the horizontal dimension (width) is enabled.
When this bit = 0, there is no hardware effect.
Note
Pixel Doubling is not supported in SwivelView 90° or SwivelView 270° modes.
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bit 23
Display Blank
When this bit = 0, the LCD display pipeline is enabled.
When this bit = 1, all applicable LCD data outputs (see Table 4-9: “LCD Interface Pin
Mapping,” on page 27) are forced to zero or one. The following table summarizes the
changes to the signals on FPDAT[17:0] for each combination of bits.
Table 8-8: Display Control Summary
Display Blank
(REG[10h] bit 23)
Display Blank Polarity
(REG[10h] bit 21)
0
X
Software Video Invert
(REG[10h] bit 20)
Output Data Lines
(FPDAT[17:0])
0
Normal
1
Inverted
0
All 0
1
All 1
0
All 1
1
All 0
0
1
1
bit 22
Dithering Disable
When this bit = 0, dithering on the passive LCD panel is enabled, allowing a maximum of
64K colors (218) or 64 gray shades in 1/2/4/8 bpp mode. In 16bpp mode, only 64K colors
(216) can also be achieved.
When this bit = 1, dithering on the passive LCD panel is disabled, allowing a maximum of
4096 colors (212) or 16 gray shades.
The dithering algorithm provides more shades of each primary color.
Note
For a summary of the results of dithering for each color depth, see Table 8-10: “LCD
Bit-per-pixel Selection,” on page 99.
bit 21
Display Blank Polarity
When this bit = 0, the display blank function operates normally.
When this bit = 1, the display blank function switches polarity.
This bit works in conjunction with bit 23 and bit 20. Table 8-8: “Display Control Summary” summarizes the changes to the signals on FPDAT[17:0] for each combination of
bits.
bit 20
Software Video Invert
When this bit = 0, video data is normal.
When this bit = 1, video data is inverted.
This bit works in conjunction with bit 23 and bit 21. Table 8-8: “Display Control Summary” summarizes the changes to the signals on FPDAT[17:0] for each combination of
bits.
Note
Video data is inverted after the Look-Up Table
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bit 19
PIP+ Window Enable
This bit enables a PIP+ window within the main window. The location of the PIP+ window within the landscape window is determined by the PIP+ X Position register
(REG[58h]) and PIP+ Y Position register (REG[5Ch]). The PIP+ window has its own Display Start Address register (REG[50h]) and Memory Address Offset register (REG[54h]).
The PIP+ window shares the same color depth and SwivelViewTM orientation as the main
window.
bit 17-16
SwivelView Mode Select Bits [1:0]
These bits select different SwivelViewTM orientations:
Table 8-9: SwivelViewTM Mode Select Options
bits 4-0
SwivelView Mode Select Bits
SwivelView Orientation
00
0° (Normal)
01
90°
10
180°
11
270°
Bit-per-pixel Select bits [4:0]
These bits select the color depth (bit-per-pixel) for the displayed data for both the main
window and the PIP+ window (if active).
1, 2, 4 and 8 bpp modes use the 18-bit LUT. 16 bpp mode bypasses the LUT. For further
details on the LUT, refer to Section 12, “Look-Up Table Architecture” on page 164.
Table 8-10: LCD Bit-per-pixel Selection
Bit-per-pixel Select Bits [4:0]
Color Depth (bpp)
00000
Max. No. Of Simultaneously
Displayed Colors/Shades
Reserved
00001
1 bpp
2/2
00010
2 bpp
4/4
00011
00100
Reserved
4 bpp
00101 - 00111
16/16
Reserved
01000
8 bpp
256/64
10000
16 bpp
64K/64
10001 - 11111
Reserved
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Power Save Configuration Register
REG[14h]
Default = 00000010h
Read/Write
n/a
31
30
29
28
27
26
25
24
VNDP
Status
(RO)
n/a
15
14
13
12
23
11
10
9
8
7
22
Memory
Power
Save
Status
(RO)
6
21
20
n/a
Power
Save
Enable
5
4
19
18
17
Reserv
ed
n/a
3
2
16
1
0
bit 7
Vertical Non-Display Period Status (Read-only)
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
bit 6
Memory Controller Power Save Status (Read-only)
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
Note
Memory reads/writes are possible during power save mode because the S1D13A05 dynamically enables the memory controller for display buffer accesses.
bit 4
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 15, “Power
Save Mode” on page 178.
Note
Memory reads/writes are possible during power save mode because the S1D13A05 dynamically enables the memory controller for display buffer accesses.
bit 0
Reserved
This bit must be set to 0.
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8.3.4 Look-Up Table Registers
Look-Up Table Write Register
REG[18h]
Default = 00000000h
Write Only
LUT Write Address
31
15
30
14
29
28
LUT Green Write Data
13
12
27
LUT Red Write Data
26
25
24
23
22
n/a
11
10
9
8
7
6
21
20
LUT Blue Write Data
5
4
n/a
19
18
17
16
n/a
3
2
1
0
Note
The S1D13A05 has three 256-position, 6-bit wide LUTs, one for each of red, green, and
blue (see Section 12, “Look-Up Table Architecture” on page 164).
Note
This is a write-only register and returns 00h if read.
bits 31-24
LUT Write Address Bits [7:0]
These bits form a pointer into the Look-Up Table (LUT) which is used to write the LUT
Red, Green, and Blue data. When the S1D13A05 is set to a host bus interface using little endian (CNF4 = 0), the RGB data is updated to the LUT with the completion of a
write to these bits.
Note
When a value is written to the LUT Write Address Bits, the same value is automatically
placed in the LUT Read Address Bits (REG[1Ch] bits 31-24).
bits 23-18
LUT Red Write Data Bits [5:0]
These bits contains the data to be written to the red component of the Look-Up Table. The
LUT position is controlled by the LUT Write Address bits (bits 31-24).
bits 15-10
LUT Green Write Data Bits [5:0]
These bits contains the data to be written to the green component of the Look-Up Table.
The LUT position is controlled by the LUT Write Address bits (bits 31-24).
bits 7-2
LUT Blue Write Data Bits [5:0]
These bits contains the data to be written to the blue component of the Look-Up Table.
The LUT position is controlled by the LUT Write Address bits (bits 31-24). When the
S1D13A05 is set to a host bus interface using big endian (CNF4 = 1), the RGB data is
updated to the LUT with the completion of a write to these bits.
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Look-Up Table Read Register
REG[1Ch]
Default = 00000000h
Write Only (bits 31-24)/Read Only
LUT Read Address (write only)
31
15
30
14
29
28
LUT Green Read Data
13
12
27
26
LUT Red Read Data
25
24
23
22
n/a
11
10
9
8
7
6
21
20
LUT Blue Read Data
5
4
n/a
19
18
17
16
n/a
3
2
1
0
Note
The S1D13A05 has three 256-position, 6-bit wide LUTs, one for each of red, green, and
blue (see Section 12, “Look-Up Table Architecture” on page 164).
bits 31-24
LUT Read Address Bits [7:0] (Write Only)
This register forms a pointer into the Look-Up Table (LUT) which is used to read LUT
data. Red data is read from bits 23-18, green data from bits 15-10, and blue data from bits
7-2.
Note
If a write to the LUT Write Address Bits (REG[18h] bits 31-24) is made, the LUT Read
Address bits are automatically updated with the same value.
bits 23-18
LUT Red Read Data Bits [5:0] (Read Only)
These bits point to the data from the red component of the Look-Up Table. The LUT position is controlled by the LUT Read Address bits (bits 31-24). This is a read-only register.
bits 15-10
LUT Green Read Data Bits [5:0] (Read Only)
These bits point to the data from the green component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address bits (bits 31-24). This is a read-only register.
bits 7-2
LUT Blue Read Data Bits [5:0] (Read Only)
These bits point to the data from the blue component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address bits (bits 31-24). This is a read-only register.
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8.3.5 Display Mode Registers
Horizontal Total Register
REG[20h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
n/a
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
bits 6-0
20
19
18
Horizontal Total bits 6-0
4
3
2
17
16
1
0
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Horizontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolution supported is 800x600.
REG[20h] bits 6:0 = (Horizontal Total in number of pixels ÷ 8) - 1
Note
1
For all panels this register must be programmed such that:
HDPS + HDP < HT
HT - HDP ≥ 8MCLK
2
For passive panels, this register must be programmed such that:
HPS + HPW < HT
3 See Section 6.5, “Display Interface” on page 52.
Horizontal Display Period Register
REG[24h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
n/a
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
bits 6-0
20
19
18
Horizontal Display Period bits 6-0
4
3
2
17
16
1
0
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total to allow for a sufficient
Horizontal Non-Display period.
REG[24h] bits 6:0 = (Horizontal Display Period in number of pixels ÷ 8) - 1
Note
For passive panels, HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
For TFT panels, HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
Note
See Section 6.5, “Display Interface” on page 52.
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Horizontal Display Period Start Position Register
REG[28h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
12
11
10
9
8
7
n/a
15
14
13
bits 9-0
22
21
20
19
18
Horizontal Display Period Start Position bits 9-0
6
5
4
3
2
17
16
1
0
Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT and HR-TFT panels.
For passive LCD panels these bits must be set to 00h which will result in HDPS = 22.
HDPS = (REG[28h] bits 9-0) + 22
For TFT panels, HDPS is calculated using the following formula.
HDPS = (REG[28h] bits 9-0) + 5
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
FPLINE Register
REG[2Ch]
Default = 00000000h
Read/Write
FPLINE
Polarity
n/a
31
30
29
28
27
26
25
24
23
12
11
10
9
8
7
n/a
15
14
13
FPLINE Pulse Width bits 6-0
22
21
20
19
FPLINE Pulse Start Position bits 9-0
6
5
4
3
18
17
16
2
1
0
bit 23
FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must
be set to 1. For active panels, this bit is set according to the horizontal sync signal of the
panel (typically FPLINE or LP). This bit has no effect for TFT Type 2 and TFT Type 3
panels.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
bits 22-16
FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically FPLINE or LP, depending on the panel type.
REG[2Ch] bits 22:16 = FPLINE Pulse Width in number of pixels - 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
See Section 6.5, “Display Interface” on page 52.
S1D13A05
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bits 9-0
Page 105
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[2Ch] bits 9-0) + 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
See Section 6.5, “Display Interface” on page 52.
Vertical Total Register
REG[30h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
12
11
10
9
8
7
6
n/a
15
bits 9-0
14
13
21
20
Vertical Total bits 9-0
5
4
19
18
17
16
3
2
1
0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
REG[30h] bits 9:0 = Vertical Total in number of lines - 1
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
2
If an HR-TFT panel is selected, the following formula must also apply.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
3
See Section 6.5, “Display Interface” on page 52.
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Vertical Display Period Register
REG[34h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
Vertical Display Period bits 9-0
18
17
16
12
11
10
9
8
7
6
2
1
0
n/a
15
14
13
bits 9-0
5
4
3
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total to allow for a sufficient
Vertical Non-Display period.
REG[34h] bits 9:0 = Vertical Display Period in number of lines - 1
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
2 If an HR-TFT panel is selected, the following formula must also apply.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
3
See Section 6.5, “Display Interface” on page 52.
Vertical Display Period Start Position Register
REG[38h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
12
11
10
9
8
7
n/a
15
14
bits 9-0
13
22
21
20
19
18
Vertical Display Period Start Position bits 9-0
6
5
4
3
17
16
1
0
2
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for TFT and HR-TFT panels
in 1 line resolution. For passive LCD panels these bits must be set to 00h.
For passive LCD panels these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VDPS = REG[38h] bits 9-0
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
2
If an HR-TFT panel is selected, the following formula must also apply.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
3
See Section 6.5, “Display Interface” on page 52.
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FPFRAME Register
REG[3Ch]
Default = 00000000h
Read/Write
FPFRAME
Polarity
n/a
31
30
29
28
27
26
25
24
23
12
11
10
9
8
7
n/a
15
14
13
FPFRAME Pulse Width
bits 2-0
n/a
22
21
20
19
FPFRAME Pulse Start Position bits 9-0
6
5
4
3
18
17
16
2
1
0
bit 23
FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be
set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel
(typically FPFRAME, SPS). This bit has no effect for TFT Type 2 panels.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
bits 18-16
FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The vertical sync signal is typically FPFRAME, or SPS, depending on the panel type.
REG[3Ch] bits 2:0 = FPFRAME Pulse Width in number of lines - 1
Note
See Section 6.5, “Display Interface” on page 52.
bits 9-0
FPFRAME Pulse Start Position Bits [9:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
For passive panels, these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VPS = REG[3Ch] bits 9-0
Note
See Section 6.5, “Display Interface” on page 52.
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Main Window Display Start Address Register
REG[40h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bits 16-0
bit 16
25
24
23
22
21
Main Window Display Start Address bits 15-0
9
8
7
6
5
20
19
18
17
16
4
3
2
1
0
Main Window Display Start Address Bits [16:0]
This register specifies the starting address, in DWORDS, for the LCD image in the display
buffer for the main window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on. Calculate the Display Start Address as
follows:
REG[40h] bits 16:0 = image address ÷ 4 (valid only for SwivelView 0°)
Note
For information on setting this register for other SwivelView orientations, see Section
13, “SwivelView™” on page 170.
Main Window Line Address Offset Register
REG[44h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
12
11
10
9
8
7
n/a
15
14
bits 9-0
13
22
21
20
19
Main Window Line Address Offset bits 9-0
6
5
4
3
18
17
16
2
1
0
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in DWORDS, from the beginning of one display line to
the beginning of the next display line in the main window. Note that this is a 32-bit
address increment. Calculate the Line Address Offset as follows:
REG[44h] bits 9:0 = display width in pixels ÷ (32 ÷ bpp)
Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than the
display width and the displayed image becomes a window into the larger virtual image.
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Extended Panel Type Register
REG[48h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
14
13
12
23
22
Compare
n/a
15
24
Data
10
9
8
20
7
6
19
18
17
16
Extended Panel Type bits 3-0
n/a
Invert
Enable
11
21
5
4
3
2
1
0
bit 8
Data Compare Invert Enable
This bit can be used to lower power consumption for TFT Type 2 and TFT Type 3 Interfaces. The Data Compare and Invert function reduces the amount of data toggled by
counting the number of bits that are changed (1 to 0 or 0 to 1) from the previous pixel
data. If more than half of the bits are changed the data is inverted and the lesser amount of
bits are toggled. For all other panel interfaces it has no effect.
When this bit = 0, the Data Compare and Invert functions are disabled.
When this bit = 1, the Data Compare and Invert functions are enabled.
bits 3-0
Extended Panel Type Bits [3:0]
These bits override the setting in REG[0Ch] bits 1-0 and allow selection of the alternate
TFT panel types.
Table 8-11: Extended Panel Type Selection
REG[48h] Bits [3:0]
Panel Type
0000
no effect from REG[0Ch] bits 1-0
0001
TFT Type 2
0010
TFT Type 3
0011
TFT Type 4
0100
Casio TFT
0101 - 1111
Reserved
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8.3.6 Picture-in-Picture Plus (PIP+) Registers
PIP+ Display Start Address Register
REG[50h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bit 16
25
24
23
22
PIP+ Display Start Address bits 15-0
9
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
PIP+ Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the
PIP+ window.
bits 16-0
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
PIP+ Line Address Offset Register
REG[54h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
PIP+ Line Address Offset bits 9-0
18
17
16
12
11
10
9
8
7
6
2
1
0
n/a
15
14
bits 9-0
13
5
4
3
PIP+ Window Line Address Offset Bits [9:0]
These bits are the LCD display’s 10-bit address offset from the starting double-word of
line “n” to the starting double-word of line “n + 1” for the PIP+window. Note that this is a
32-bit address increment.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
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PIP+ X Positions Register
REG[58h]
Default = 00000000h
Read/Write
PIP+ X End Position bits 9-0
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
PIP+ X Start Position bits 9-0
18
17
16
12
11
10
9
8
7
6
2
1
0
n/a
15
14
13
5
4
3
Note
The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is written
and at the next vertical non-display period.
bits 25-16
PIP+ Window X End Position Bits [9:0]
These bits determine the X end position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the X end position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X End Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X end position is incremented by x pixels where x is relative to
the current color depth.
Table 8-12: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (x)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X end position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
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bits 9-0
PIP+ Window X Start Position Bits [9:0]
These bits determine the X start position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the X start position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X Start Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X start position is incremented by x pixels where x is relative to
the current color depth.
Table 8-13: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (x)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X start position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
S1D13A05
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PIP+ Y Positions Register
REG[5Ch]
Default = 00000000h
Read/Write
PIP+ Y End Position bits 9-0
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
PIP+ Y Start Position bits 9-0
18
17
16
12
11
10
9
8
7
6
2
1
0
n/a
15
14
13
5
4
3
Note
1
The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is
written and at the next vertical non-display period.
2
For host bus interfaces using little endian (CNF4 = 0), a write to bits 31-24 causes the
PIP+ Window Y End Position to take effect.
For host bus interfaces using big endian (CNF4 = 1), a write to bits 7-0 causes the PIP+
Window Y End Position to take effect.
bits 25-16
PIP+ Window Y End Position Bits [9:0]
These bits determine the Y end position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the Y end position may not be a
vertical position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the Y End Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y end position is incremented in 1 line increments. For 90° and
270° SwivelView the Y end position is incremented by y pixels where y is relative to the
current color depth.
Table 8-14: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (y)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
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bits 9-0
PIP+ Window Y Start Position Bits [9:0]
These bits determine the Y start position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the Y start position may not be a
vertical position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the Y Start Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y start position is incremented in 1 line increments. For 90° and
270° SwivelView the Y start position is incremented by y pixels where y is relative to the
current color depth.
Table 8-15: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (y)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
S1D13A05
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8.3.7 Miscellaneous Registers
Reserved
REG[60h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
Reserved
27
26
25
24
n/a
15
14
13
12
11
10
9
8
23
Reserved
22
7
6
21
20
19
n/a
5
4
18
3
2
GPIO Status and Control Register
REG[64h]
Default = 20000000h
GPIO6
Input
Enable
GPIO5
Input
Enable
GPIO4
Input
Enable
GPIO3
Input
Enable
GPIO2
Input
Enable
GPIO1
Input
Enable
GPIO0
Input
Enable
31
30
29
28
27
26
25
11
10
9
13
12
1
0
GPIO7
Config
GPIO6
Config
GPIO5
Config
GPIO4
Config
GPIO3
Config
GPIO2
Config
GPIO1
Config
GPIO0
Config
24
23
GPIO7
Control/
Status
22
GPIO6
Control/
Status
21
GPIO5
Control/
Status
20
GPIO4
Control/
Status
19
GPIO3
Control/
Status
18
GPIO2
Control/
Status
17
GPIO1
Control/
Status
16
GPIO0
Control/
Status
8
7
6
5
4
3
2
1
0
n/a
14
16
n/a
Read/Write
GPIO7
Input
Enable
15
17
Reserved
The S1D13A05 GPIO pins default to inputs, however they can be individually configured
to outputs or inputs using the GPIO[7:0] Config bits (bits 23-16). If a GPIO pin is
configured as an input, the input functionality must be enabled using the corresponding
GPIO[7:0] Input Enable pin (see bits 31-24). Once the GPIO pin has been configured, it can
be controlled/read using the GPIO[7:0] Control/Status bits (bits 7-0). See the individual bit
descriptions for further details.
Some GPIOs must be configured as outputs after every RESET for use with some extended
panel types (i.e. Sharp HR-TFT, Casio TFT, etc.). See Table 4-9: “LCD Interface Pin
Mapping,” on page 27 and the individual bit descriptions for bits 7-0 for specific information on each GPIO pin.
bits 31-24
GPIO[7:0] Input Enable bits
These bits individually enable the input function for each GPIO pin (GPIO[7:0]). After
power-on/reset, each bit must be set to a 1 to enable the input function of each GPIO pin
(default is 0 except for GPIO5 which is 1). If the GPIO pin is configured as an output the
GPIO[7:0] Input Enable bit has no effect.
Note
At power-on/reset, the GPIO5 Input Enable bit (bit 29) defaults to 1.
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bits 23-16
GPIO[7:0] IO Configuration
At power-on/reset, the GPIO[7:0] pins default to inputs. These bits individually configure
each GPIO pin as either an output or input.
When these bits = 0, the associated GPIO pin is configured as an input.
When these bits = 1, the associated GPIO pin is configured as an output.
This may be required for some extended panel types (i.e. Sharp HR-TFT, Casio TFT, etc.)
or USB. See Table 4-9: “LCD Interface Pin Mapping,” on page 27 and the individual bit
descriptions for bits 7-0 for specific information on each GPIO pin.
Note
If a GPIO pin is configured as an input, the input function of the GPIO pin must be enabled using the corresponding GPIOx Input Enable bit (bits 31-24) before the input configuration takes effect.
bit 7
GPIO7 IO Control/Status
The following table shows the multiple uses of GPIO7.
Table 8-16: GPIO7 Usage
Function
Pin Usage
GPIO7
USB
bit 6
Output
Input
Write 0
Write 1
Read
GPIO7 driven low
GPIO7 driven high
GPIO7 status returned
not available (used by USBDP) not available (used by USBDP) not available (used by USBDP)
GPIO6 IO Control/Status
The following table shows the multiple uses of GPIO6.
Table 8-17: GPIO6 Usage
Function
Pin Usage
GPIO6
USB
bit 5
Output
Input
Write 0
Write 1
Read
GPIO6 driven low
GPIO6 driven high
GPIO6 status returned
not available (used by USBDM) not available (used by USBDM) not available (used by USBDM)
GPIO5 IO Control/Status
The following table shows the multiple uses of GPIO5.
Table 8-18: GPIO5 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO5
GPIO5 driven low
GPIO5 driven high
GPIO5 status returned
USB
not available (used by
USBDETECT)
not available (used by
USBDETECT)
not available (used by
USBDETECT)
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bit 4
Page 117
GPIO4 IO Control/Status
The following table shows the multiple uses of GPIO4.
Table 8-19: GPIO4 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO4
GPIO4 driven low
GPIO4 driven high
GPIO4 status returned
USB
not available (used by
USBPUP)
not available (used by
USBPUP)
not available (used by
USBPUP)
bit 3
GPIO3 IO Control/Status
The following table shows the multiple uses of GPIO3.
Table 8-20: GPIO3 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO3
GPIO3 driven low
GPIO3 driven high
GPIO3 status returned
Sharp HR-TFT
not available (used by SPL)
not available (used by SPL)
not available (used by SPL)
Casio TFT
not available (used by STH)
not available (used by STH)
not available (used by STH)
TFT Type 2
not available (used by STH)
not available (used by STH)
not available (used by STH)
TFT Type 3
not available (used by EIO)
not available (used by EIO)
not available (used by EIO)
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bit 2
GPIO2 IO Control/Status
The following table shows the multiple uses of GPIO2.
Table 8-21: GPIO2 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO2
GPIO2 driven low
GPIO2 driven high
GPIO2 status returned
Sharp HR-TFT
not available (used by REV)
not available (used by REV)
not available (used by REV)
Casio TFT
not available (used by FRP)
not available (used by FRP)
not available (used by FRP)
TFT Type 2
not available (used by POL)
not available (used by POL)
not available (used by POL)
TFT Type 3
not available (used by POL)
not available (used by POL)
not available (used by POL)
bit 1
GPIO1 IO Control/Status
The following table shows the multiple uses of GPIO1.
Table 8-22: GPIO1 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO1
GPIO1 driven low
GPIO1 driven high
GPIO1 status returned
Sharp HR-TFT
not available (used by CLS)
not available (used by CLS)
not available (used by CLS)
Casio TFT
GRES forced low
GRES enabled
GRES status returned
TFT Type 2
not available (used by AP)
not available (used by AP)
not available (used by AP)
TFT Type 3
OE forced low
OE enabled
OE status returned
bit 0
GPIO0 IO Control/Status
The following table shows the multiple uses of GPIO0.
Table 8-23: GPIO0 Usage
Function
Pin Usage
Output
Input
Write 0
Write 1
Read
GPIO0
GPIO0 driven low
GPIO0 driven high
GPIO0 status returned
Sharp HR-TFT
not available (used by PS)
not available (used by PS)
not available (used by PS)
Casio TFT
not available (used by POL)
not available (used by POL)
not available (used by POL)
TFT Type 2
not available (used by VCLK)
not available (used by VCLK)
not available (used by VCLK)
TFT Type 3
not available (used by CPV)
not available (used by CPV)
not available (used by CPV)
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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GPO Control Register
REG[68h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
GPO10
Control
25
GPO9
Control
24
GPO8
Control
23
GPO7
Control
22
GPO6
Control
21
GPO5
Control
20
GPO4
Control
19
GPO3
Control
18
GPO2
Control
17
GPO1
Control
16
GPO0
Control
12
11
10
9
8
7
6
5
4
3
2
1
0
n/a
15
bit 10
14
13
GPO10 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO10 high and writing a 0 to this bit drives GPO10 low. A read from this
bit returns the status of GPO10.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets PDME = 1 and writing a 0 sets PDME = 0.
bit 9
GPO9 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO9 high and writing a 0 to this bit drives GPO9 low. A read from this bit
returns the status of GPO9.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XSTBY = 1 and writing a 0 sets XSTBY = 0.
bit 8
GPO8 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO8 high and writing a 0 to this bit drives GPO8 low. A read from this bit
returns the status of GPO8.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XOHV = 1 and writing a 0 sets XOHV = 0.
bit 7
GPO7 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO7 high and writing a 0 to this bit drives GPO7 low. A read from this bit
returns the status of GPO7.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XRESV = 1 and writing a 0 sets XRESV = 0.
bit 6
GPO6 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO6 high and writing a 0 to this bit drives GPO6 low. A read from this bit
returns the status of GPO6.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XRESH = 1 and writing a 0 sets XRESH = 0.
Hardware Functional Specification
Issue Date: 2012/02/27
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X40A-A-001-07
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GPO5 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO5 high and writing a 0 to this bit drives GPO5 low. A read from this bit
returns the status of GPO5.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables PCLK2 and writing a 0 forces PCLK2 low.
bit 4
GPO4 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO4 high and writing a 0 to this bit drives GPO4 low. A read from this bit
returns the status of GPO4.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables PCLK1 and writing a 0 forces PCLK1 low.
bit 3
GPO3 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO3 high and writing a 0 to this bit drives GPO3 low. A read from this bit
returns the status of GPO3.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), GPO3 is not
available.
bit 2
GPO2 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO2 low and writing a 0 to this bit drives GPO2 high. A read from
this bit returns the status of GPO2.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables XOEV and writing a 0 sets XOEV = 0.
bit 1
GPO1 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO1 high and writing a 0 to this bit drives GPO1 low. A read from this bit
returns the status of GPO1.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables VCOM and writing a 0 sets VCOM = 0.
bit 0
GPO0 Control
Writing a 1 to this bit drives GPO0 high and writing a 0 to this bit drives GPO0 low. A
read from this bit returns the status of GPO0.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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Page 121
PWM Clock Configuration Register
REG[70h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
14
13
12
21
20
PWM Clock Divide Select
bits 3-0
n/a
15
22
11
10
9
8
7
6
5
4
19
PWM
Clock
Force
High
3
18
17
PWMCLK Source
Select bits 1-0
2
1
16
PWM
Clock
Enable
0
PWM Clock Enable
PWMCLK
Divided
Clock
PWM Clock
Divider
Clock Source /
2m
m = PWM Clock Divide Select value
PWM Duty Cycle
Modulation
to PWMOUT
Duty = n / 256
n = PWM Clock Duty Cycle
frequency =
Clock Source / (2m X 256)
PWM Clock Force High
Figure 8-1: PWM Clock Block Diagram
Note
For further information on PWMCLK, see Section 7.1.4, “PWMCLK” on page 87.
bits 7-4
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.
Table 8-24: PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0]
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
PWM Clock Divide Amount
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Note
This divided clock is further divided by 256 before it is output at PWMOUT.
Hardware Functional Specification
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bit 3
PWM Clock Force High
When this bit = 0, the PWMOUT pin function is controlled by the PWM Clock enable bit.
When this bit = 1, the PWMOUT pin is forced to high.
bits 2-1
PWMCLK Source Select Bits [1:0]
These bits determine the source of PWMCLK.
Table 8-25: PWMCLK Source Selection
REG[70h] bits 2-1
PWMCLK Source
00
CLKI
01
CLKI2
10
BCLK
11
PCLK
Note
For further information on the PWMCLK source select, see Section 7.2, “Clock Selection” on page 88.
bit 0
PWM Clock Enable
When this bit = 0, PWMOUT output acts as a general purpose output pin controllable by
bit 3 of REG[70h].
When this bit = 1, the PWM Clock circuitry is enabled.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
PWMOUT Duty Cycle Register
REG[74h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PWMOUT Duty Cycle bits 7-0
17
16
11
10
9
8
7
6
5
1
0
n/a
15
14
bits 7-0
13
12
4
3
2
PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.
Table 8-26: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0]
PWMOUT Duty Cycle
00h
Always Low
01h
High for 1 out of 256 clock periods
02h
High for 2 out of 256 clock periods
...
...
FFh
High for 255 out of 256 clock periods
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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Scratch Pad A Register
REG[80h]
Default = not applicable
Read/Write
Scratch Pad A bits 31-24
31
30
29
28
27
26
25
15
14
13
12
11
10
9
bits 31-0
24
23
22
Scratch Pad A bits 15-0
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
Scratch Pad A Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hardware.
Note
The contents of the Scratch Pad A register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A05 is reset,
as long as the chip is not powered off.
Scratch Pad B Register
REG[84h]
Default = not applicable
Read/Write
Scratch Pad B bits 31-24
31
30
29
28
27
26
25
15
14
13
12
11
10
9
bits 31-0
24
23
22
Scratch Pad B bits 15-0
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
Scratch Pad B Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hardware.
Note
The contents of the Scratch Pad B register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A05 is reset,
as long as the chip is not powered off.
Scratch Pad C Register
REG[88h]
Default = not applicable
Read/Write
Scratch Pad C bits 31-24
31
30
29
28
27
26
25
15
14
13
12
11
10
9
bits 31-0
24
23
22
Scratch Pad C bits 15-0
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
Scratch Pad C Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hardware.
Note
The contents of the Scratch Pad C register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A04 is reset,
as long as the chip is not powered off.
Hardware Functional Specification
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8.3.8 Extended Panel Registers
HR-TFT CLS Width Register
REG[A0h]
Default = 0000012Ch
Read/Write
n/a
31
30
29
28
n/a
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
bits 8-0
21
20
19
CLS Pulse Width bits 8-0
5
4
3
18
17
16
2
1
0
CLS Pulse Width Bits [8:0]
This register determines the width of the CLS signal in PCLKs.
Note
This register must be programmed such that the following formula is valid.
(REG[A0h] bits 8-0) > 0
HR-TFT PS1 Rising Edge Register
REG[A4h]
Default = 00000032h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
n/a
15
14
13
bits 5-0
12
11
19
18
17
16
1
0
PS1 Rising Edge bits 5-0
10
9
8
7
6
5
4
3
2
PS1 Rising Edge Bits [5:0]
This register determines the number of PCLKs between the CLS falling edge and the PS1
rising edge.
HR-TFT PS2 Rising Edge Register
REG[A8h]
Default = 00000064h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
n/a
15
14
bits 7-0
13
12
20
19
18
17
16
2
1
0
PS2 Rising Edge bits 7-0
11
10
9
8
7
6
5
4
3
PS2 Rising Edge Bits [7:0]
This register determines the number of PCLKs between the LP falling edge and the first
PS2 rising edge.
Note
This register must be programmed such that the following formula is valid.
(REG[A8h] bits 7-0) > 0
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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HR-TFT PS2 Toggle Width Register
REG[ACh]
Default = 0000000Ah
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
n/a
15
14
13
bits 6-0
12
11
20
19
18
17
16
1
0
PS2 Toggle Width bits 6-0
10
9
8
7
6
5
4
3
2
PS2 Toggle Width Bits [6:0]
This register determines the width of the PS2 signal before toggling (in number of
PCLKs).
Note
This register must be programmed such that the following formula is valid.
(REG[ACh] bits 6-0) > 0
HR-TFT PS3 Signal Width Register
REG[B0h]
Default = 00000064h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
n/a
15
14
13
bits 6-0
12
11
20
19
18
17
16
1
0
PS3 Signal Width bits 6-0
10
9
8
7
6
5
4
3
2
PS3 Signal Width Bits [6:0]
This register determines the width of the PS3 signal in PCLKs.
Note
This register must be programmed such that the following formula is valid.
(REG[B0h] bits 6-0) > 0
HR-TFT REV Toggle Point Register
REG[B4h]
Default = 0000000Ah
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
n/a
15
bits 4-0
14
13
12
11
10
19
18
17
16
REV Toggle bits 4-0
9
8
7
6
5
4
3
2
1
0
REV Toggle Bits [4:0]
This register determines the width in PCLKs to toggle the REV signal prior to LP rising
edge.
Hardware Functional Specification
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HR-TFT PS1/2 End Register
REG[B8h]
Default = 00000007h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
n/a
15
14
13
bits 2-0
12
11
10
9
17
16
PS1/2 End bits 2-0
8
7
6
5
4
3
2
1
0
PS1/2 End Bits [2:0]
This register allows the PS signal to continue into the vertical non-display period (in
lines).
Note
This register must be programmed such that the following formula is valid.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
Type 2 TFT Configuration Register
REG[BCh]
Default = 00000000h
Read/Write
n/a
31
POL
Type
15
30
29
n/a
14
13
28
27
AP Pulse Width
bits 2-0
12
11
26
n/a
10
25
24
AP Rising Position
bits 1-0
9
8
23
22
21
n/a
7
6
5
20
19
VCLK Hold
bits 1-0
4
3
18
n/a
2
17
16
VCLK Setup
bits 1-0
1
0
bit 15
POL Type
This bit selects how often the POL signal is toggled. The S1D13A05 GPIO2 pin controls
the POL signal used for the TFT Type 2 Interface. For all other panel interfaces this bit has
no effect.
When this bit = 0, the POL signal is toggled every line.
When this bit = 1, the POL signal is toggled every frame.
bits 13-11
AP Pulse Width Bits [2:0]
These bits specify the AP Pulse Width used for the TFT Type 2 Interface. The S1D13A05
GPIO1 pin controls the AP signal for the TFT Type 2 Interface. For all other panel interfaces it has no effect.
Table 8-27: AP Pulse Width
REG[4Ch] bits 13-11
AP Pulse Width (in PCLKs)
000
20
001
40
010
80
011
120
100
150
101
190
110
240
111
270
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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bits 9-8
Page 127
AP Rising Position Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of FPLINE
(STB) to the rising edge of GPIO1 (AP). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-28: AP Rising Position
bits 4-3
REG[4Ch] bits 9-8
AP Rising Position (in PCLKs)
00
40
01
52
10
68
11
90
VCLK Hold Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of FPLINE
(STB) to the falling edge of GPIO0 (VCLK). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-29: VCLK Hold
bits 1-0
REG[4Ch] bits 4-3
VCLK Hold (in PCLKs)
00
7
01
9
10
12
11
16
VCLK Setup Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of GPIO0
(VCLK) to the rising edge of FPLINE (STB). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-30: VCLK Setup
REG[4Ch] bits 1-0
VCLK Setup (in PCLKs)
00
7
01
9
10
12
11
16
Hardware Functional Specification
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Casio TFT Timing Register
REG[C0h]
Default = 09180E09h
n/a
31
30
n/a
15
14
Read/Write
GPCK Rising Edge to STH Pulse bits 5-0
n/a
29
28
27
26
25
24
GRES Falling Edge to GPCK Rising Edge bits 4-0
23
13
7
12
11
10
9
8
GRES Falling Edge to FRP Toggle Point bits 6-0
22
21
20
19
18
17
16
GPCK Rising Edge to GRES Rising Edge bits 5-0
6
5
n/a
4
3
2
1
0
bits 29-24
GPCK Rising Edge to STH Pulse Bits[5:0]
These bits determine the number of PCLKs from GPCK rising edge to STH pulse.
bits 22-16
GRES Falling Edge to FRP Toggle Point Bits[6:0]
These bits determine the number of PCLKs from GRES falling edge to FRP Toggle point.
bits 13-8
GRES Falling Edge to GPCK Rising Edge Bits[5:0]
These bits determine the number of PCLKs from GRES falling edge to GPCK rising edge.
bits 5-0
GPCK Rising Edge to GRES Rising Edge Bits[5:0]
These bits determine the number of PCLKs from GPCK rising edge to GRES rising edge.
Type 3 TFT Configuration Register 0
REG[D8h]
Default = 00000000h
Read/Write
POL Toggle Position bits 7-0
31
30
29
28
27
26
OE Pulse Width bits 7-0
25
24
23
22
21
20
OE Rising Edge Position bits 7-0
15
14
bits 31-24
13
12
11
10
19
18
17
16
3
2
1
0
n/a
9
8
7
6
5
4
POL Toggle Position Bits [7:0]
These bits specify the toggle position of the POL signal in 2 pixel resolution. The
S1D13A05 GPIO2 pin controls the POL signal used for the TFT Type 3 Interface. This
register has no effect for all other panel interfaces.
POL Toggle Position in pixels = (REG[D8h] bits 31-24) × 2
bits 23-16
OE Pulse Width Bits [7:0]
These bits specify the pulse width of the OE signal in 2 pixel resolution. The S1D13A05
GPIO1 pin controls the OE signal used for the TFT Type 3 Interface. This register has no
effect for all other panel interfaces.
OE Pulse Width in pixels = (REG[D8h] bits 23-16) × 2
bits 15-8
OE Rising Edge Position Bits [7:0]
These bits specify the rising edge position of the OE signal in 2 pixel resolution. The
S1D13A05 GPIO1 pin controls the OE signal used for the TFT Type 3 Interface. This register has no effect for all other panel interfaces.
OE Rising Edge Position in pixels = (REG[D8h] bits 15-8) × 2
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Page 129
Type 3 TFT Configuration Register 1
REG[DCh]
Default = 00000000h
Read/Write
XOEV End Position bits 7-0
31
30
29
15
14
13
bits 31-24
XOEV Start Position bits 7-0
28
27
26
CPV Pulse Width bits 6-0
12
11
10
25
24
23
22
21
20
19
18
VCOM Toggle Position bits 7-0
17
16
9
8
7
6
5
1
0
4
3
2
XOEV End Position Bits [7:0]
These bits specify the falling/rising edge position of the XOEV signal in 2 pixel resolution
(depending on the FPFRAME Pulse Polarity bit in REG[3Ch] bit 23). The S1D13A05
GPO2 pin controls the XOEV signal used for the TFT Type 3 Interface. This register has
no effect for all other panel interfaces.
XOEV Falling Edge Position in pixels = (REG[DCh] bits 31-24) × 2
Note
If this register is set to 0, no pulse is generated.
bits 23-16
XOEV Start Position Bits [7:0]
These bits specify the rising/falling edge position of the XOEV signal in 2 pixel resolution
(depending on the FPFRAME Pulse Polarity bit in REG[3Ch] bit 23). The S1D13A05
GPO2 pin controls the XOEV signal used for the TFT Type 3 Interface. This register has
no effect for all other panel interfaces.
XOEV Rising Edge Position in pixels = (REG[DCh] bits 23-16) × 2
Note
If this register is set to 0, no pulse is generated.
bits 15-8
CPV Pulse Width Bits [7:0]
These bits specify the pulse width of the CPV signal in 2 pixel resolution. The S1D13A05
GPIO0 pin controls the CPV signal used for the TFT Type 3 Interface. This register has no
effect for all other panel interfaces.
CPV Pulse Width in pixels = (REG[DCh] bits 15-8) × 2
bits 7-0
VCOM Toggle Position Bits [7:0]
These bits specify the toggle position of the VCOM signal in 2 pixel resolution. The
S1D13A05 GPO1 pin controls the VCOM signal used for the TFT Type 3 Interface. This
register has no effect for all other panel interfaces.
VCOM Toggle Position in pixels = (REG[DCh] bits 7-0) × 2
Hardware Functional Specification
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Revision 7.7
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Type 3 TFT PCLK Divide Register
REG[E0h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
10
9
8
7
6
n/a
15
14
bit 5-4
13
12
11
21
20
PCLK2 Divide
Rate bits 1-0
5
4
19
18
17
16
PCLK1 Divide Rate bits 3-0
3
2
1
0
PCLK2 Divide Rate Bits [1:0]
These bits specify the divide rate for PCLK2. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
Table 8-31: PCLK2 Divide Rate
bits 3-0
REG[C8h] bits 5-4
PCLK2 Divide Rate
00
64
01
128
10
256
11
512
PCLK1 Divide Rate Bits [3:0]
These bits specify the divide rate for PCLK1. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
Table 8-32: PCLK1 Divide Rate
REG[C8h] bits 3-0
PCLK1 Divide Rate
0000
2
0001
4
0010
8
0011
16
0100
32
0101
64
0110
128
0111
256
1000
512
1001
1024
1010
2048
1011
4096
1100
8192
1101
16384
1110
32768
1111
65536
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Type 3 TFT Partial Mode Display Area Control Register
REG[E4h]
Default = 00000000h
Read/Write
n/a
31
30
29
n/a
15
28
27
26
25
24
23
Partial Mode Display Refresh Cycle bits 5-0
14
13
12
11
10
9
22
21
n/a
8
7
6
20
Partial
Mode
Display
Enable
5
4
19
Partial
Mode
Display
Type
Select
3
18
17
16
Area 2
Display
Enable
Area 1
Display
Enable
Area 0
Display
Enable
2
1
0
bits 13-8
Partial Mode Display Refresh Cycle Bits [5:0]
These bits specify the refresh cycle for the Partial Mode Display. The refresh cycle can be
a value from 0 to 63. This register is used for the TFT Type 3 Interface and has no effect
for all other panel interfaces.
bit 4
Partial Mode Display Enable
This bit enables/disables the Partial Mode Display for the TFT Type 3 and has no effect
for all other panel interfaces.
When this bit = 1, Partial Mode Display is enabled.
When this bit = 0, Partial Mode Display is disabled.
bit 3
Partial Mode Display Type Select
This bit selects the type of partial mode display.
When this bit =0, the Stripe type of partial mode display is selected. If Stripe is enabled
only the Y Position registers are used in calculating the partial display.
When this bit = 1, type Block type of partial mode display is selected. If Block is enabled
both the X and Y Position registers are used in calculating the partial display.
bit 2
Area 2 Display Enable
This bit enables/disables the Area 2 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 2 is enabled.
When this bit = 0, Area 2 is disabled.
bit 1
Area 1 Display Enable
This bit enables/disables the Area 1 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 1 is enabled.
When this bit = 0, Area 1 is disabled.
bit 0
Area 0 Display Enable
This bit enables/disables the Area 0 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 0 is enabled.
When this bit = 0, Area 0 is disabled.
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Type 3 TFT Partial Area 0 Positions Register
REG[E8h]
Default = 00000000h
n/a
31
30
29
n/a
15
Read/Write
Partial Area 0 Y End Position bits 5-0
14
13
28
27
26
25
Partial Area 0 Y Start Position bits 5-0
12
11
10
9
Partial Area 0 X End Position bits 5-0
n/a
24
23
22
21
6
5
n/a
8
7
20
19
18
17
Partial Area 0 X Start Position bits 5-0
4
3
2
1
16
0
bits 29-24
Partial Area 0 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 0 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 21-16
Partial Area 0 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 0 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 13-8
Partial Area 0 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 0 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0
Partial Area 0 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 0 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Type 3 TFT Partial Area 1 Positions Register
REG[ECh]
Default = 00000000h
n/a
31
30
29
n/a
15
Read/Write
Partial Area 1 Y End Position bits 5-0
14
13
28
27
26
25
Partial Area 1 Y Start Position bits 5-0
12
11
10
9
Partial Area 1 X End Position bits 5-0
n/a
24
23
22
21
6
5
n/a
8
7
20
19
18
17
Partial Area 1 X Start Position bits 5-0
4
3
2
1
16
0
bits 29-24
Partial Area 1 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 21-16
Partial Area 1 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 13-8
Partial Area 1 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0
Partial Area 1 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Type 3 TFT Partial Area 2 Positions Register
REG[F0h]
Default = 00000000h
n/a
31
30
29
n/a
15
Read/Write
Partial Area 2 Y End Position bits 5-0
14
13
28
27
26
25
Partial Area 2 Y Start Position bits 5-0
12
11
10
9
Partial Area 2 X End Position bits 5-0
n/a
24
23
22
21
6
5
n/a
8
7
20
19
18
17
Partial Area 2 X Start Position bits 5-0
4
3
2
1
16
0
bits 29-24
Partial Area 2 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 21-16
Partial Area 2 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 13-8
Partial Area 2 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0
Partial Area 2 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Type 3 TFT Command Store Register
REG[F4h]
Default = 00000000h
Read/Write
n/a
31
30
Command 1 Store bits 11-0
29
28
27
26
25
24
23
13
12
11
10
9
8
7
n/a
15
14
22
21
20
Command 0 Store bits 11-0
6
5
4
19
18
17
16
3
2
1
0
bits 27-16
Command 1 Store Bits [11:0]
These bits store command 1 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
bits 11-0
Command 0 Store Bits [11:0]
These bits store command 0 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
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Type 3 TFT Miscellaneous Register
REG[F8h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
n/a
15
14
bits 9-8
13
25
24
23
22
21
Source Driver IC
Number bits 1-0
12
11
10
9
8
20
19
18
17
16
Command
Send
Request
3
2
1
0
n/a
7
6
5
4
Source Driver IC Number Bits [1:0]
These bits contain the number of Source Driver ICs.
Table 8-33: Number of Source Driver ICs
bit 0
REG[E0h] bits 1-0
Source Driver ICs
00
1
01
2
10
3
11
4
Command Send Request
After the CPU sets this bit, the S1D13A05 sends the command in the next non-display
period and clears this bit automatically. This register has no effect for all other panel interfaces.
S1D13A05
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Hardware Functional Specification
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8.4 USB Registers (Offset = 4000h)
The S1D13A05 USB device occupies a 48 byte local register space which can be accessed
by the CPU on the local host interface.
To access the USB registers:
1. A valid USBCLK must be provided.
2. The USBClk Enable bit (REG[4000h] bit 7) must be set to 1 and the USB Setup bit
(REG[4000h] bit 2) must be set to 1. Both bits should be set together.
If any of the above conditions are not true, the USB registers must not be accessed.
Control Register
REG[4000h]
Default = 00h
Read/Write
n/a
15
USBClk Enable
14
Software EOT
13
USB Enable
12
Endpoint 4 Stall
11
Endpoint 3 Stall
10
USB Setup
9
Reserved
8
Reserved
7
6
5
4
3
2
1
0
bit 7
USBClk Enable.
This bit allows the USBClk to be enabled/disabled allowing the S1D13A05 to save power
when the USBClk is not required. The USBClk Enable bit operates independently of the
Power Save Mode Enable bit (REG[14h] bit 4). For example, enabling power save mode
does not disable the USB section of the S1D13A05. It must be disabled using the USBClk
enable bit.
This bit should initially be set with the USB Setup bit. However, it can be disabled/reenabled individually.
When this bit = 1, the USBClk is enabled.
When this bit = 0, the USBClk is disabled.
Note
The USB Registers must not be accessed when this bit is 0.
bit 6
Software EOT
This bit determines the response to an IN request to Endpoint 4 when the transmit FIFO is
empty. If this bit is asserted, the S1D13A05 responds to an IN request to Endpoint 4 with
an ACK and a zero length packet if the FIFO is empty. If this bit is not asserted, the
S1D13A05 responds to an IN request from Endpoint 4 with an NAK if the FIFO is empty,
indicating that it expects to transmit more data. This bit is automatically cleared when the
S1D13A05 responds to the host with a zero length packet when the FIFO is empty.
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bit 5
USB Enable
Any device or configuration descriptor reads from the host will be acknowledged with a
NAK until this bit is set. This allows time for the local CPU to set up the interrupt polling
register, maximum packet size registers, and other configuration registers (e.g. Product ID
and Vendor ID) before the host reads the descriptors.
Note
As the device and configuration descriptors cannot be read by the host until the USB
Enable bit is set, the device enumeration process will not complete and the device will
not be recognized on the USB.
bit 4
Endpoint 4 Stall.
If this bit is set, host bulk reads from the transmit FIFO will result in a STALL acknowledge by the S1D13A05. No data will be returned to the USB host.
bit 3
Endpoint 3 Stall.
If this bit is set, host bulk writes to the receive FIFO will result in a STALL acknowledge
by the S1D13A05. Receive data will be discarded.
bit 2
USB Setup
This bit is used by software to select between GPIO and USB functions for multifunction
GPIO pins (GPIO[7:4]). This bit should be set at the same time as the USBClk Enable bit.
When this bit = 1, the USB function is selected.
When this bit = 0, the GPIO function is selected.
Note
The USB Registers must not be accessed when this bit is 0.
bit 1
Reserved.
This bit must be set to 0.
bit 0
Reserved.
This bit must be set to 0.
Interrupt Enable Register 0
REG[4002h]
Default = 00h
Read/Write
n/a
15
Suspend Request
Interrupt Enable
14
SOF Interrupt
Enable
7
6
13
Reserved
12
Endpoint 4
Interrupt Enable
11
Endpoint 3
Interrupt Enable
10
Endpoint 2
Interrupt Enable
9
Endpoint 1
Interrupt Enable
4
3
2
1
5
8
n/a
0
bit 7
Suspend Request Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB host is requesting the
S1D13A05 USB device to enter suspend mode.
bit 6
SOF Interrupt Enable.
When set, this bit enables an interrupt to occur when a start-of-frame packet is received by
the S1D13A05.
bit 5
Reserved.
This bit must be set to 0.
S1D13A05
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bit 4
Endpoint 4 Interrupt Enable.
When set, this bit enables an interrupt to occur when a USB Endpoint 4 Data Packet has
been sent by the S1D13A05.
bit 3
Endpoint 3 Interrupt Enable.
When set, this bit enables an interrupt to occur when a USB Endpoint 3 Data Packet has
been received by the S1D13A05.
bit 2
Endpoint 2 Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB Endpoint 2 Transmit Mailbox registers have been read by the USB host.
bit 1
Endpoint 1 Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB Endpoint 1 Receive Mailbox registers have been written to by the USB host.
Interrupt Status Register 0
REG[4004h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
Suspend Request
Interrupt Status
SOF Interrupt
Status
Reserved
Endpoint 4
Interrupt Status
Endpoint 3
Interrupt Status
Endpoint 2
Interrupt Status
Endpoint 1
Interrupt Status
7
6
5
4
3
2
1
8
Upper Interrupt
Active
(read only)
0
bit 7
Suspend Request Interrupt Status.
This bit indicates when a suspend-request has been received by the S1D13A05. Writing a
1 clears this bit.
bit 6
SOF Interrupt Status.
This bit indicates when a start-of-frame packet has been received by the S1D13A05. Writing a 1 clears this bit.
bit 5
Reserved.
This bit must be set to 0.
bit 4
Endpoint 4 Interrupt Status.
This bit indicates when a USB Endpoint 4 Data packet has been sent by the S1D13A05.
Writing a 1 clears this bit.
bit 3
Endpoint 3 Interrupt Status (Receive FIFO Valid).
This bit indicates when a USB Endpoint 3 Data packet has been received by the
S1D13A05. No more packets to endpoint 3 will be accepted until this bit is cleared. Writing a 1 clears this bit.
bit 2
Endpoint 2 Interrupt Status.
This bit indicates when the USB Endpoint 2 Mailbox registers have been read by the USB
host. Writing a 1 clears this bit.
bit 1
Endpoint 1 Interrupt Status (Receive Mailbox Valid).
This bit indicates when the USB Endpoint 1 Mailbox registers have been written to by the
USB host. Writing a 1 clears this bit.
bit 0
Upper Interrupt Active (read only).
At least one interrupt status bit is set in register REG[4008h].
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Interrupt Enable Register 1
REG[4006h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
Transmit FIFO
Almost Empty
Interrupt Enable
8
Receive FIFO
Almost Full
Interrupt Enable
4
3
2
1
0
n/a
7
6
bit 1
5
Transmit FIFO Almost Empty Interrupt Enable.
When set, this bit enables an interrupt to be generated when the Transmit FIFO Almost
Empty status bit is set.
Note
The Transmit FIFO Almost Empty threshold must be set greater than zero, as the FIFO
count must drop below the threshold to cause an interrupt.
bit 0
Receive FIFO Almost Full Interrupt Enable.
When set, this bit enables an interrupt to be generated when the Receive FIFO Almost Full
status bit is set.
Note
The Receive FIFO Almost Full threshold must be set less than 64, as the FIFO count
must rise above the threshold to cause an interrupt.
Interrupt Status Register 1
REG[4008h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
n/a
7
6
5
4
3
2
9
Transmit FIFO
Almost Empty
Status
1
8
Receive FIFO
Almost Full Status
0
bit 1
Transmit FIFO Almost Empty Status.
This bit is set when the number of bytes in the Transmit FIFO is equal to the Transmit
FIFO Almost Empty Threshold, and another byte is sent to the USB bus from the FIFO.
Writing a 1 clears this bit.
bit 0
Receive FIFO Almost Full Status.
This bit is set when the number of bytes in the Receive FIFO is equal to the Receive FIFO
Almost Full Threshold, and another byte is received from the USB bus into the FIFO.
Writing a 1 clears this bit.
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Endpoint 1 Index Register
REG[4010h]
Default = 00h
Read/Write
n/a
15
14
13
n/a
12
11
10
9
Endpoint 1 Index bits 2-0 (RO)
8
7
6
5
4
3
2
1
0
bits 2-0
Endpoint 1 Index Register Bits [2:0].
This register determines which Endpoint 1 Receive Mailbox is accessed when the Endpoint 1 Receive Mailbox Data register is read. This register is automatically incremented
after the Endpoint 1 Receive Mailbox Data register is read. This index register wraps
around to zero when it reaches the maximum count (7).
Endpoint 1 Receive Mailbox Data Register
REG[4012h]
Default = 00h
Read Only
n/a
15
14
13
7
6
5
bits 7-0
12
11
Endpoint 1 Receive Mailbox Data bits 7-0
4
3
10
9
8
2
1
0
Endpoint 1 Receive Mailbox Data Bits [7:0].
This register is used to read data from one of the receive mailbox registers. Data is
returned from the register selected by the Endpoint 1 Index Register. The eight receive
mailbox registers are written by a USB bulk transfer to endpoint 1, and can be used to pass
messages from the USB host to the local CPU. The format and content of the messages are
user defined. If enabled, USB writes to this register can generate an interrupt.
Endpoint 2 Index Register
REG[4018h]
Default = 00h
Read/Write
n/a
15
14
13
n/a
12
11
10
9
Endpoint 2 Index bits 2-0
8
7
6
5
4
3
2
1
0
bits 2-0
Endpoint 2 Index Register Bits [2:0].
This register determines which Endpoint 2 Transmit Mailbox is accessed when the Endpoint 2 Transmit Mailbox Data register is read or written. This register is automatically
incremented after the Endpoint 2 Transmit Mailbox Data port is read or written. This
index register wraps around to zero when it reaches the maximum count (7).
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Endpoint 2 Transmit Mailbox Data Register
REG[401Ah]
Default = 00h
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Endpoint 2 Transmit Mailbox Data bits 7-0
4
3
10
9
8
2
1
0
Endpoint 2 Transmit Mailbox Data Bits [7:0].
This register is used to read or write one of the transmit mailbox registers. The register
being accessed is selected by the Endpoint 2 Index register. The eight Transmit Mailbox
registers are written by the local CPU and are read by a USB transfer from endpoint 2. The
format and content of the messages are user defined. If enabled, USB reads from this register can generate an interrupt.
Endpoint 2 Interrupt Polling Interval Register
REG[401Ch]
Default = FFh
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Interrupt Polling Interval bits 7-0
4
3
10
9
8
2
1
0
Interrupt Polling Interval Bits [7:0].
This register specifies the Endpoint 2 interrupt polling interval in milliseconds. It can be
read by the host through the endpoint 2 descriptor.
Endpoint 3 Receive FIFO Data Register
REG[4020h]
Default = 00h
Read Only
n/a
15
14
13
7
6
5
bits7-0
12
11
Endpoint 3 Receive FIFO Data bits 7-0
4
3
10
9
8
2
1
0
Endpoint 3 Receive FIFO Data Bits [7:0].
This register is used by the local CPU to read USB receive FIFO data. The FIFO data is
written by the USB host using bulk or isochronous transfers to endpoint 3.
Endpoint 3 Receive FIFO Count Register
REG[4022h]
Default = 00h
Read Only
n/a
15
14
13
7
6
5
bits 7-0
12
11
Receive FIFO Count bits 7-0
4
3
10
9
8
2
1
0
Receive FIFO Count Bits [7:0].
This register returns the number of receive FIFO entries containing valid entries. Values
range from 0 (empty) to 64 (full). This register is automatically decremented after every
read of the of the Receive FIFO Data Register (REG[4020h]).
S1D13A05
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Endpoint 3 Receive FIFO Status Register
REG[4024h]
Default = 01h
Read/Write
n/a
15
14
13
n/a
7
6
12
11
10
9
Receive FIFO
Flush
Receive FIFO
Overflow
Receive FIFO
Underflow
Receive FIFO Full
(read only)
4
3
2
1
5
8
Receive FIFO
Empty
(read only)
0
bit 4
Receive FIFO Flush.
Writing to this bit causes the receive FIFO to be flushed. Reading this bit always returns a
0.
bit 3
Receive FIFO Overflow.
If set, this bit indicates that an attempt was made by the USB host to write to the receive
FIFO when the receive FIFO was full. Writing a 1 clears this bit.
bit 2
Receive FIFO Underflow.
If set, this bit indicates that an attempt was made to read the receive FIFO when the
receive FIFO was empty. Writing a 1 clears this bit.
bit 1
Receive FIFO Full.
If set, this bit indicates that the receive FIFO is full.
bit 0
Receive FIFO Empty.
If set, this bit indicates that the receive FIFO is empty.
Endpoint 3 Maximum Packet Size Register
REG[4026h]
Default = 08h
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Endpoint 3 Max Packet Size bits 7-0
4
3
10
9
8
2
1
0
Endpoint 3 Max Packet Size Bits [7:0].
This register specifies the maximum packet size for endpoint 3 in units of 8 bytes (default
= 64 bytes). It can be read by the host through the endpoint 3 descriptor.
Endpoint 4 Transmit FIFO Data Register
REG[4028h]
Default = 00h
Write Only
n/a
15
14
13
7
6
5
bits 7-0
12
11
Transmit FIFO Data bits 7-0
4
3
10
9
8
2
1
0
Transmit FIFO Data Bits [7:0].
This register is used by the local CPU to write data to the transmit FIFO. The FIFO data is
read by the USB host using bulk or isochronous transfers from endpoint 4.
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Endpoint 4 Transmit FIFO Count Register
REG[402Ah]
Default = 00h
Read Only
n/a
15
14
13
7
6
5
bits 7-0
12
11
Transmit FIFO Count bits 7-0
4
3
10
9
8
2
1
0
Transmit FIFO Count Bits [7:0].
This register returns the number of transmit FIFO entries containing valid entries. Values
range from 0 (empty) to 64 (full).
Endpoint 4 Transmit FIFO Status Register
REG[402Ch]
Default = 01h
Read/Write
n/a
15
14
n/a
7
13
Transmit FIFO
Valid
12
Transmit FIFO
Flush
11
Transmit FIFO
Overflow
5
4
3
6
10
Reserved
2
9
Transmit FIFO
Full (read only)
8
Transmit FIFO
Empty (read only)
1
0
bit 5
Transmit FIFO Valid.
If set, this bit allows the data in the Transmit FIFO to be read by the next read from the
host. This bit is automatically cleared by a host read. This bit is only used if bit 0 in
USB[403Ah] Index [0Ch] is set.
bit 4
Transmit FIFO Flush.
Writing to this bit causes the transmit FIFO to be flushed. Reading this bit always returns
a 0.
bit 3
Transmit FIFO Overflow.
If set, this bit indicates that an attempt was made by the local CPU to write to the transmit
FIFO when the transmit FIFO was full. Writing a 1 clears this bit.
bit 2
Reserved.
bit 1
Transmit FIFO Full (read only).
If set, this bit indicates that the transmit FIFO is full.
bit 0
Transmit FIFO Empty (read only).
If set, this bit indicates that the transmit FIFO is empty.
Endpoint 4 Maximum Packet Size Register
REG[402Eh]
Default = 08h
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Endpoint 4 Max Packet Size bits 7-0
4
3
10
9
8
2
1
0
Endpoint 4 Max Packet Size Bits [7:0].
This register specifies the maximum packet size for endpoint 4 in units of 8 bytes (default
= 64 bytes). It can be read by the host through the endpoint 4 descriptor.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
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Revision Register
REG[4030h]
Page 143
Default = 01h
Read Only
n/a
15
14
13
12
11
Chip Revision bits 7-0
10
9
8
7
6
5
4
2
1
0
bits 7-0
3
Chip Revision Bits [7:0].
This register returns current silicon revision number of the USB client.
USB Status Register
REG[4032h]
Default = 00h
Read/Write
n/a
15
Suspend Control
7
14
USB Endpoint 4
STALL
13
USB Endpoint 4
NAK
12
USB Endpoint 4
ACK
11
USB Endpoint 3
STALL
10
USB Endpoint 3
NAK
9
USB Endpoint 3
ACK
6
5
4
3
2
1
8
Endpoint 2 Valid
0
bit 7
Suspend Control
If set, this bit indicates that there is a pending suspend request. Writing a 1 clears this bit
and causes the S1D13A05 USB device to enter suspended mode.
bit 6
USB Endpoint 4 STALL
The last USB IN token could not be serviced because the endpoint was stalled
(REG[4000h] bit 4 set), and was acknowledged with a STALL. Writing a 1 clears this bit.
bit 5
USB Endpoint 4 NAK
The last USB packet transmitted (IN packet) encountered a FIFO underrun condition, and
was acknowledged with a NAK. Writing a 1 clears this bit.
bit 4
USB Endpoint 4 ACK
The last USB packet transmitted (IN packet) was successfully acknowledged with an
ACK from the USB host. Writing a 1 clears this bit.
bit 3
USB Endpoint 3 STALL
The last USB packet received (OUT packet) could not be accepted because the endpoint
was stalled (REG[4000h] bit 3 set), and was acknowledged with a STALL. Writing a 1
clears this bit.
bit 2
USB Endpoint 3 NAK
The last USB packet received (OUT packet) could not be accepted, and was acknowledged with a NAK. Writing a 1 clears this bit.
bit 1
USB Endpoint 3 ACK.
The last USB packet received (OUT packet) was successfully acknowledged with an
ACK. Writing a 1 clears this bit.
bit 0
Endpoint 2 Valid.
When this bit is set, the 8-byte endpoint 2 mailbox registers have been written by the local
CPU, but not yet read by the USB host. The local CPU should not write into these registers while this bit is set.
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Frame Counter MSB Register
REG[4034h]
Default = 00h
Read Only
n/a
15
14
13
n/a
12
11
10
9
Frame Counter bits 10-8
8
7
6
5
4
3
2
1
0
Frame Counter LSB Register
REG[4036h]
Default = 00h
Read Only
n/a
15
14
13
7
6
5
bits 10-0
12
11
Frame Counter bits 7-0
4
3
10
9
8
2
1
0
Frame Counter Bits [10:0]
This register contains the frame counter from the most recent start-of-frame packet.
Extended Register Index
REG[4038h]
Default = 00h
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Extended Register Index bits 7-0
4
3
10
9
8
2
1
0
Extended Register Index Bits [7:0]
This register selects which extended data register is accessed when the REG[403Ah] is
read or written.
Extended Register Data
REG[403Ah]
Default = 04h
Read/Write
n/a
15
14
13
7
6
5
bits 7-0
12
11
Extended Data bits 7-0
4
3
10
9
8
2
1
0
Extended Data Bits [7:0]
This port provides access to one of the extended data registers. The index of the current
register is held in REG[4038h].
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Vendor ID MSB
REG[403Ah], Index[00h]
Page 145
Default = 04h
Read/Write
Vendor ID bits 15-8
7
6
5
Vendor ID LSB
REG[403Ah], Index[01h]
4
3
2
1
Default = B8h
0
Read/Write
Vendor ID bits 7-0
7
6
bits 15-0
5
4
3
2
1
0
Vendor ID Bits [15:0]
These registers determine the Vendor ID returned in a “Get Device Descriptor” request.
Product ID MSB
REG[403Ah], Index[02h]
Default = 88h
Read/Write
Product ID bits 15-8
7
6
5
Product ID LSB
REG[403Ah], Index[03h]
4
3
2
1
Default = 21h
0
Read/Write
Product ID bits 7-0
7
6
bits 15-0
5
4
3
2
1
0
Product ID Bits [15:0]
These registers determine the Product ID returned in a “Get Device Descriptor” request.
Release Number MSB
REG[403Ah], Index[04h]
Default = 01h
Read/Write
Release Number bits 15-8
7
6
5
Release Number LSB
REG[403Ah], Index[05h]
4
3
2
1
Default = 00h
0
Read/Write
Release Number bits 7-0
7
bits 15-0
6
5
4
3
2
1
0
Release Number Bits [15:0]
These registers determine the device release number returned in a “Get Device Descriptor” request.
Hardware Functional Specification
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Receive FIFO Almost Full Threshold
REG[403Ah], Index[06h]
Default = 3Ch
Read/Write
n/a
7
Receive FIFO Almost Full Threshold bits 5-0
6
bits 5-0
5
4
3
2
1
0
Receive FIFO Almost Full Threshold Bits [5:0]
This register determines the threshold at which the receive FIFO almost full status bit is
set.
Note
The Receive FIFO Almost Full threshold must be set less than 64, as the FIFO count
must rise above the threshold to cause an interrupt.
Transmit FIFO Almost Empty Threshold
REG[403Ah], Index[07h]
Default = 04h
Read/Write
n/a
7
Transmit FIFO Almost Empty Threshold bits 5-0
6
bits 5-0
5
4
3
2
1
0
Transmit FIFO Almost Empty Threshold Bits [5:0].
This register determines the threshold at which the transmit FIFO almost empty status bit
is set.
Note
The Transmit FIFO Almost Empty threshold must be set greater than zero, as the FIFO
count must drop below the threshold to cause an interrupt.
USB Control
REG[403Ah], Index[08h]
Default = 01h
Read/Write
USB String
Enable
n/a
7
6
bit 0
5
4
3
2
1
0
USB String Enable.
When set, this bit allows the default Vendor and Product ID String Descriptors to be
returned to the host. When this bit is cleared, the string index values in the Device
Descriptor are set to zero.
Maximum Power Consumption
REG[403Ah], Index[09h]
Default = FAh
Read/Write
Maximum Current bits 7-0
7
bits 7-0
6
5
4
3
2
1
0
Maximum Current Bits [7:0].
The amount of current drawn by the peripheral from the USB port in increments of 2 mA.
The S1D13A05 reports this value to the host controller in the configuration descriptor.
The default and maximum value is 500 mA (FAh * 2 mA).
In order to comply with the USB specification the following formula must apply:
REG[403Ah] index[09h] ≤ FAh.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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Packet Control
REG[403Ah], Index[0Ah]
Page 147
Default = 00h
Read/Write
EP4 Data Toggle
EP3 Data Toggle
EP2 Data Toggle
EP1 Data Toggle
Reserved
Reserved
n/a
Reserved
7
6
5
4
3
2
1
0
bit 7
EP4 Data Toggle Bit.
Contains the value of the Data Toggle bit to be sent in response to the next IN token to
endpoint 4 from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
bit 6
EP3 Data Toggle Bit.
Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 3
from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
bit 5
EP2 Data Toggle Bit.
Contains the value of the Data Toggle bit to be sent in response to the next IN token to
endpoint 2 from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
bit 4
EP1 Data Toggle Bit.
Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 1
from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
bit 3
Reserved.
This bit must be set to 0.
bit 2
Reserved.
This bit must be set to 0.
bit 0
Reserved.
This bit must be set to 0.
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Reserved
REG[403Ah], Index[0Bh]
Default = 00h
Read/Write
n/a
7
6
bit 0
5
Reserved
4
3
2
1
0
Reserved.
This bit must be set to 0.
FIFO Control
REG[403Ah], Index[0Ch]
Default = 00h
Read/Write
Transmit FIFO
Valid Mode
n/a
7
6
bit 0
5
4
3
2
1
0
Transmit FIFO Valid Mode.
When set, this bit causes a NAK response to a host read request from the transmit FIFO
(EP4) unless the FIFO Valid bit (in register EP4STAT) is set. When this bit is cleared, any
data waiting in the transmit FIFO will be sent in response to a host read request, and the
FIFO Valid bit is ignored.
USBFC Input Control Register
REG[4040h]
Default = 0Dh
Read/Write
n/a
15
n/a
14
USCMPEN
13
Reserved
12
Reserved
11
ISO
10
WAKEUP
9
Reserved
8
Reserved
7
6
5
4
3
2
1
0
These bits control inputs to the USB module.
bit 6
USCMPEN
This bit controls the USB differential input receiver.
0 = differential input receiver disabled
1 = differential input receiver enabled
bits 5
Reserved.
This bit must be set to 0.
bits 4
Reserved.
This bit must be set to 0.
bit 3
ISO
This bits selects between isochronous and bulk transfer modes for the FIFOs (Endpoint 3
and Endpoint 4).
0 = Isochronous transfer mode
1 = Bulk transfer mode
bit 2
WAKEUP
This active low bit initiates a USB remote wake-up.
0 = initiate USB remote wake-up
1 = no action
S1D13A05
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Page 149
bit 1
Reserved.
This bit must be set to 0.
bit 0
Reserved.
This bit must be set to 0.
Reserved
REG[4042h]
n/a
15
14
13
12
11
10
9
8
3
2
1
0
n/a
7
6
5
4
Pin Input Status / Pin Output Data Register
REG[4044h]
Default = depends on USB input pin state
Read/Write
n/a
15
14
13
12
11
10
n/a
7
6
5
4
3
2
9
USBDETECT
Input Pin Status
(read only)
1
8
USBPUP Output
Pin Status
0
These bits can generate interrupts.
bit 1
USBDETECT Input Pin Status
This read-only bit indicates the status of the USBDETECT input pin after a steady-state
period of 0.5 seconds.
bit 0
USBPUP Output Pin Status
This bit controls the state of the USBPUP output pin.
This bit must be set to 1 to enable the USB interface and USB registers. See the S1D13A05
Programming Notes and Examples, document number X40-A-G-003-xx for further information on this bit.
Interrupt Control Enable Register 0
REG[4046h]
Default = 00h
Read/Write
n/a
15
n/a
7
14
USB Host
Connected
6
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
USBRESET
Reserved
5
4
3
2
1
0
These bits enable interrupts from the corresponding bit of the Interrupt Control Status/Clear
Register 0.
0 = corresponding interrupt bit disabled (masked).
1 = corresponding interrupt bit enabled.
Hardware Functional Specification
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Interrupt Control Enable Register 1
REG[4048h]
Default = 00h
Read/Write
n/a
15
n/a
7
14
USB Host
Disconnect
6
13
Reserved
5
12
Device
Configured
4
11
10
9
8
Reserved
Reserved
Reserved
INT
3
2
1
0
These bits enable interrupts from the corresponding bit of the Interrupt Control Status/Clear
Register 1.
0 = corresponding interrupt bit disabled (masked).
1 = corresponding interrupt bit enabled.
Interrupt Control Status/Clear Register 0
REG[404Ah]
Default = 00h
Read/Write
n/a
15
n/a
7
14
USB Host
Connected
6
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
USBRESET
Reserved
5
4
3
2
1
0
On reads, these bits represent the interrupt status for interrupts caused by low-to-high
transitions on the corresponding signals.
0 (read) = no low-to-high event detected on the corresponding signal.
1 (read) = low-to-high event detected on the corresponding signal.
On writes, these bits clear the corresponding interrupt status bit.
0 (write) = corresponding interrupt status bit unchanged.
1 (write) = corresponding interrupt status bit cleared to zero.
These bits must always be cleared via a write to this register before first use. This will
ensure that any changes on input pins during system initialization do not generate erroneous
interrupts. The interrupt bits are used as follows.
bit 6
USB Host Connected
Indicates the USB device is connected to a USB host.
bit 5
Reserved.
Must be set to 0.
bit 4
Reserved.
Must be set to 0.
bit 3
Reserved.
Must be set to 0.
bit 2
Reserved.
Must be set to 0.
bit 1
USBRESET
Indicates the USB device is reset using the RESET# pin or using the USB port reset.
S1D13A05
X40A-A-001-07
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bit 0
Page 151
Reserved.
Must be set to 0.
Interrupt Control Status/Clear Register 1
REG[404Ch]
Default = 00h
Read/Write
n/a
15
n/a
7
14
USB Host
Disconnected
6
13
Reserved
5
12
Device
Configured
11
10
9
8
Reserved
Reserved
Reserved
INT
3
2
1
0
4
On reads, these bits represent the interrupt status for interrupts caused by high-to-low
transitions on the corresponding signals.
0 (read) = no high-to-low event detected on the corresponding signal.
1 (read) = high-to-low event detected on the corresponding signal.
On writes, these bits clear the corresponding interrupt status bit.
0 (write) = corresponding interrupt status bit unchanged.
1 (write) = corresponding interrupt status bit cleared to zero.
These bits must always be cleared via a write to this register before first use. This will
ensure that any changes on input pins during system initialization do not generate erroneous
interrupts. The interrupt bits are used as follows.
bit 6
USB Host Disconnected
Indicates the USB device is disconnected from a USB host.
bit 5
Reserved.
Must be set to 0.
bit 4
Device Configured.
Indicates the USB device has been configured by the USB host.
bit 3
Reserved.
Must be set to 0.
bit 2
Reserved.
Must be set to 0.
bit 1
Reserved.
Must be set to 0.
bit 0
INT
Indicates an interrupt request originating from within the USB registers (REG[4000h] to
REG[403Ah]).
Hardware Functional Specification
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Interrupt Control Masked Status Register 0
REG[404Eh]
Default = 00h
Read Only
n/a
15
n/a
7
14
USB Host
Connected
6
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
USBRESET
Reserved
5
4
3
2
1
0
These read-only bits represent the logical AND of the corresponding Interrupt Control
Status/Clear Register 0 (REG[404Ah])and the Interrupt Control Enable Register 0
(REG[4046h]).
Interrupt Control Masked Status Register 1
REG[4050h]
Default = 00h
Read Only
n/a
15
n/a
7
14
USB Host
Disconnected
6
13
12
Device
Configured
Reserved
5
4
11
10
9
8
Reserved
Reserved
Reserved
INT
3
2
1
0
These read-only bits represent the logical AND of the corresponding Interrupt Control
Status/Clear Register 1 (REG[404Ch]) and the Interrupt Control Enable Register 1
(REG[4048h]).
USB Software Reset Register
REG[4052h]
Default = 00h
Write Only
n/a
15
14
13
7
6
5
bits 7-0
12
11
USB Software Reset (Code = 10100100) bits 7-0
4
3
10
9
8
2
1
0
USB Software Reset Bits [7:0] (Write Only)
When the specific code of 10100100b is written to these bits the USB module of the
S1D13A05 is reset. Use of the above code avoids the possibility of accidently resetting the
USB.
USB Wait State Register
REG[4054h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
4
3
2
n/a
7
bits 1-0
6
5
9
8
USB Wait State bits 1-0
1
0
USB Wait State Bits [1:0]
This register controls the number of wait states the S1D13A05 uses for its internal USB
support. For all bus interfaces supported by the S1D13A05 these bits must be set to 01.
S1D13A05
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Page 153
8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h)
These registers control the S1D13A05 2D Acceleration engine. For detailed BitBLT
programming instructions, see the S1D13A05 Programming Notes and Examples,
document number X40A-G-003-xx.
BitBLT Control Register
REG[8000h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
Color
Format
Select
Dest
Linear
Select
Source
Linear
Select
23
22
21
20
19
18
17
16
BitBLT
Enable
(WO)
7
6
5
4
3
2
1
0
n/a
15
14
13
12
11
10
9
8
bit 18
BitBLT Color Format Select
This bit selects the color format that the 2D operation is applied to.
When this bit = 0, 8 bpp (256 color) format is selected.
When this bit = 1, 16 bpp (64K color) format is selected.
bit 17
BitBLT Destination Linear Select
When this bit = 1, the Destination BitBLT is stored as a contiguous linear block of
memory.
When this bit = 0, the Destination BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
bit 16
BitBLT Source Linear Select
When this bit = 1, the Source BitBLT is stored as a contiguous linear block of memory.
When this bit = 0, the Source BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
bit 0
BitBLT Enable
This bit is write only.
Setting this bit to 1 begins the 2D BitBLT operation. This bit must not be set to 0 while a
BitBLT operation is in progress.
Note
To determine the status of a BitBLT operation use the BitBLT Busy Status bit
(REG[8004h] bit 0).
Hardware Functional Specification
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BitBLT Status Register
REG[8004h]
Default = 00000000h
n/a
31
30
Read Only
n/a
Number of Used FIFO Entries
29
28
27
26
25
24
23
n/a
15
14
13
12
11
10
9
8
22
FIFO
Not
Empty
7
6
Number of Free FIFO Entries (0 means full)
21
FIFO
Half Full
5
20
FIFO
Full
Status
19
4
3
18
17
16
BitBLT
Busy
Status
1
0
n/a
2
bits 28-24
Number of Used FIFO Entries Bits [4:0]
These bits indicate the minimum number of FIFO entries currently in use (there may be
more values in internal pipeline stages).
bits 20-16
Number of Free FIFO Entries Bits [4:0]
These bits indicate the number of empty FIFO entries available. If these bits return a 0, the
FIFO is full.
bit 6
BitBLT FIFO Not-Empty Status
This is a read-only status bit.
When this bit = 0, the BitBLT FIFO is empty.
When this bit = 1, the BitBLT FiFO has at least one data.
To reduce system memory read latency, software can monitor this bit prior to a BitBLT
read burst operation.
The following table shows the number of words available in BitBLT FIFO under different
status conditions.
Table 8-34: BitBLT FIFO Words Available
BitBLT FIFO Not Number of Words
BitBLT FIFO Half
BitBLT FIFO Full
available in BitBLT
Empty Status
Full Status
Status
FIFO
(REG[8004h] Bit 4) (REG[8004h] Bit 5) (REG[8004h] Bit 6)
0
0
0
0
0
0
1
1 to 6
0
1
1
7 to 14
1
1
1
15 to 16
bit 5
BitBLT FIFO Half Full Status
This is a read-only status bit.
When this bit = 1, the BitBLT FIFO is half full or greater than half full.
When this bit = 0, the BitBLT FIFO is less than half full.
bit 4
BitBLT FIFO Full Status
This is a read-only status bit.
When this bit = 1, the BitBLT FIFO is full.
When this bit = 0, the BitBLT FIFO is not full.
S1D13A05
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Issue Date: 2012/02/27
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bit 0
Page 155
BitBLT Busy Status
This bit is a read-only status bit.
When this bit = 1, the BitBLT operation is in progress.
When this bit = 0, the BitBLT operation is complete.
Note
During a BitBLT Read operation, the BitBLT engine does not attempt to keep the FIFO
full. If the FIFO becomes full, the BitBLT operation stops temporarily as data is read
out of the FIFO. The BitBLT will restart only when less than 14 values remain in the
FIFO.
BitBLT Command Register
REG[8008h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
BitBLT ROP Code bits 3-0
25
24
23
22
21
20
19
9
8
7
6
5
4
3
n/a
15
14
13
bits 19-16
12
11
10
18
17
16
BitBLT Operation bits 3-0
2
1
0
BitBLT Raster Operation Code/Color Expansion Bits [3:0]
ROP Code for Write BitBLT and Move BitBLT. Bits 2-0 also specify the start bit position
for Color Expansion.
Table 8-35 : BitBLT ROP Code/Color Expansion Function Selection
BitBLT ROP Code Bits
[3:0]
Boolean Function for Write
BitBLT and Move BitBLT
Boolean Function for
Pattern Fill
Start Bit Position for Color
Expansion
0000
0 (Blackness)
0 (Blackness)
bit 0
0001
~S . ~D or ~(S + D)
~P . ~D or ~(P + D)
bit 1
0010
~S . D
~P . D
bit 2
0011
~S
~P
bit 3
0100
S . ~D
P . ~D
bit 4
0101
~D
~D
bit 5
0110
S^D
P^D
bit 6
0111
~S + ~D or ~(S . D)
~P + ~D or ~(P . D)
bit 7
1000
S.D
P.D
bit 0
1001
~(S ^ D)
~(P ^ D)
bit 1
1010
D
D
bit 2
1011
~S + D
~P + D
bit 3
1100
S
P
bit 4
1101
S + ~D
P + ~D
bit 5
1110
S+D
P+D
bit 6
1111
1 (Whiteness)
1 (Whiteness)
bit 7
Note
S = Source, D = Destination, P = Pattern.
~ = NOT, . = Logical AND, + = Logical OR, ^ = Logical XOR
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BitBLT Operation Bits [3:0]
Specifies the 2D Operation to be carried out based on the following table.
Table 8-36 : BitBLT Operation Selection
BitBLT Operation Bits [3:0]
BitBLT Operation
0000
Write BitBLT with ROP.
0001
Read BitBLT.
0010
Move BitBLT in positive direction with ROP.
0011
Move BitBLT in negative direction with ROP.
0100
Transparent Write BitBLT.
0101
Transparent Move BitBLT in positive direction.
0110
Pattern Fill with ROP.
0111
Pattern Fill with transparency.
1000
Color Expansion.
1001
Color Expansion with transparency.
1010
Move BitBLT with Color Expansion.
1011
Move BitBLT with Color Expansion and transparency.
1100
Solid Fill.
Other combinations
Reserved
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BitBLT Source Start Address Register
REG[800Ch]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bits 20-0
BitBLT Source Start Address bits 20-16
25
24
23
22
BitBLT Source Start Address bits 15-0
9
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
BitBLT Source Start Address Bits [20:0]
A 21-bit register that specifies the source start address for the BitBLT operation.
If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word
and the other address bits are ignored. In pattern fill operation, the BitBLT Source Start
Address is defined by the following equation.
Value programmed to the Source Start Address Register =
Pattern Base Address + Pattern Line Offset + Pixel Offset.
The following table shows how Source Start Address Register is defined for 8 and 16 bpp
color depths.
Table 8-37 : BitBLT Source Start Address Selection
Color Format
Pattern Base Address[20:0]
Pattern Line Offset[2:0]
Pixel Offset[3:0]
8 bpp
BitBLT Source Start Address[20:6]
BitBLT Source Start
Address[5:3]
BitBLT Source Start
Address[2:0]
16 bpp
BitBLT Source Start Address[20:7]
BitBLT Source Start
Address[6:4]
BitBLT Source Start
Address[3:0]
Note
For further information on the BitBLT Source Start Address register, see the S1D13A05
Programming Notes and Examples, document number X40A-G-003-xx.
BitBLT Destination Start Address Register
REG[8010h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bits 20-0
BitBLT Destination Start Address bits 20-16
25
24
23
22
BitBLT Destination Start Address bits 15-0
9
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
BitBLT Destination Start Address Bits [20:0]
A 21-bit register that specifies the destination start address for the BitBLT operation.
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BitBLT Memory Address Offset Register
REG[8014h]
Default = 00000000h
Read/Write
n/a
31
30
29
n/a
28
27
26
25
24
23
22
21
20
19
BitBLT Memory Address Offset bits 10-0
18
17
16
15
14
13
12
11
10
9
8
7
2
1
0
bits 10-0
6
5
4
3
BitBLT Memory Address Offset Bits [10:0]
These bits are the display’s 11-bit address offset from the starting word of line n to the
starting word of line n + 1. They are used only for address calculation when the BitBLT is
configured as a rectangular region of memory. They are not used for the displays.
BitBLT Width Register
REG[8018h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
12
11
10
9
8
7
6
n/a
15
14
13
bits 9-0
21
20
BitBLT Width bits 9-0
5
4
19
18
17
16
3
2
1
0
BitBLT Width Bits [9:0]
A 10-bit register that specifies the BitBLT width in pixels - 1.
BitBLT width in pixels = (REG[8018h] bits 9-0) + 1
BitBLT Height Register
REG[801Ch]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
12
11
10
9
8
7
6
n/a
15
14
bits 9-0
13
21
20
BitBLT Height bits 9-0
5
4
19
18
17
16
3
2
1
0
BitBLT Height Bits [9:0]
A 10-bit register that specifies the BitBLT height in lines - 1.
BitBLT height in lines = (REG[801Ch] bits 9-0) + 1
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BitBLT Background Color Register
REG[8020h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bits 15-0
25
24
23
22
BitBLT Background Color bits 15-0
9
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
BitBLT Background Color Bits [15:0]
This register specifies the BitBLT background color for Color Expansion or key color for
Transparent BitBLT. For 16 bpp color depths (REG[8000h] bit 18 = 1), bits 15-0 are used.
For 8 bpp color depths (REG[8000h] bit 18 = 0), bits 7-0 are used.
BitBLT Foreground Color Register
REG[8024h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
15
14
13
12
11
10
bits 15-0
25
24
23
22
BitBLT Foreground Color bits 15-0
9
8
7
6
21
20
19
18
17
16
5
4
3
2
1
0
BitBLT Foreground Color Bits [15:0]
This register specifies the BitBLT foreground color for Color Expansion or Solid Fill. For
16 bpp color depths (REG[8000h] bit 18 = 1), bits 15-0 are used. For 8 bpp color depths
(REG[8000h] bit 18 = 0), bits 7-0 are used.
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8.6 2D Accelerator (BitBLT) Data Register Descriptions
The 2D Accelerator (BitBLT) data registers decode AB15-AB0 and require AB16 = 1. The
BitBLT data registers are 32-bit wide. Byte access to the BitBLT data registers is not
allowed.
2D Accelerator (BitBLT) Data Memory Mapped Region Register
AB16-AB0 = 10000h-1FFFEh, even addresses
Read/Write
BitBLT Data bits 31-16
31
30
29
28
27
26
25
15
14
13
12
11
10
9
bits 15-0
24
23
BitBLT Data bits 15-0
8
7
22
21
20
19
18
17
16
6
5
4
3
2
1
0
BitBLT Data Bits [15:0]
This register specifies the BitBLT data. This register is loosely decoded from 10000h to
1FFFEh.
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9 2D Accelerator (BitBLT) Engine
9.1 Overview
The S1D13A05 is designed with a built-in 2D BitBLT engine which increases the performance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths.
The BitBLT engine supports rectangular and linear addressing modes for source and destination in a positive direction for all BitBLT operations except the move BitBLT which also
supports in a negative direction.
The BitBLT operations support byte alignment of all types. The BitBLT engine has a
dedicated BitBLT IO access space. This allows the BitBLT engine to support simultaneous
BitBLT and host side operations.
9.2 BitBLT Operations
The S1D13A05 2D BitBLT engine supports the following BitBLTs. For detailed information on using the individual BitBLT operations, refer to the S1D13A05 Programming
Notes and Examples, document number X40A-G-003-xx.
• Write BitBLT.
• Move BitBLT.
• Solid Fill BitBLT.
• Pattern Fill BitBLT.
• Transparent Write BitBLT.
• Transparent Move BitBLT.
• Read BitBLT.
• Color Expansion BitBLT.
• Move BitBLT with Color Expansion.
Note
For details on the BitBLT registers, see Section 8.5, “2D Acceleration (BitBLT) Registers (Offset = 8000h)” on page 153.
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10 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
f PCLK
FrameRate = -------------------------------( HT ) × ( VT )
Where:
fPCLK
= PClk frequency (Hz)
HT
= Horizontal Total
= ((REG[20h] bits 6-0) + 1) x 8 Pixels
VT
= Vertical Total
= ((REG[30h] bits 9-0) + 1) Lines
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11 Display Data Formats
The following diagrams show the display mode data formats for a little-endian system.
1 bpp:
bit 7
bit 0
Byte 0
A0
A1
A2
A3
A4
A5
A6
Byte 1
A8
A9
A10 A11 A12 A13 A14 A15
Byte 2
A16 A17 A18 A19 A20 A21 A22 A23
P0 P1 P2 P3 P4 P5 P6 P7
A7
LUT
Pn = RGB value from LUT
Index (An)
Host Address
Panel Display
Display Memory
2 bpp:
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
Byte 2
A8
B8
A9
B9
A10 B10 A11 B11
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn)
Host Address
Display Memory
Panel Display
4 bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
A1
B1
C1
D1
Byte 1
A2
B2
C2
D2
A3
B3
C3
D3
Byte 2
A4
B4
C4
D4
A5
B5
C5
D5
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn, Cn, Dn)
Host Address
Display Memory
Panel Display
8 bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
E0
F0
G0
H0
Byte 1
A1
B1
C1
D1
E1
F1
G1
H1
Byte 2
A2
B2
C2
D2
E2
F2
G2
H2
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT Index
(An, Bn, Cn, Dn, En, Fn, Gn, Hn)
Host Address
Panel Display
Display Memory
16 bpp:
Byte 0
5-6-5 RGB
bit 7
bit 0
1
2
0
G0 G0 G0 B04 B03 B02 B01 B00
Byte 1
R04 R03 R02 R01 R00 G05 G04 G03
2
G1
1
0
4
3
2
1
Byte 2
G1
R14 R13 R12 R11 R10 G15 G14 G13
B1
B1
B1
B1
B1
Bypasses LUT
Pn = (Rn4-0, Gn 5-0, Bn4-0)
0
Byte 3
G1
P0 P1 P2 P3 P4 P5 P6 P7
Panel Display
Host Address
Display Buffer
Figure 11-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system.
2. For 16 bpp format, Rn, Gn, Bn represent the red, green, and blue color components.
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12 Look-Up Table Architecture
The following figures are intended to show the display data output path only.
Note
When Video Data Invert is enabled the video data is inverted after the Look-Up Table.
12.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes.
1 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
6-bit Gray Data
00
01
FC
FD
FE
FF
= unused Look-Up Table entries
1 bit-per-pixel data
from Display Buffer
Figure 12-1: 1 Bit-per-pixel Monochrome Mode Data Output Path
2 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Gray Data
FC
FD
FE
FF
= unused Look-Up Table entries
2 bit-per-pixel data
from Display Buffer
Figure 12-2: 2 Bit-per-pixel Monochrome Mode Data Output Path
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4 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Gray Data
FC
FD
FE
FF
4 bit-per-pixel data
from Display Buffer
= unused Look-Up Table entries
Figure 12-3: 4 Bit-per-pixel Monochrome Mode Data Output Path
8 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
6-bit Gray Data
8 bit-per-pixel data
from Display Buffer
Figure 12-4: 8 Bit-per-pixel Monochrome Mode Data Output Path
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16 Bit-Per-Pixel Monochrome Mode
The LUT is bypassed and the green data is directly mapped for this color depth– “Display
Data Formats” on page 163..
12.2 Color Modes
1 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
0
1
6-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
0
1
6-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
0
1
6-bit Blue Data
FC
FD
FE
FF
1 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 12-5: 1 Bit-Per-Pixel Color Mode Data Output Path
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2 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Red Data
00
01
10
11
6-bit Green Data
00
01
10
11
6-bit Blue Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
FC
FD
FE
FF
2 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 12-6: 2 Bit-Per-Pixel Color Mode Data Output Path
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4 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FC
FD
FE
FF
6-bit Blue Data
= unused Look-Up Table entries
4 bit-per-pixel data
from Image Buffer
Figure 12-7: 4 Bit-Per-Pixel Color Mode Data Output Path
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8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
6-bit Red Data
6-bit Green Data
6-bit Blue Data
8 bit-per-pixel data
from Display Buffer
Figure 12-8: 8 Bit-per-pixel Color Mode Data Output Path
16 Bit-Per-Pixel Color Mode
The LUT is bypassed and the color data is directly mapped for this color depth– “Display
Data Formats” on page 163.
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13 SwivelView™
13.1 Concept
Most computer displays are refreshed in landscape orientation – from left to right and top
to bottom. Computer images are stored in the same manner. SwivelView™ is designed to
rotate the displayed image on an LCD by 90°, 180°, or 270° in a counter-clockwise
direction. The rotation is done in hardware and is transparent to the user for all display
buffer reads and writes. By processing the rotation in hardware, SwivelView™ offers a
performance advantage over software rotation of the displayed image.
The image is not actually rotated in the display buffer since there is no address translation
during CPU read/write. The image is rotated during display refresh.
13.2 90° SwivelView™
90° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: B-D-A-C.
physical memory
start address
320
display start address
(panel origin)
C
SwivelView
window
SwivelView
window
B
D
B
A
480
A
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-1: Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.
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13.2.1 Register Programming
Enable 90° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 01.
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “B”. To
calculate the value of the address of pixel “B” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0
= ((image address + (panel height x bpp ÷ 8)) ÷ 4) - 1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) -1
= 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
REG[44h] bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
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13.3 180° SwivelView™
The following figure shows how the programmer sees a 480x320 landscape image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: D-C-B-A.
display start address
(panel origin)
D
B
D
320
320
B
C
A
SwivelView
window
SwivelView
window
A
C
physical memory
start address
480
480
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-2: Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.
13.3.1 Register Programming
Enable 180° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 10.
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “D”. To
calculate the value of the address of pixel “D” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0
= ((image address + (offset x (panel height - 1) + panel width) x bpp ÷ 8) ÷ 4) - 1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) - 1
= 38399 (95FFh)
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Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
= display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ 32 ÷ 8 bpp
= 120 (78h)
REG[44h] bits 9:0
13.4 270° SwivelView™
270° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: C-A-D-B.
physical memory
start address
B
320
display start address
(panel origin)
A
SwivelView
window
SwivelView
window
C
480
A
B
D
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.
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13.4.1 Register Programming
Enable 270° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 11.
Display Start Address
The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “C”. To
calculate the value of the address of pixel “C” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0
= (image address + ((panel width - 1) x offset x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels - 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)
= 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
REG[44h] bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
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14 Picture-in-Picture Plus (PIP + )
14.1 Concept
Picture-in-Picture Plus (PIP+) enables a secondary window (or PIP+ window) within the
main display window. The PIP+ window may be positioned anywhere within the virtual
display and is controlled through the PIP+ Window control registers (REG[50h] through
REG[5Ch]). The PIP+ window retains the same color depth and SwivelView orientation as
the main window.
The following diagram shows an example of a PIP+ window within a main window and the
registers used to position it.
0° SwivelViewTM
PIP+ window y start position
(REG[5Ch] bits 9-0)
panel’s origin
PIP+ window y end position
(REG[5Ch] bits 25-16)
main-window
PIP+ window
PIP+ window x start position
(REG[58h] bits 9-0)
PIP+ window x end position
(REG[58h] bits 25-16)
Figure 14-1: Picture-in-Picture Plus with SwivelView disabled
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14.2 With SwivelView Enabled
14.2.1 SwivelView 90°
90° SwivelViewTM
panel’s origin
PIP+ window x start position
(REG[58h] bits 9-0)
PIP+ window x end position
(REG[58h] bits 25-16)
PIP+ window
PIP+ window y start position
(REG[5Ch] bits 9-0)
PIP+ window y end position
(REG[5Ch] bits 25-16)
main-window
Figure 14-2: Picture-in-Picture Plus with SwivelView 90° enabled
14.2.2 SwivelView 180°
180° SwivelViewTM
PIP+ window x end position
(REG[58h] bits 25-16)
PIP+ window x start position
(REG[58h] bits 9-0)
PIP+ window
main-window
PIP+ window y end position
(REG[5Ch] bits 25-16)
PIP+ window y start position
(REG[5Ch] bits 9-0)
panel’s origin
Figure 14-3: Picture-in-Picture Plus with SwivelView 180° enabled
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14.2.3 SwivelView 270°
270° SwivelViewTM
PIP+ window y end position
(REG[5Ch] bits 25-16)
PIP+ window y start position
(REG[5Ch] bits 9-0)
main-window
PIP+ window
PIP+ window x start position
(REG[58h] bits 9-0)
PIP+ window x end position
(REG[58h] bits 25-16)
panel’s origin
Figure 14-4: Picture-in-Picture Plus with SwivelView 270° enabled
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15 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13A05 to accommodate
the need for power reduction in the hand-held devices market. This mode is enable via the
Power Save Mode Enable bit (REG[14h] bit 4).
Software Power Save Mode saves power by powering down the control signals and
stopping display refresh accesses to the display buffer. For programming information on
disabling the clocks, see the S1D13A05 Programming Notes and Examples, document
number X40A-G-003-xx.
Table 15-1: Power Save Mode Function Summary
Software
Power Save
Normal
IO Access Possible?
Yes
Yes
Memory Access Possible?
Yes1
Yes
Look-Up Table Registers Access Possible?
Yes
Yes
Display Active?
No
Yes
LCD I/F Outputs
Forced Low
Active
PWMCLK
Stopped
Active
GPIO Pins configured for HR-TFT
Forced Low
Active
GPIO Pins configured as GPIOs; Access Possible?
Yes2
Yes
3
Yes
USB Running?
Yes
Note
1
When power save mode is enabled, the memory controller is powered down and the
status of the memory controller is indicated by the Memory Controller Power Save Status bit (REG[14h] bit 6). However, memory reads/writes are possible during power save
mode because the S1D13A05 dynamically enables the memory controller for display
buffer accesses.
2 GPIOs can be accessed and if configured as outputs can be changed.
3
The power-down state of the USB section is controlled by the USBClk Enable bit
(REG[4000h] bit 7).
After reset, the S1D13A05 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
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16 USB Considerations
16.1 USB Oscillator Circuit
The following circuit provides an example implementation for using an external oscillator
to drive USBCLK.
USBOSCI
USBOSCO
Rf
Rd
Cg
Cd
Figure 16-1: USB Oscillator Example Circuit
The following values are recommended for a 48MHz fundamental mode oscillator. If an
oscillator of a different value is used, the capacitive and resistive values must be adjusted
accordingly.
Table 16-1: Resistance and Capacitance Values for Example Circuit
Symbol
Value
Rf
1MΩ
Rd
470Ω
Cg
12pF
Cd
12pF
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17 Mechanical Data
1.2max
+0.30
+0.10
10 -0.15
+0.30
10-0.15
0.35 -0.05
SIDE VIEW
+0.10
0.45 -0.05
0.05max
0.1max
TOP VIEW
1.0
0.08
M
6
7
L
K
J
H
G
0.8
F
E
D
C
B
1.0
A
1
2
3
4
5
8
9
10 11
BOTTOM VIEW
All dimensions in mm
Figure 17-1: Mechanical Data PFBGA 121-pin Package
S1D13A05
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18 References
The following documents contain additional information related to the S1D13A05.
Document numbers are listed in parenthesis after the document name. All documents can
be found at the Epson Research and Development Website at www.erd.epson.com.
• S1D13A05 Product Brief (X40A-C-001-xx)
• S1D13A05 Programming Notes And Examples (X40A-G-003-xx)
• S1D13A05 Register Summary (X40A-R-001-xx)
• Interfacing to the Toshiba TMPR3905/3912 Microprocessor (X40A-G-002-xx)
• Interfacing to the PC Card Bus (X40A-G-005-xx)
• S1D13A05 Power Consumption (X40A-G-006-xx)
• Interfacing to the Freescale MCF5307 "Coldfire" Microprocessor (X40A-G-010-xx)
• S1D13A05 Wind River WindML v2.0 Display Drivers (X40A-E-003-xx)
• S5U13A05B00C Rev. 1.0 Evaluation Board User Manual (X40A-G-004-xx)
• 13A05CFG Configuration Utility Users Manual (X40A-B-001-xx)
• 13A05PLAY Diagnostic Utility Users Manual (X40A-B-002-xx)
• 13A05VIEW Demonstration Utility Users Manual (X40A-B-003-xx)
• S5U13A05P00C100 Evaluation Board User Manual (X40A-G-014-xx)
• Errata No. X00Z-P-001 (X00Z-P-001-xx)
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19 Sales and Technical Support
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
214 Devcon Drive
San Jose, CA 95112,USA
Phone: +1-800-228-3964
7F, Jinbao Bldg., No.89 Jinbao St.,
Dongcheng District,
Beijing 100005, CHINA
Phone: +86-10-8522-1199 FAX: +86-10-8522-1125
FAX: +1-408-922-0238
SHANGHAI BRANCH
EUROPE
EPSON EUROPE ELECTRONICS GmbH
Riesstrasse 15, 80992 Munich,
GERMANY
Phone: +49-89-14005-0
FAX: +49-89-14005-110
7F, Block B, High-Tech Bldg., 900, Yishan Road,
Shanghai 200233, CHINA
Phone: +86-21-5423-5577 FAX: +86-21-5423-4677
SHENZHEN BRANCH
12F, Dawning Mansion, Keji South 12th Road,
Hi-Tech Park, Shenzhen 518057, CHINA
Phone: +86-755-2699-3828 FAX: +86-755-2699-3838
EPSON HONG KONG LTD.
Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road,
Kowloon, Hong Kong
Phone: +852-2585-4600
FAX: +852-2827-4346
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110, TAIWAN
Phone: +886-2-8786-6688 FAX: +886-2-8786-6660
EPSON SINGAPORE PTE., LTD.
1 HarbourFront Place,
#03-02 HarbourFront Tower One, Singapore 098633
Phone: +65-6586-5500
FAX: +65-6271-3182
SEIKO EPSON CORP.
KOREA OFFICE
5F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027
FAX: +82-2-767-3677
SEIKO EPSON CORP.
MICRODEVICES OPERATIONS DIVISION
Device Sales & Marketing Dept.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814
FAX: +81-42-587-5117
S1D13A05
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Change Record
X40A-A-001-07
Revision 7.7- Issued: February 27, 2012
• globally remove QFP5-128 package
• section 2.9, remove QFP package to features
• section 4.1.2, remove QFP package pin diagram
• section 4.2, remove QFP package pin descriptions
• section 18, remove QFP package mechanical drawing
X40A-A-001-07
Revision 7.6 - Issued: December 18, 2008
• all changes from the previous revision are in Red
• section 19, updated Sales and Technical Support addresses
X40A-A-001-07
Revision 7.5 - Issued: February 13, 2008
• all changes from the previous revision are in Red
• Release as revision 7.5 to align with Japan numbering
• section 18 References - remove references to obsolete application notes and change
“Interfacing to the Motorola MCF5307...” to “Interfacing to the Freescale MCF5307...”
X40A-A-001-07
Revision 7.04 - Released: September 17, 2007
• all changes from the previous revision are in Red
• section 18, updated Refereces
• section 19, updated Sales and Technical Support addresses
X40A-A-001-07
Revision 7.03 - Released: June 13, 2007
• all changes from the previous revision are in Red
• section 4.2.1, corrected the PFBGA Pin# listing for the DB[15:0] pin description
X40A-A-001-07
Revision 7.02 - Released: February 01, 2007
• all changes from the previous revision are in Red
• section 6.5, changed formula for VPS from “REG[002Ch] bits 9-0” to “REG[003Ch]
bits 9-0”
• section 6.5.1, changed formula for VPS from “REG[002Ch] bits 9-0” to “REG[003Ch]
bits 9-0”
X40A-A-001-07
Revision 7.01, Released: October 3, 2006
• all changes from the previous revision are in Red
• REG[04h] bit 0 - remove reference to CNF7
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• section 19 Sales and Technical Support - update the addresses for North America and
Singapore
X40A-A-001-07
Revision 7, Released: July 7, 2006
• all changes from the previous revision are in Red
• add section 6.2 RESET# Timing
X40A-A-001-06
Revision 6.01
• section 3.1, figure 3-1, changed System Diagram for Generic #1 so that BS# pin is
connected to IOVDD instead of VSS (GND)
• section 4.2.1, table 4-2, changed BS# pin description for Generic #1 so that BS# pin is
connected to IOVDD instead of VSS (GND)
• REG[10h] bits 4-0, updated the Bits-Per-Pixel bit description and clarified the color
depth table
X40A-A-001-06
Revision 6.0
• released as revision 6.0
X40A-A-001-05
Revision 5.01
• section 2.9, added QFP package to features
• section 4.1.2, added QFP package pin diagram
• section 4.2, added QFP package pin descriptions
• section 18, added QFP package mechanical drawing
X40A-A-001-05
Revision 5.0
• released as revision 5.0
X40A-A-001-04
Revision 4.01
• section 4.2.2, for DRDY pin description, removed description for HR-TFT (not used)
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7