HITACHI 2SK2553

2SK2553(L), 2SK2553(S)
Silicon N Channel MOS FET
High Speed Power Switching
ADE-208-357H (Z)
9th. Edition
February 1999
Application
High speed power switching
Features
•
•
•
•
Low on-resistance
R DS(on) = 7 mΩ typ.
High speed switching
4 V gate drive device can be driven from 5 V source
Outline
LDPAK
4
4
1 2
1
2
3
3
D
G
S
1. Gate
2. Drain
3. Source
4. Drain
2SK2553(L), 2SK2553(S)
Absolute Maximum Ratings (Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDSS
60
V
Gate to source voltage
VGSS
±20
V
Drain current
ID
50
A
200
A
50
A
45
A
174
mJ
75
W
Drain peak current
I D(pulse)
Body to drain diode reverse drain current
I DR
Avalanche current
Avalanche energy
I AP
Note 1
Note 3
EAR
Note 3
Note 2
Channel dissipation
Pch
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Notes 1. PW ≤ 10 µs, duty cycle ≤ 1 %
2. Value at Tc = 25 °C
3. Value at Tch = 25 °C, Rg ≥ 50 Ω
2
2SK2553(L), 2SK2553(S)
Electrical Characteristics (Ta = 25°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
60
—
—
V
I D = 10 mA, VGS = 0
Gate to source breakdown
voltage
V(BR)GSS
±20
—
—
V
I G = ±100 µA, VDS = 0
Gate to source leak current
I GSS
—
—
±10
µA
VGS = ±16 V, VDS = 0
Zero gate voltage drain current I DSS
—
—
10
µA
VDS = 60 V, VGS = 0
Gate to source cutoff voltage
VGS(off)
1.0
—
2.0
V
I D = 1 mA, VDS = 10 V
Static drain to source on state
resistance
RDS(on)
—
7
10
mΩ
I D = 25 A
VGS = 10 V Note 1
—
10
16
mΩ
I D = 25 A
VGS = 4 V Note 1
Forward transfer admittance
|yfs|
35
55
—
S
I D = 25 A
VDS = 10 V Note 1
Input capacitance
Ciss
—
3550
—
pF
VDS = 10 V
Output capacitance
Coss
—
1760
—
pF
VGS = 0
Reverse transfer capacitance
Crss
—
500
—
pF
f = 1 MHz
Turn-on delay time
t d(on)
—
35
—
ns
I D = 25 A
Rise time
tr
—
230
—
ns
VGS = 10 V
Turn-off delay time
t d(off)
—
470
—
ns
RL = 1.2 Ω
Fall time
tf
—
360
—
ns
Body to drain diode forward
voltage
VDF
—
0.85
—
V
I F = 50 A, VGS = 0
Body to drain diode reverse
recovery time
t rr
—
135
—
ns
I F = 50 A, VGS = 0
diF / dt = 50 A / µs
Note
1. Pulse Test
See characteristic curves of 2SK2529.
3
2SK2553(L), 2SK2553(S)
Power vs. Temperature Derating
500
20
I D (A)
1
10
Operation in
this area is
limited by R DS(on)
Case Temperature
150
(1
sh
ot
)
)
°C
100
s
s
25
50
µs
m
m
2
0
µs
=
5
=
c
(T
10
0
n
Drain Current
PW
50
10
tio
ra
25
100
pe
50
10
200
O
Channel Dissipation
75
Maximum Safe Operation Area
C
D
Pch (W)
100
1
Ta = 25 °C
0.5
3
30
0.1 0.3
1
10
100
Drain to Source Voltage V DS (V)
200
Tc (°C)
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermal Impedance
γ s (t)
3
Tc = 25°C
1
D=1
0.5
0.3
0.1
0.03
0.01
10 µ
0.2
θ ch – c(t) = γ s (t) • θ ch – c
θ ch – c = 1.67 °C/W, Tc = 25 °C
0.1
0.05
PDM
0.02
1
lse
0.0 t pu
o
h
1s
100 µ
PW
T
PW
T
1m
10 m
Pulse Width
4
D=
100 m
PW (S)
1
10
2SK2553(L), 2SK2553(S)
Avalanche Test Circuit
Avalanche Waveform
EAR =
L
V DS
Monitor
1
2
• L • I AP •
2
VDSS
VDSS – V DD
I AP
Monitor
V (BR)DSS
I AP
Rg
D. U. T
V DS
VDD
ID
Vin
15 V
50 Ω
0
VDD
Switching Time Test Circuit
Waveform
Vout
Monitor
Vin Monitor
90%
D.U.T.
RL
Vin
Vin
10 V
50 Ω
V DD
= 30 V
Vout
10%
10%
90%
td(on)
tr
10%
90%
td(off)
tf
5
2SK2553(L), 2SK2553(S)
Package Dimensions
1.2 ± 0.2
0.4 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
L type
2.54 ± 0.5
(1.4)
(1.5)
(1.5)
1.27 ± 0.2
3.0 +0.3
–0.5
2.59 ± 0.2
4.44 ± 0.2
8.6 ± 0.3
10.0 +0.3
–0.5
10.2 ± 0.3
1.27 ± 0.2
0.76 ± 0.1
1.3 ± 0.2
11.3 ± 0.5
4.44 ± 0.2
11.0 ± 0.5
1.2 ± 0.2
0.86 +0.2
–0.1
8.6 ± 0.3
10.0 +0.3
–0.5
(1.5)
10.2 ± 0.3
(1.4)
Unit: mm
1.3 ± 0.2
0.1 +0.2
–0.1
2.59 ± 0.2
0.4 ± 0.1
0.86 +0.2
–0.1
2.54 ± 0.5
S type
Hitachi Code
EIAJ
JEDEC
6
LDPAK
—
—
Cautions
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