TI SNJ54ALS569AJ

SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). Asynchronous (direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
RCO
CCO
OE
QA
QB
QC
QD
ENT
LOAD
SN54ALS569A . . . FK PACKAGE
(TOP VIEW)
B
C
D
ENP
ACLR
3
RCO
The SN74ALS568A decade counter and
′ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
U/D
CLK
A
B
C
D
ENP
ACLR
SCLR
GND
U/D
VCC
description
SN54ALS569A . . . J PACKAGE
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE
(TOP VIEW)
A
CLK
•
•
•
•
3-State Q Outputs Drive Bus Lines Directly
Counter Operation Independent of 3-State
Output
Fully Synchronous Clear, Count, and Load
Asynchronous Clear Is Also Provided
Fully Cascadable
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
CCO
OE
QA
QB
QC
SCLR
GND
LOAD
ENT
QD
•
•
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active
until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
FUNCTION TABLE
INPUTS
2
OPERATION
OE
ACLR
SCLR
LOAD
ENT
ENP
U/D
CLK
H
X
X
X
X
X
X
X
Q outputs disabled
L
L
X
X
X
X
X
X
Asynchronous clear
L
H
L
X
X
X
X
↑
Synchronous clear
L
H
H
L
X
X
X
↑
Load
L
H
H
H
L
L
H
↑
Count up
L
H
H
H
L
L
L
↑
Count down
L
H
H
H
H
X
X
X
Inhibit count
L
H
H
H
X
H
X
X
Inhibit count
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic symbols†
SN74ALS568A
17
OE
1
U/D
CLK
2
CTRDIV10
EN10
M1 [UP]
M2 [DOWN]
C5/1,4,7,8,+/2,4,7,8–
Z6
12
ENT
ENP
SCLR
7
9
11
LOAD
8
ACLR
A
B
C
D
3
6,7,8,9
G7
1,7 (CT=9) G9
2,7 (CT=0) G9
G8
18
19
CCO
RCO
5CT=0
M3 [LOAD]
M4 [COUNT]
CT=0
3,5D
10
16
4
15
5
14
6
13
QA
QB
QC
QD
′ALS569A
17
OE
1
U/D
CLK
2
12
ENT
ENP
SCLR
7
9
11
LOAD
8
ACLR
A
B
C
D
3
CTRDIV16
EN10
M1 [UP]
M2 [DOWN]
C5/1,4,7,8,+/2,4,7,8–
Z6
6,7,8,9
G7
1,7 (CT=15) G9
2,7 (CT=0) G9
G8
18
19
CCO
RCO
5CT=0
M3 [LOAD]
M4 [COUNT]
CT=0
3,5D
10
16
4
15
5
14
6
13
QA
QB
QC
QD
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic)
SN74ALS568A
OE
U/D
CLK
ENT
ENP
17
1
2
12
18
19
SCLR
LOAD
ACLR
A
9
8
3
15
QB
14
QC
6
C1
1D
R
4
QA
5
C1
1D
R
D
16
4
C1
1D
R
C
RCO
11
C1
1D
R
B
CCO
7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
QD
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic) (continued)
′ALS569A
OE
U/D
CLK
ENT
ENP
17
1
2
12
18
19
SCLR
LOAD
ACLR
A
9
8
3
QA
15
QB
5
C1
1D
R
D
16
4
C1
1D
R
C
RCO
11
C1
1D
R
B
CCO
7
14
QC
6
C1
1D
R
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
QD
5
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
typical load, count, and inhibit sequences
SN74ALS568A
OE
ÌÌ
ÌÌ
ÌÌ ÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌ
ÌÌ ÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ACLR
SCLR
LOAD
ENP
Don’t Care
ENT
Don’t Care
Don’t Care
U/D
CLK
A
Don’t Care
Don’t Care
B
Don’t Care
Don’t Care
C
Don’t Care
Don’t Care
D
Don’t Care
Don’t Care
QA
Hi Z
QB
Hi Z
QC
Hi Z
QD
Hi Z
RCO
CCO
1
2
Count
Up
0
7
8
9
0
1
2
Count Up
Async
Clear
6
Sync
Clear
3
4
3
2
1
Count Down
Sync
Load
POST OFFICE BOX 655303
0
• DALLAS, TEXAS 75265
9
8
Inhibit
Counting
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
typical load, count, and inhibit sequences (continued)
′ALS569A
OE
ÌÌ
ÌÌ
ÌÌ ÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌ
ÌÌ ÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ACLR
SCLR
LOAD
ENP
Don’t Care
ENT
Don’t Care
Don’t Care
U/D
CLK
A
Don’t Care
Don’t Care
B
Don’t Care
Don’t Care
C
Don’t Care
Don’t Care
D
Don’t Care
Don’t Care
QA
Hi Z
QB
Hi Z
QC
Hi Z
QD
Hi Z
RCO
CCO
1
2
Count
Up
0
13
14 15
0
1
2
Count Up
Async
Clear
Sync
Clear
3
4
3
2
1
0
Count Down
15 14
Inhibit
Counting
Sync
Load
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS569A . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS568A, SN74ALS569A . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS568A
SN74ALS569A
SN54ALS569A
VCC
VIH
Supply voltage
VIL
Low-level input voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
fclock
l k
Clock frequency
High-level input voltage
Pulse duration
4.5
5
5.5
4.5
5
5.5
2
0
0.8
–1
– 2.6
– 0.4
– 0.4
12
24
4
8
SN74ALS568A
SCLR
22
20
0
20
0
30
mA
MHz
ns
25
CLK high
20
16.5
CLK low
23
16.5
25
20
High
35
30
Low
25
20
Low
20
15
High (inactive)
35
30
Low
20
15
High (inactive)
35
30
U/D
35
30
ACLR inactive
10
10
0
– 55
POST OFFICE BOX 655303
mA
25
CLK low
Operating free-air temperature
V
15
CLK high
Hold time after CLK↑ for any input
V
V
0.7
SN74ALS568A
LOAD
8
MAX
CCO and RCO
ENP ENT
ENP,
th
TA
NOM
Q outputs
Data at A, B, C, D
Setup time before CLK↑
MIN
CCO and RCO
′ALS569A
tsu
MAX
Q outputs
ACLR or LOAD low
tw
NOM
2
′ALS569A
UNIT
MIN
• DALLAS, TEXAS 75265
ns
0
125
0
ns
70
°C
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
MIN
VIK
TYP†
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
Q outputs
VCC = 4
4.5
5V
IOH = – 1 mA
IOH = – 2.6 mA
Q outputs
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
0.25
VCC = 4
4.5
5V
IOL = 4 mA
IOL = 8 mA
0.25
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VI = 0.4 V
All outputs
VOH
VOL
CCO and RCO
IIL
IO‡
ICC
CCO and RCO
Q outputs
VCC = 5
5.5
5V
V,
VCC = 5.5 V
VO = 2
2.25
25 V
SN74ALS568A
SN74ALS569A
SN54ALS569A
TEST CONDITIONS
MAX
MIN
TYP†
– 1.5
VCC – 2
2.4
UNIT
MAX
– 1.5
V
VCC – 2
V
3.3
2.4
0.4
0.4
3.2
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
20
20
µA
– 20
– 20
µA
0.1
0.1
mA
20
20
µA
– 0.2
mA
– 0.2
–15
– 70
–15
– 70
– 20
– 112
– 30
– 112
Outputs high
16
26
16
26
Outputs low
20
32
20
32
mA
mA
Outputs disabled
20
32
20
32
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
SN54ALS569A
MIN
22
CLK
An Q
Any
tPLH
tPHL
CLK
RCO
tPLH
tPHL
CLK
CCO
tPLH
tPHL
U/D
RCO
tPLH
tPHL
ENT
RCO
tPLH
tPHL
ENT
CCO
tPLH
tPHL
ENP
CCO
ACLR
Any Q
OE
An Q
Any
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
30
4
21
4
13
7
19
7
16
12
37
12
28
10
28
10
19
5
17
5
13
6
30
6
25
9
31
9
23
9
33
9
19
6
21
6
15
4
20
4
13
5
18
5
13
9
32
9
23
4
18
4
12
5
18
5
14
9
25
9
20
6
23
6
18
6
29
6
24
1
10
3
13
1
12
OE
Any Q
tPLZ
3
29
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
10
MAX
20
′ALS569A
tPLH
tPHL
tPZL
tPHZ
MIN
SN74ALS568A
fmax
tPHL
tPZH
MAX
UNIT
SN74ALS568A
SN74ALS569A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
1.3 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
[0 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
83025022A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
8302502RA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
8302502SA
ACTIVE
CFP
W
20
1
TBD
Call TI
Level-NC-NC-NC
SN54ALS569AJ
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
SN74ALS568AN
OBSOLETE
PDIP
N
20
TBD
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SN74ALS569ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS569ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS569ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS569ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS569AN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ALS569ANE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ALS569ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS569ANSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54ALS569AFK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS569AJ
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS569AW
ACTIVE
CFP
W
20
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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