TS12A4516,, TS12A4517 www.ti.com ................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES FEATURES 1 • • • • ±1-V to ±6-V Dual-Supply Operation Specified ON-State Resistance: – 25 Ω Max With ±5-V Supply – 35 Ω Max With ±3.3-V Supply – 47 Ω Max With ±1.8-V Supply Specified Low OFF-Leakage Currents: – 5 nA at 25°C – 10 nA at 85°C • • • • • Specified Low ON-Leakage Currents: – 5 nA at 25°C – 10 nA at 85°C Low Charge Injection: 13 pC (±5-V Supply) Fast Switching Speed: tON = 85 ns, tOFF = 50 ns (±5-V Supply) Break-Before-Make Operation (tON > tOFF) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2500-V Human-Body Model (A114-F) – 1000-V Charged-Device Model (C101-C) – 250-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION The TS12A4516/TS12A4517 are single pole/single throw (SPST), low-voltage, dual-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A4516 is normally open (NO). The TS12A4517 is normally closed (NC). These CMOS switches can operate continuously with a dual supplies between ±1 V and ±6 V [(2 V < (V+ – V–) < 12 V]. Each switch can handle rail-to-rail analog signals. The OFF-leakage current maximum is only 5 nA at 25°C or 10 nA at 85°C. For pin-compatible parts for use with single supply, see the TS12A4514/TS12A4515. ORDERING INFORMATION TA PACKAGE SOIC – D –40°C to 85°C SOP (SOT-23) – DBV SOIC – D SOP (SOT-23) – DBV (1) (2) (1) (2) ORDERABLE PART NUMBER Reel of 1500 TS12A4516D Reel of 2500 TS12A4516DR Reel of 3000 TS12A4516DBVR Reel of 1500 TS12A4517D Reel of 2500 TS12A4517DR Reel of 3000 TS12A4517DBVR TOP-SIDE MARKING YD516 9CL_ YD517 9CM_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2009, Texas Instruments Incorporated TS12A4516,, TS12A4517 SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 ................................................................................................................................................. www.ti.com PIN CONFIGURATIONS TS12A4517 D PACKAGE (TOP VIEW) TS12A4516 D PACKAGE (TOP VIEW) TS12A4516 DBV PACKAGE (TOP VIEW) COM 1 8 NO COM 1 8 NC N.C. 2 7 V– N.C. 2 7 V– N.C. 3 6 IN N.C. 3 6 IN V+ 4 5 N.C. V+ 4 5 N.C. COM 1 NO 2 V– 3 TS12A4517 DBV PACKAGE (TOP VIEW) 5 V+ 4 IN COM 1 NC 2 V– 3 5 V+ 4 IN SWITCH STATE INPUT TS12A4516 TS12A4517 LOW OFF ON HIGH ON OFF N.C. = Not internally connected NC = Normally closed NO = Normally open Absolute Minimum and Maximum Ratings (1) (2) voltages referenced to 0 V MIN MAX –0.3 13 V Analog voltage range (3) V– –0.3 V+ + 0.3 V Logic input range V– –0.3 V+ + 0.3 V V+ Supply voltage range VNC VNO VCOM VIN UNIT Continuous current into any terminal ±20 mA Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle) ±30 mA ESD per method 3015.7 >2000 Continuous power dissipation (TA = 70°C) 8-pin SOIC (derate 5.88 mW/°C above 70°C) 471 5-pin SOT23-5 (derate 7.1 mW/°C above 70°C) 571 V mW TA Operating temperature range –40 85 °C Tstg Storage temperature range –65 150 °C 300 °C Lead temperature (soldering, 10 s) (1) (2) (3) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current rating. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 TS12A4516,, TS12A4517 www.ti.com ................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 Electrical Characteristics for ±5-V Supply (1) V+ = 4.5 V to 5.5 V, V– = –4.5 V to –5.5 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP (2) TA MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC ON-state resistance ron ON-state resistance flatness ron(flat) V– V+ V+ = 4.5 V, V– = –4.5 V, VCOM = 3.5 V, ICOM = 20 mA 25°C 12 V+ = 4.5 V, V– = –4.5 V, VCOM = –3.5 V, 0 V, 3.5 V, ICOM = 20 mA 25°C Full 3 Full 20 25 1.2 V Ω 2.5 NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 5.5 V, V– = –5.5 V, VCOM = 4.5 V, VNO or VNC = –4.5 V 25°C 5 Full 10 COM OFF leakage current (3) V+ = 5.5 V, V– = –5.5 V, VCOM = –4.5 V, VNO or VNC = 4.5 V 25°C 5 ICOM(OFF) Full 10 COM ON leakage current (3) V+ = 5.5 V, V– = –5.5 V, VCOM = 5.5 V, VNO or VNC = open 25°C 5 ICOM(ON) Full 10 Ω nA nA nA Digital Control Input (IN) Input logic high VIH Full V+ – 1.5 Input logic low VIL Full V– Input leakage current V Full V+ – 3.5 V 0.010 µA IIH, IIL VIN = V+, 0 V Turn-on time tON See Figure 2 Turn-off time tOFF See Figure 2 Charge injection (4) QC CL = 1 nF, VNO = 0 V, RS = 0 Ω, See Figure 1 25°C –13 pC NO, NC OFF capacitance CNO(OFF), CNC(OFF) f = 1 MHz, See Figure 4 25°C 5.5 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 5.5 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 16 pF VIN = V+, 0 V 25°C 1.5 pF 25°C 464 MHz Dynamic Digital input capacitance CI 25°C 58 Full 75 85 25°C 28 Full 45 50 ns ns Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 1 MHz 25°C –83 dB Total harmonic distortion THD RL = 600 Ω, CL = 15 pF, VNO = 1 VRMS, f = 20 kHz 25°C 0.07 % Supply V+ supply current I+ VIN = 0 V or V+ V– supply current I– VIN = 0 V or V+ (1) (2) (3) (4) 25°C 70 Full 80 25°C –70 Full –80 µA µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 Submit Documentation Feedback 3 TS12A4516,, TS12A4517 SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 ................................................................................................................................................. www.ti.com Electrical Characteristics for ±3.3-V Supply (1) V+ = 3.0 V to 3.6 V, V– = –3.0 V to –3.6, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS TA MIN TYP (2) MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC V– V+ ron V+ = 3.0 V, V– = –3.0 V, VCOM = 3 V, ICOM = 20 mA 25°C ON-state resistance ON-state resistance flatness ron(flat) VCOM = –2 V, 0 V, 2 V, ICOM = 20 mA 25°C Full 4 NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 3.6 V, V– = –3.6 V, VCOM = 3 V, VNO or VNC = –3 V 25°C 5 Full 10 COM OFF leakage current (3) V+ = 3.6 V, V– = –3.6 V, VCOM = –3 V, VNO or VNC = 3 V 25°C 5 ICOM(OFF) Full 10 COM ON leakage current (3) V+ = 3.6 V, V– = –3.6 V, VCOM = 3.6 V, VNO or VNC = open 25°C 5 ICOM(ON) Full 10 17 Full 25 35 1.5 V 3 Ω Ω nA nA nA Digital Control Input (IN) Input logic high VIH Full V+ – 1.5 Input logic low VIL Full V– Input leakage current V Full V+ – 3.5 V 0.01 µA IIH, IIL VIN = V+, 0 V Turn-on time tON see Figure 2 Turn-off time tOFF see Figure 2 Charge injection (4) QC CL = 1 nF, VNO = 0 V, RS = 0 Ω, See Figure 1 25°C –7.5 pC NO, NC OFF capacitance CNO(OFF) CNC(OFF) f = 1 MHz, See Figure 4 25°C 5.5 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 5.5 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 16 pF VIN = V+, 0 V 25°C 1.5 pF Dynamic Digital input capacitance CI 25°C 65 Full 85 95 25°C 37 Full 60 70 ns ns Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C 464 MHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C –83 dB Total harmonic distortion THD RL = 600 Ω, CL = 15 pF, VNO = 1 VRMS, f = 20 kHz 25°C 0.10 % Supply V+ supply current I+ VIN = 0 V or V+ V– supply current I– VIN = 0 V or V+ (1) (2) (3) (4) 4 25°C 40 Full 45 25°C –40 Full 45 µA µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 TS12A4516,, TS12A4517 www.ti.com ................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 Electrical Characteristics for ±1.8-V Supply (1) V+ = 1.65 V to 1.95 V, V– = –1.65 V to –1.95 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS TA MIN TYP (2) MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC V– V+ ron V+ = 1.65 V, V– = –1.65 V, VCOM = 0 V, ICOM = 20 mA 25°C ON-state resistance ON-state resistance flatness V+ = 1.65 V, V– = –1.65 V, VCOM = –1.8 V, 0 V, 1.5 V, ICOM = 20 mA 25°C ron(flat) Full 15 NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 1.95 V, V– = –1.95 V, VCOM = 1.65 V, VNO or VNC = –1.65 V 25°C 5 Full 10 COM OFF leakage current (3) V+ = 1.95 V, V– = –1.95 V, VCOM = –1.65 V, VNO or VNC = 1.65 V 25°C 5 ICOM(OFF) Full 10 COM ON leakage current (3) V+ = 1.95 V, V– = –1.95 V, VCOM = 1.95 V, VNO or VNC = open 25°C 5 ICOM(ON) Full 10 28 Full 40 47 9 V Ω 13 Ω nA nA nA Digital Control Input (IN) Input logic high VIH Full V+ – 1.5 Input logic low VIL Full V– Input leakage current V Full V+ – 3.5 V 0.01 µA IIH, IIL VIN = V+, 0 V Turn-on time (4) tON See Figure 2 Turn-off time (4) tOFF See Figure 2 Charge injection (4) QC CL = 1 nF, See Figure 1 25°C –3.5 pC NO, NC OFF capacitance CNO(OFF), CNC(OFF) f = 1 MHz, See Figure 4 25°C 6 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 6 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 14.5 pF VIN = V+, 0 V 25°C 1.5 pF Dynamic Digital input capacitance CI 25°C 90 Full 120 150 25°C 95 Full 150 200 ns ns Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C 464 MHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 1 MHz 25°C –83 dB Total harmonic distortion THD RL = 600 Ω, CL = 50 pF, VNO = 1 VRMS, f = 20 kHz 25°C 0.37 % Supply V+ supply current I+ VIN = 0 V or V+ V– supply current I– VIN = 0 V or V+ (1) (2) (3) (4) 25°C 20 Full 30 25°C –20 Full –30 µA µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 Submit Documentation Feedback 5 TS12A4516,, TS12A4517 SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 ................................................................................................................................................. www.ti.com PIN DESCRIPTION (1) PIN NO. TS12A4516 (1) 6 TS12A4517 D, P SOT23-5 NAME D, P SOT23-5 DESCRIPTION 1 1 1 1 COM Common 2, 3, 5 – 2, 3, 5 – N.C. No connect (not internally connected) 4 5 4 5 V+ Positive power supply 6 4 6 4 IN Digital control to connect COM to NO or NC 7 3 7 3 V– Negative power supply 8 2 – – NO Normally open – – 8 2 NC Normally closed NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both directions. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 TS12A4516,, TS12A4517 www.ti.com ................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 APPLICATION INFORMATION Power-Supply Considerations The TS12A4516 and TS12A4517 operate with power-supply voltages from ±1 V to ±6 V [(2 V < (V+ – V–) < 12 V], but are tested and specified at ±5V, ±3.3V, and ±1.8V supplies. The pin-compatible TS12A4514 and TS12A4515 are recommended for use when only a single supply is desirable. The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and V–. V+ and V– drive the internal CMOS switches and set their analog voltage limits. Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V+ and V–. One of these diodes conducts if any analog signal exceeds V+ or V–. Virtually all the analog leakage current comes from the ESD diodes to V+ or V–. Although the ESD diodes on a given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V– and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V– pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. V+ and V– also power the internal logic and logic-level translators. The logic-level translators convert the logic levels to switched V+ and V– signals to drive the analog signal gates. Logic-Level Thresholds Since these parts have no ground pin, the logic-level threshold is referenced to V+. The threshold limits are V+ –1.5 V and V+ –3.5 V for V+ levels between 6 V and 3 V. When V+ = 2 V, the logic threshold is approximately 0.6 V. CAUTION: Do not connect the TS12A4516/TS12A4517 V+ to 3 V and then connect the logic-level pins to logic-level signals that operate from 5-V supply. TTL levels can exceed 3 V and violate the absolute maximum ratings, damaging the part and/or external circuits. Test Circuits/Timing Diagrams NO or NC Figure 1. Charge Injection Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 Submit Documentation Feedback 7 TS12A4516,, TS12A4517 SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 ................................................................................................................................................. www.ti.com V+ V+ V+ NO 0V VNO TS12A4516 VIN IN VNOPEAK COM 90% 90% VOUT VOUT V– 50 Ω 50% VIN 35 pF 300 Ω 0V tOFF tON V+ V+ V+ 0V VNO NC TS12A4517 VIN VNOPEAK COM IN 90% VOUT V– 50 Ω 50% VIN VOUT 35 pF 300 Ω 90% 0V tON tOFF Figure 2. Switching Times V+ V+ 10 nF VIN NO or NC TS12A4516 TS12A4517 V+ IN VOUT 50 Ω 50 Ω MEAS REF COM V– 50 Ω 50 Ω Measurements are standardized against short at socket terminals. OFF isolation is measured between COM and OFF terminals on each switch. ON loss is measured between COM and ON terminals on each switch. Signal direction through switch is reversed; worst values are recorded. OFF Isolation = 20log VOUT VIN ON Loss = 20log VOUT VIN Figure 3. OFF Isolation and ON Loss V+ V+ As Required NO or NC TS12A4516 TS12A4517 IN COM V– 1-MHz Capacitance Analyzer Figure 4. NO, NC, and COM Capacitance 8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4516 TS12A4517 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TS12A4516D ACTIVE SOIC D 8 TS12A4516DBVR ACTIVE SOT-23 DBV 5 TS12A4516DG4 ACTIVE SOIC D 8 TS12A4516DR ACTIVE SOIC D TS12A4516DRG4 ACTIVE SOIC TS12A4517D ACTIVE TS12A4517DBVR 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A4517DG4 ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A4517DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TS12A4517DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 75 75 75 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) TS12A4516DBVR SOT-23 DBV 5 3000 180.0 TS12A4516DR SOIC D 8 2500 TS12A4517DR SOIC D 8 2500 9.2 3.23 3.17 1.37 4.0 8.0 Q3 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS12A4516DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TS12A4516DR SOIC D 8 2500 346.0 346.0 29.0 TS12A4517DR SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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