Integrated Circuit Systems, Inc. ICS9248-162 Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 General Description Features The ICS9248-162 is the single chip clock solution for various mobile chipset platforms. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-162 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Up to 137MHz frequency support Spread Spectrum for EMI control Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Provides the following system clocks - 4-CPUs @ 2.5/3.3V, up to 137MHz. (including CPUCLK_F) - 9-SDRAMs @3.3V, up to 137MHz (including SDRAM_F) - 8-PCI @3.3V, CPU/2 or CPU/3 (including 1 free running PCICLK_F) - 1-24/48MHz @3.3V - 1-48MHz @3.3V fixed - 2-REF @3.3V, 14.318MHz. Efficient Power management scheme through PCI and CLK STOP CLOCKS Spread Spectrum ± .25%, & 0 to -0.5% down spread Block Diagram 48MHz 24_48MHz /2 X1 X2 XTAL OSC 2 REF(1:0) BUFFER IN CPUCLK_F PLL1 Spread Spectrum FS(3:0) SEL24_48# STOP STOP LATCH 3 8 CPUCLK (2:0) SDRAM (7:0) SDRAM_F POR CLK_STOP# PCI_STOP# CPU2.5_3.3# Control SDATA SCLK PD# Config. Logic PCI CLOCK DIVDER STOP 7 PCICLK (6:0) PCICLK_F Reg. Power Groups VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F VDD48, GND48 = 48MHz, 24MHz VDDREF, GNDREF = REF, X1, X2 VDDCOR = PLL CORE 9248-162 Rev A 8/31/00 Pin Configuration VDDREF REF0 GNDREF X1 X2 VDDPCI *CPU2.5_3.3#/PCICLK_F *FS3/PCICLK0 GNDPCI *SEL24_48#/PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER IN GNDPCI PCICLK5 PCICLK6 VDDCOR PCI_STOP# *PD# GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9248-162 PLL2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* VDDLCPU CPUCLK_F CPUCLK0 GNDLCPU CPUCLK1 CPUCLK2 CLK_STOP# GNDSDR SDRAM_F SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GNDSDR SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24_48MHz/FS1* 48-Pin SSOP and TSSOP * Internal Pull-up Resistor of 120K to VDD Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-162 Pin Descriptions PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 8 10 18, 17, 13, 12, 11, 15 19 21 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48 P I N NA M E VDDREF REF0 PCI_STOP# GND X1 TYPE PWR OUT IN PWR IN X2 VDDPCI C P U 2 . 5 _ 3 . 3 # 1,2 PCICLK_F FS31,2 OUT PWR IN OUT IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK , nominal 3.3V Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. PCICLK0 OUT PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) SEL24_48#1,2 PCICLK1 IN OUT Selects either 24 or 48MHz when Low =48 MHz PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCICLK (6:2) OUT PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) BUFFER IN VDDCOR IN PWR GND48 PWR Input to Fanout Buffers for SDRAM outputs. Power pin for the PLL core. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 4ms. Ground pin for the 24 & 48MHz output buffers & fixed PLL core. SDRAM (7:0) OUT SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). VDDSDR SDATA SCLK 24_48MHz FS11, 2 48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK [2:0] CPUCLK_F VDDLCPU REF1 FS21, 2 PWR I/O IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK, & SDRAM clocks at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input PD#1 IN Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-162 Functionality VDD = 3.3V±5%, VDDL= 2.5V±5% or 3.3±5%, TA=0 to 70°C Crystal (X1, X2) = 14.31818MHz FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 124.00 120.00 114.99 109.99 105.00 83.31 137.00 75.00 100.00 95.00 97.00 133.33 90.00 96.22 66.82 91.5 PCI (MHz) 41.33 40.00 38.33 36.66 35.00 41.65 34.25 37.50 33.33 31.67 32.33 33.33 30.00 32.07 33.41 30.5 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Bit 7 Bit [2, 6:4] Bit 3 Bit 1 Bit 0 Description 0 - ±0.25% Spread Spectrum Modulation, Center Spread 1 - 0 to -0.5% Down Spread CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 124.00 41.33 0001 120.00 40.00 0010 114.99 38.33 0011 109.99 36.66 0100 105.00 35.00 0101 83.31 41.65 0110 137.00 34.25 0111 75.00 37.50 1000 100.00 33.33 1001 95.00 31.67 1010 97.00 32.33 1011 133.33 33.33 1100 90.00 30.00 1101 96.22 32.07 1110 66.82 33.41 1111 91.5 30.5 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit (2, 6:4) 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs 3 PWD 1 Note1 0 1 0 Notes: 1, Default at Power-up will be for latched logic inputs to define frequency. Bit (2, 6:4) are default to 0010. 2, PWD = Power-Up Default 3, When disabling spread spectrum bit7 needs to be set to 0 to maintain nominal frequency. ICS9248-162 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD 1 1 1 1 1 1 1 1 Description (Reserved) CPUCLK_F (Act/Inact) (Reserved) (Reserved) SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 18 17 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description PCICLK_F (Act/Inact) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 4 ICS9248-162 Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - PWD 1 1 X 1 X 1 X 1 Description (Reserved) (Reserved) (SEL24_48)# (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved) Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) 48MHz (Act/Inact) 24MHz (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 5 ICS9248-162 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 115°C 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL CL = 0 pF; Select @ 66MHz Operating Supply IDD3.3OP CL = 0 pF; Select @ 100MHz Current CL = 0 pF; Select @ 133MHz IDDPD Powerdown Current CL = 0 pF; Input address VDD or GND Input Frequency Fi VDD = 3.3 V Input Capacitance1 Clk Stabilization1 Skew1 1 CIN CINX Logic Inputs X1 & X2 pins TSTAB From VDD = 3.3 V to 1% target Freq. tCPU-PCI1 MIN 2 VSS-0.3 12 27 VT = 1.5 V 1 TYP MAX VDD+0.3 0.8 90 150 120 170 151 180 250 600 14.318 16 36 2.8 UNITS V V mA µA MHz 5 45 pF pF 5.5 ms 4 ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 8 CL = 0 pF; Select @ 66.8 MHz IDDL2.5 Operating SupplyCurren 11 CL = 0 pF; Select @ 100 MHz 17 CL = 0 pF; Select @ 133 MHz IDDLPD Powerdown Current CL = 0 pF; Input address VDD or GND <1 1 t V = 1.5 V; V = 1.25 V 1 2.4 Skew CPU-PCI2 T TL 1 Guaranteed by design, not 100% tested in production. 6 MAX 15 18 20 10 4 UNITS mA µA ns ICS9248-162 Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -20 mA Output High Voltage VOH2A IOL = 12 mA Output Low Voltage VOL2A Output High Current IOH2A VOH = 2.0 V Output Low Current IOL2A VOL = 0.8 V 22 TYP 2.85 0.31 -45 29 MAX 0.4 -27 UNITS V V mA mA tr2A VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns 1 tf2A dt2A VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns 55 % tsk2A VT = 1.5 V 80 175 ps tjcyc-cyc2A VT = 1.5 V 200 250 ps TYP 2.3 0.31 -39 26 MAX UNITS V V mA mA 1.3 1.6 ns 1.4 47.5 47 1.6 55 52 ns 1 Duty Cycle 1 Skew window Jitter, Cycle-to-cycle1 1 MIN 2.4 1 Rise Time Fall Time CONDITIONS VT = 1.5 V 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -12 mA Output High Voltage VOH2B IOL = 12 mA Output Low Voltage VOL2B VOH = 1.7 V Output High Current IOH2B VOL = 0.7 V Output Low Current IOL2B MIN 2 22 1 tr2B VOL = 0.4 V, VOH = 2.0 V 1 tf2B VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, < 133 MHz VT = 1.25 V, >= 133 MHz Rise Time Fall Time CONDITIONS 45 42 0.4 -21 Duty Cycle1 dt2B Skew window1 Jitter, Cycle-to-cycle1 tsk2B VT = 1.25 V 70 175 ps tjcyc-cyc2B VT = 1.25 V 200 300 ps 1 Guaranteed by design, not 100% tested in production. 7 % ICS9248-162 Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -18 mA Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V MAX 0.4 -33 UNITS V V mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns 1 tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns dt1 VT = 1.5 V 50 55 % tsk1 VT = 1.5 V 180 500 ps tj1s1 VT = 1.5 V 15 150 ps tjabs1 VT = 1.5 V -250 75 250 ps MIN 2.4 TYP 3 0.3 -69 42 1 MAX 1.3 UNITS V V mA mA ns 1.3 2 ns 50 55 % 1 Duty Cycle 1 Skew window 1 Jitter, One Sigma Jitter, Absolute1 1 38 TYP 3 0.2 -62 43 1 Rise Time Fall Time MIN 2.4 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew window SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 CONDITIONS IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V 32 0.4 -46 Tf3 VOH = 2.4 V, VOL = 0.4 V Dt3 VT = 1.5 V Tsk3 VT = 1.5 V 185 250 ps Tsk3 VT = 1.5 V 4 5 ns 45 1 Propagation Time (Buffer In to output) 1 Guaranteed by design, not 100% tested in production. 8 ICS9248-162 Electrical Characteristics - 24,48M Hz, REF T A = 0 - 70C; VD D = VD D L = 3.3 V +/-5%; CL = 10 - 20 pF (unles s otherwis e s tated) PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, A bs olute 1 1 1 SYM BOL VO H 5 VO L 5 IO H 5 IO L 5 CONDITIONS IO H = -14 mA IO L = 6 mA VO H = 2.0 V VO L = 0.8 V M IN 2.4 16 TYP 2.6 0.22 -32 22 MAX 0.4 -20 UNITS V V mA mA t r5 VO L = 0.4 V, VO H = 2.4 V 2 4 ns t f5 VO H = 2.4 V, VO L = 0.4 V 2 4 ns d t5 VT = 1.5 V 1 55 % t j1 s 5 VT = 1.5 V 150 250 ps t jabs 5 VT = 1.5 V 600 ps 45 -600 Guaranteed by des ign, not 100% tes ted in production. 9 ICS9248-162 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 10 ICS9248-162 CLK_STOP# Timing Diagram CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-162. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) SDRAM CPUCLK CPUCLK _F SDRAM_F Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-162. 3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-162 CLK_STOP# signal. SDRAMs are controlled as shown. 4. All other clocks continue to run undisturbed. 11 ICS9248-162 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLK PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 12 ICS9248-162 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-162. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-162 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock. CPUCLK (Internal) PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP# PCI_STOP# PCICLK Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state. 13 ICS9248-162 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9248162 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 14 ICS9248-162 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N α 0.635 0° .110 .005 .010 SEE VARIATIONS 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 15.748 16.002 .620 .630 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B VARIATIONS D mm. N 48 D (inch) Ordering Information ICS9248yF-162-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 15 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-162 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 SEE VARIATIONS D .0035 .008 SEE VARIATIONS 8.10 BASIC E E1 6.00 e 6.20 0.319 .236 0.50 BASIC L 0.45 0.75 SEE VARIATIONS N .244 0.020 BASIC .018 .30 SEE VARIATIONS α 0° 8° 0° 8° aaa - 0.10 - .004 MIN MAX MIN 12.40 12.60 VARIATIONS D mm. N 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) 48 D (inch) MAX .488 .496 MO-153 JEDEC Doc.# 10-0039 7/6/00 Rev B Ordering Information ICS9248yG-162-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.