TI TPD2E007YFMRG4

TPD2E007
www.ti.com ........................................................................................................................................ SLVS796D – SEPTEMBER 2008 – REVISED OCTOBER 2009
2-CHANNEL ESD-PROTECTION ARRAY
FOR AC-COUPLED/NEGATIVE-RAIL DATA INTERFACES
FEATURES
1
YFMG4 PACKAGE
(BOTTOM VIEW)
• ESD Protection Exceeds IEC61000-4-2
(Level 4)
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC 61000-4-2 Contact Discharge
– ±15-kV IEC 61000-4-2 Air-Gap Discharge
• 4.5-A Peak Pulse Current (8/20 ms Pulse)
• 15-pF Line to GND Capacitance
• Low 50-nA Leakage Current
• 2-Channel Device
• Space-Saving PicoStar™ and DCK Package
2
B1
B2
GND
IO1
A1
A2
IO2
0.8 mm × 0.8 mm (0.4 mm pitch)
YFMG4 PIN DESCRIPTIONS
TERMINAL
NAME
IO
APPLICATIONS
•
•
•
•
GND
GND
Cell Phones, PDAs
Audio Interface Connections
Consumer Electronics (DVR, Set-Top Box, TV)
Industrial Interface (RS-232, RS-485, RS-422,
LVDS)
NO.
DESCRIPTION
A1, A2 ESD-protection channel
B1, B2 Ground
DCK PACKAGE
(TOP VIEW)
IO1
1
3
IO2
GND
2
DESCRIPTION/ORDERING INFORMATION
This device is an application-specific integrated parts (ASIP) designed to offer system level ESD solutions for
wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or
negative-going data transmission (audio interface, LVDS, RS-485, RS-232, etc.) without compromising signal
integrity. The PicoStar™ package is intended to be embedded inside the printed circuit board which saves board
space in portable applications. This device exceeds the IEC61000-4-2 (Level 4) ESD protection and suitable to
provide system level ESD protection for the valuable internal ICs while placed near the connector.
The TPD2E007 is offered in a 4-bump PicoStar™ and 3-pin DCK packages. The PicoStar™ package (YFMG4),
with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package
height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in
surface mount applications. The industry standard DCK package offers straightforward board layout option in
legacy designs.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PicoStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
TPD2E007
SLVS796D – SEPTEMBER 2008 – REVISED OCTOBER 2009 ........................................................................................................................................ www.ti.com
ORDERING INFORMATION
TA
PACKAGE
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
DSLGA – YFM
Tape and reel
TPD2E007YFMRG4
45
T
–40°C to 85°C
3-DCK
Tape and reel
TPD2E007DCKR
45U
(1)
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
EQUIVALENT SCHEMATIC REPRESENTATION
IO1
IO2
GND
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VIO
Continuous power dissipation
(TA = 70°C)
MIN
MAX
UNIT
–13.5
13.5
V
270
mW
YFM package
Operating temperature range
–40
85
°C
Tstg
Storage temperature range
–65
150
°C
TJ
Junction temperature
150
°C
Bump temperature (soldering)
Infrared (15 s)
220
Vapor phase (60 s)
215
Lead temperature (soldering, 10 s)
(1)
°C
300
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
VBR
Break-down voltage
IIO
Channel leakage current
20
Rd
Dynamic resistance
3.5
CIN
Channel input capacitance
(1)
IIO = 10 mA
MIN
VIO = 2.5 V
MAX
±14
UNIT
V
10
50
nA
15
pF
Ω
Typical values are at VCC = 5 V and TA = 25°C.
ESD Protection
PARAMETER
TYP
UNIT
±15
kV
IEC 61000-4-2 Contact Discharge
±8
kV
IEC 61000-4-2 Air-Gap Discharge
±15
kV
HBM
2
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPD2E007
TPD2E007
www.ti.com ........................................................................................................................................ SLVS796D – SEPTEMBER 2008 – REVISED OCTOBER 2009
TYPICAL OPERATING CHARACTERISTICS
IEC Clamping Waveforms
(20 ns/div)
280
40
20
240
0
–20
–40
200
Amplitude (V)
Amplitude (V)
–60
160
120
80
–80
–100
–120
–140
–160
–180
–200
40
–220
–240
0
–260
–280
–40
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
Time (ns)
Figure 1. 8-kV Contact
80
100
120
Time (ns)
140
160
180
200
Figure 2. –8-kV Contact
1.5E-11
1.50E-01
1.4E-11
1.25E-01
1.3E-11
1.00E-01
1.2E-11
7.50E-02
1.1E-11
2.50E-02
9.0E-12
Amps
Capacitance (F)
5.00E-02
1.0E-11
8.0E-12
0.00E+00
–2.50E-02
7.0E-12
Device 2
6.0E-12
–5.00E-02
Device 1
5.0E-12
–7.50E-02
4.0E-12
–1.00E-01
Device 1
3.0E-12
–1.25E-01
Device 2
2.0E-12
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5
0
0
7.
5
10
.0
12
.5
15
.0
17
.5
20
.0
1.5
5.
1.0
2.
0.5
0.
0.0
–2
0.
0
–1
7.
5
–1
5.
0
–1
2.
5
–1
0.
0
–7
.5
–5
.0
-2
.5
–1.50E-01
1.0E-12
Volts
Input Voltage (V)
Figure 3. Capacitance vs Input Voltage at TA = 27°C
Figure 4. Diode Breakdown Voltage Data at TA = 27°C
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPD2E007
3
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPD2E007DCKR
ACTIVE
SC70
DCK
3
TPD2E007YFMR
PREVIEW
DSLGA
YFM
4
TPD2E007YFMRG4
ACTIVE
DSLGA
YFM
4
3000 Green (RoHS &
no Sb/Br)
TBD
3000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-2-260C-1 YEAR
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPD2E007DCKR
SC70
DCK
3
3000
179.0
8.4
2.4
2.4
1.19
4.0
8.0
Q3
TPD2E007YFMRG4
DSLGA
YFM
4
3000
180.0
8.4
0.84
0.84
0.28
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD2E007DCKR
SC70
DCK
3
3000
195.0
200.0
45.0
TPD2E007YFMRG4
DSLGA
YFM
4
3000
190.5
212.7
31.8
Pack Materials-Page 2
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