MOSEL VITELIC PRELIMINARY V29C51400T/V29C51400B 4 MEGABIT (262,144 x 16 BIT/524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Features Description ■ ■ ■ ■ ■ ■ The V29C51400T/V29C51400B is a high speed 262,144 x 16 bit or 524,288 x 8-bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The V29C51400T/V29C51400B offers a combination of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. The V29C51400T/V29C51400B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (V29C51400T) or the bottom (V29C51400B). All inputs and outputs are CMOS and TTL compatible. The V29C51400T/V29C51400B is ideal for applications that require updatable code and data storage. ■ ■ ■ ■ ■ ■ ■ ■ 256K x 16-bit or 512K x 8-bit Organization Address Access Time: 70, 90, 120 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 16KB Boot Block (lockable) 1K bytes per Sector, 512 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Write Cycle Time: 20µs (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation – Active Read Current: 19mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100µA (Max) Hardware Data Protection Low VCC Program Inhibit Below 3.5V Self-timed write/erase operations with end-ofcycle detection – DATA Polling – Toggle Bit CMOS and TTL Interface Available in two versions – V29C51400T (Top Boot Block) – V29C51400B (Bottom Boot Block) Packages: – 48-pin TSOP Device Usage Chart Operating Temperature Range Package Outline 0°C to 70 °C V29C51400T/V29C51400B Rev. 1.5 October 2000 Access Time (ns) T 70 90 120 Temperature Mark • • • • Blank 1 MOSEL VITELIC V 29 V29C51400T/V29C51400B C 51 400 OPERATING VOLTAGE 51: 5V T – DEVICE SPEED PKG. TEMP. BLANK (0°C TO 70°C) BOOT BLOCK LOCATION T: TOP B: BOTTOM 70: 70ns 90: 90ns 12: 120ns T = TSOP 51400-01 Pin Configurations A15 A14 A13 A12 A11 A10 A9 A8 N/C N/C WE N/C N/C N/C RY/BY N/C A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Names 48-Pin TSOP Standard Pinout Top View 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15(A-1) I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0 51400-02 V29C51400T/V29C51400B Rev. 1.5 October 2000 2 A0–A17 Address Inputs I/O0–I/O14 Data Input/Output I/O15 (A-1) Data Input/Output, Word Mode (LSB Address Input, Byte Mode) CE Chip Enable OE Output Enable WE Write Enable VCC 5V ± 10% Power Supply GND Ground NC No Connect RY/BY Ready/Busy Output BYTE Selects 8-Bit or 16-Bit mode MOSEL VITELIC V29C51400T/V29C51400B Functional Block Diagram 4,194,304 Bit Memory Cell Array X-Decoder A0–A17 Address buffer & latches RY/BY CE OE WE BYTE Y-Decoder Control Logic I/O Buffer & Data Latches I/O0–I/O15 (A-1) 51400-03 Capacitance (1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test Setup Typ. Max. Units VIN = 0 6 8 pF VOUT = 0 8 12 pF VIN = 0 8 10 pF NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz. Latch Up Characteristics(1) Parameter Min. Max. Unit Input Voltage with Respect to GND on A9, OE -1 +13 V Input Voltage with Respect to GND on I/O, address or control pins -1 VCC + 1 V -100 +100 mA VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time. AC Test Load +5.0 V IN3064 or Equivalent 2.7 kΩ Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent 51400-04 V29C51400T/V29C51400B Rev. 1.5 October 2000 3 MOSEL VITELIC V29C51400T/V29C51400B Absolute Maximum Ratings(1) Symbol Parameter Commercial Unit VIN Input Voltage (input or I/O pins) -2 to +7 V VIN Input Voltage (A9 pin, OE) -2 to +13 V VCC Power Supply Voltage -0.5 to +5.5 V TSTG Storage Temperature (Plastic) -65 to +125 °C TOPR Operating Temperature 0 to +70 °C IOUT Short Circuit Current(2) 200 (Max.) mA NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. DC Electrical Characteristics (over the commercial operating range) Parameter Name Parameter Test Conditions VIL Input LOW Voltage VIH Min. Max. Unit VCC = VCC Min. — 0.8 V Input HIGH Voltage VCC = VCC Max. 2 — V IIL Input Leakage Current VIN = GND to VCC, VCC = VCC Max. — ±1 µA IOL Output Leakage Current VOUT = GND to VCC, VCC = VCC Max. — ±1 µA VOL Output LOW Voltage VCC = VCC Min., IOL = 2.1mA — 0.4 V VOH Output HIGH Voltage VCC = VCC Min, IOH = -400µA 2.4 — V ICC1 Read Current CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. — 40 mA ICC2 Write Current CE = WE = VIL, OE = VIH, VCC = VCC Max. — 50 mA ISB TTL Standby Current CE = OE = WE = VIH, VCC = VCC Max. — 2 mA ISB1 CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 100 µA VH Device ID Voltage for A9 CE = OE = VIL, WE = VIH 11.5 12.5 V IH Device ID Current for A9 CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA V29C51400T/V29C51400B Rev. 1.5 October 2000 4 MOSEL VITELIC V29C51400T/V29C51400B AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -70 Parameter -90 -12 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 70 — 90 — 120 — ns tAA Address Access Time — 70 — 90 — 120 ns tACS Chip Enable Access Time — 70 — 90 — 120 ns tOE Output Enable Access Time — 35 — 45 — 60 ns tCLZ CE Low to Output Active 0 — 0 — 0 — ns tOLZ OE Low to Output Active 0 — 0 — 0 — ns tDF OE or CE High to Output in High Z 0 20 0 20 0 30 ns tOH Output Hold from Address Change 0 — 0 — 0 — ns Program (Erase/Program) Cycle Parameter Name Parameter -70 -90 -12 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tWC Write Cycle Time 70 — — 90 — — 120 — — ns tAS Address Setup Time 0 — — 0 — — 0 — — ns tAH Address Hold Time 45 — — 45 — — 50 — — ns tCS CE Setup Time 0 — — 0 — — 0 — — ns tCH CE Hold Time 0 — — 0 — — 0 — — ns tOES OE Setup Time 0 — — 0 — — 0 — — ns tOEH OE High Hold Time 0 — — 0 — — 0 — — ns tWP WE Pulse Width 35 — — 45 — — 50 — — ns WE Pulse Width High 20 — — 30 — — 35 — — ns tDS Data Setup Time 30 — — 30 — — 30 — — ns tDH Data Hold Time 0 — — 0 — — 0 — — ns tWHWH1 Programming Cycle — — 20 — — 20 — — 20 µs tWHWH2 Sector Erase Cycle — — 10 — — 10 — — 10 ms tWHWH3 Chip Erase Cycle — 2 — — 2 — — 2 — sec tWPH Word/Byte Configuration Parameter Name Parameter tELFL/tELFH -70 Min. -90 Typ. Max. Min. -12 Typ. Max. Min. Typ. Max. Unit CE to BYTE Switching Low/High — — 5 — — 5 — — 5 ns tFLQZ BYTE Low to Output in HIGH — — 20 — — 20 — — 30 ns tFHQV BYTE High to Output Active 70 — — 90 — — 120 — — ns V29C51400T/V29C51400B Rev. 1.5 October 2000 5 MOSEL VITELIC V29C51400T/V29C51400B BYTE Timings for Read Operations CE OE BYTE tELFL BYTE Switching from word to byte mode Data Output (I/O0—I/O7) Data Output (I/O0—I/O14) I/O0—I/O14 Address Input I/O15 Output I/O15(A-1) tFLQZ tELFH BYTE BYTE Switching from byte to word mode I/O0—I/O14 Data Output (I/O0—I/O7) I/O15(A-1) Address Input Data Output (I/O0—I/O14) I/O15 Output tFHQV BYTE Timings for Write Operations CE The falling edge of the last WE signal WE BYTE tAS t AH Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. V29C51400T/V29C51400B Rev. 1.5 October 2000 6 MOSEL VITELIC V29C51400T/V29C51400B Waveforms of Read Cycle tRC ADDRESS tAA tCE CE tOE tDF OE tOLZ WE tCLZ HIGH-Z I/O tOH VALID DATA OUT HIGH-Z VALID DATA OUT tAA RY/BY 51400-05 Waveforms of WE Controlled-Program Cycle 3rd bus cycle tWC tAS 5555H ADDRESS PA(2) PA tCH tRC tAH CE OE tOES tWHWH1 tWP WE tDF tWPH tCS tDS tOE tDH I/O A0H PD(3) I/O7(1) DOUT tOH 51400-06 NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed. V29C51400T/V29C51400B Rev. 1.5 October 2000 7 MOSEL VITELIC V29C51400T/V29C51400B Waveforms of CE Controlled-Program Cycle tWC ADDRESS 5555H PA(1) PA tAS tRC tAH WE OE tWP tWHWH1 CE tDF tWPH tOES tDS tOE tDH I/O PD(2) A0H I/O7 DOUT tOH 51400-07 Waveforms of Erase Cycle(1) tWC ADDRESS (5555H for Chip Erase) tAS 5555H 2AAAH 5555H 5555H 2AAAH SA tAH CE OE tWP WE tWHWH 2 tWPH tCS 3 tDS (10H for Chip Erase) tDH I/O AAH 55H 80H AAH 55H 30H 51400-08 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. V29C51400T/V29C51400B Rev. 1.5 October 2000 8 MOSEL VITELIC V29C51400T/V29C51400B Waveforms of DATA Polling Cycle tCH CE tDF tOE OE tOEH tCE WE tWHWH1 (2 or 3) I/O7 I/O0-I/O6 I/O7 I/O7 INVALID I/O0-I/O6 tOH VALID DATA OUT VALID DATA OUT HIGH-Z HIGH-Z 51400-09 Waveforms of Toggle Bit Cycle CE tOEH WE OE I/O6 stop toggling tWHWH1 (2 or 3) 51400-10 V29C51400T/V29C51400B Rev. 1.5 October 2000 9 MOSEL VITELIC V29C51400Tx8 16KB Boot Block V29C51400T/V29C51400B V29C51400Bx8 V29C51400Tx16 7FFFFH 16KB Boot Block 7C000H 00000H V29C51400Bx16 3FFFFH 3E000H 00000H 3FFFH 16KB Boot Block 00000H 00000H 00000H 1FFFH 16KB Boot Block 00000H 51400-11 16KB Boot Block = 32 Sectors 16KB Boot Block = 32 Sectors BYTE MODE WORD MODE World/Byte Configuration Output Disable The BYTE pin controls whether the device data I/O pins I/O0-I/O15 operate in the byte or word configuration. If the BYTE pin is set at logic ’1’, the device is in word configuration, I/O0-I/O15 are active and controlled by CE and OE. If BYTE pin is set at logic ’0’, the device is in byte configuration, and only data I/O pins I/O0-I/O7 are active and controlled by CE and OE. The data I/O pins I/O8-I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. Standby The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state. Command Sequence The V29C51400T/V29C51400B does not provide the “reset” feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. In this case, normal operation (Read Mode) can be restored by issuing a “non-existent” command sequence, for example Address: 5555H, Data FFH. Functional Description The V29C51400T/V29C51400B consists of 512 equally-sized sectors of 512 bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The V29C51400 is available in two versions: the V29C51400T with the Boot Block address starting from 7C000H to 7FFFFH, and the V29C51400B with the Boot Block address starting from 00000H to 3FFFH. Byte Write Cycle The V29C51400T/V29C51400B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled. Read Cycle A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). V29C51400T/V29C51400B Rev. 1.5 October 2000 10 MOSEL VITELIC V29C51400T/V29C51400B Sector Erase Cycle erase command (see Table 2). A sector must be first erased before it can be re-written. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit status. The V29C51400T/V29C51400B is shipped fully erased (all bits = 1). The V29C51400T/V29C51400B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector Table 1. Operation Modes Decoding Decoding Mode CE OE WE A0 A1 A9 I/O Read Byte Write Standby Autoselect Device ID Autoselect Manufacture ID Enabling Boot Block Protection Lock Disabling Boot Block Protection Lock Output Disable VIL VIL VIH VIL VIL VIL VH VIL VIL VIH X VIL VIL VH VH VIH VIH VIL X VIH VIH VIL VIL VIH A0 A0 X VIH VIL X X X A1 A1 X VIL VIL X X X A9 A9 X VH VH VH VH X READ PD HIGH-Z CODE CODE X X HIGH-Z NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. Table 2. Command Codes Command Sequence Bus Write Cycles Req’d Reset/Read 1 Reset/Read Word 3 Byte Autoselect Mode Word First Bus Program Cycle Second Bus Program Cycle Third Bus Program Cycle Fourth Bus Program Cycle Fifth Bus Program Cycle Six Bus Program Cycle Address Data Address Data Address Data Address Data Address Data Address Data 5555H F0H RA RD 90H 01H 13H, B3H (B Device ID) XXXXH F0H 5555H AAH AAAAH 3 Byte 5555H 2AAAH 55H 5555H AAH AAAAH 2AAAH AAAAH 55H 5555H 5555H 13H, B3H (B Device ID) AAAAH Word/Byte Program Word 4 Byte Chip Erase Word 0 Byte Sector Erase Word Byte 5555H AAH AAAAH 5555H AAH AAAAH 6 5555H AAAAH 2AAAH 55H 5555H 2AAAH 2AAAH A0H 40H (Manuf. ID) PA PD(4) 5555H AAH AAAAH 55H 5555H AAH 5555H 00H 5555H 80H AAAAH 55H 5555H 5555H AAAAH AAAAH 80H 5555H AAAAH 2AAAH 55H 5555H AAH 2AAAH 5555H 10H AAAAH 55H SA 30H 5555H NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address Chip Erase Cycle command, two additional unlock program cycles, and the chip erase command (see Table 2). The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is “1”. The V29C51400T/V29C51400B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup V29C51400T/V29C51400B Rev. 1.5 October 2000 11 MOSEL VITELIC V29C51400T/V29C51400B Program Cycle Status Detection status, device ID and manufacturer ID. Entering Autoselect mode is accomplished by applying a high voltage (VH) to the A9 Pin, or through a sequence of commands (as shown in table 2). Device will exit this mode once high voltage on A9 is removed or another command is loaded into the device. There are two methods for determining the state of the V29C51400T/V29C51400B during a program (erase/write) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6). DATA Polling (I/O7) The V29C51400T/V29C51400B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle. Boot Block Protection Status In Autoselect mode, performing a read at address location 7BXX2H (V29C51400T) or 0CXX2H (V29C51400B) will indicate boot block protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3. Toggle Bit (I/O6) The V29C51400T/V29C51400B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle. Device ID Boot Block Protection Enabling/Disabling In Autoselect mode, performing a read at address XXXX0H will determine the manufacturer ID. 40H is the manufacturer code for Mosel Vitelic Flash. In Autoselect mode, performing a read at address XXX1H will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 13H, the device is a Top Boot Block. If the data is B3H, the device is a Bottom Boot Block device (see Table 3). Manufacturer ID The V29C51400T/V29C51400B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin LOW. The sector protection is disabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1. Hardware Data Protection VCC Detection: the program operation is inhibited when VCC is less than 3.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle. Autoselect Mode The V29C51400T/V29C51400B features an Autoselect mode to identify boot block locking Table 3. Autoselect Decoding Address Decoding Mode Boot Block A0 A1 A2–A13 A14–A17 Boot Block Protection Top VIL VIH X VIH 01H: protected Bottom VIL VIH X VIL 00H: unprotected Top VIH VIL X X Device ID Bottom Manufacture ID 13H B3H VIL VIL NOTE: 1. X = Don’t Care, VIH = HIGH, VIL = LOW. V29C51400T/V29C51400B Rev. 1.5 October 2000 Data I/O0–I/O7 12 X X 40H MOSEL VITELIC V29C51400T/V29C51400B Byte Program AlgorithmChip/Sector Erase Algorithm Write Byte-Write Command Sequence Write Erase Command Sequence Add/Data 5555H/AAH Add/Data 5555H/AAH 2AAAH/55H 2AAAH/55H Four Bus Cycle Sequence 5555H/A0H 5555H/80H Six Bus Cycle Sequence PA/PD 5555H/AAH Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout 2AAAH/55H 5555H/10H (Chip Erase) SA/30H (Sector Erase) Writing Completed Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout Erase Completed 51400-12 V29C51400T/V29C51400B Rev. 1.5 October 2000 13 MOSEL VITELIC V29C51400T/V29C51400B DATA Polling Algorithm No Toggle Bit Algorithm Read I/O7 Address = PBA(1) Read I/O6 I/O7 = Data Read I/O6 Yes Yes I/O6 Toggle Program Done No Program Done 51400-13 NOTE: 1. PBA: The byte address to be programmed. V29C51400T/V29C51400B Rev. 1.5 October 2000 14 MOSEL VITELIC V29C51400T/V29C51400B Package Diagrams 48-pin TSOP Pin 1 I.D. 1 48 Detail “A” 11.90 12.10 0.08 0.20 24 25 0.10 0.21 18.30 18.50 0° 5° 0.50 0.70 19.80 20.20 1.20 MAX See Detail A 0.25MM (0.0098") BSC V29C51400T/V29C51400B Rev. 1.5 October 2000 0.05 0.15 15 0.50 BSC 0.95 1.05 MOSEL VITELIC WORLDWIDE OFFICES V29C51400T/V29C51400B U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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