MOSEL VITELIC V29LC51002 2 MEGABIT (262,144 x 8 BIT) 5 VOLT CMOS FLASH MEMORY PRELIMINARY Features Description ■ ■ ■ ■ ■ The V29LC51002 is a high speed 262,144 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The V29LC51002 features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. ■ ■ ■ ■ ■ 256Kx8-bit Organization Address Access Time: 90 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 512 bytes per Sector, 512 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Write Cycle Time: 30µs (Max) Minimum 1,000 Erase-Program Cycles Low power dissipation – Active Read Current: 20mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100µA (Max) Low VCC Program Inhibit Below 3.5V CMOS and TTL Interface Packages: – 32-pin Plastic DIP – 32-pin PLCC Device Usage Chart Operating Temperature Range 0°C to 70°C V29LC51002 Rev. 0.5 October 2000 Package Outline Access Time (ns) P J 90 Temperature Mark • • • Blank 1 MOSEL VITELIC V29LC51002 V 29 LC 51 002 OPERATING VOLTAGE 51: 5V – DEVICE SPEED PKG. 90: 90ns P = PDIP J = PLCC C51002-01 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A17 2 WE 3 VCC 4 1 32 31 30 A7 5 29 A14 A6 A5 A4 A3 A2 A1 A0 I/O0 6 28 7 27 A13 A8 A9 A11 OE A10 CE I/O7 8 26 32 Pin PLCC Top View 9 25 10 24 11 23 12 22 21 13 Pin Names A0–A17 Address Inputs I/O0–I/O7 Data Input/Output CE Chip Enable OE Output Enable WE Write Enable VCC 5V ± 10% Power Supply GND Ground NC No Connect 2 I/O6 I/O5 I/O4 I/O3 14 15 16 17 18 19 20 51002-02 V29LC51002 Rev. 0.5 October 2000 A16 NC VCC WE A17 A14 A13 A8 A9 A11 OE A15 8 9 10 11 12 13 14 15 16 31 30 29 28 27 32-Pin PDIP 26 Top View 25 24 23 22 21 20 19 18 17 GND A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32 I/O2 1 2 3 4 5 6 7 I/O1 N/C A16 A15 A12 A7 A6 A5 A12 Pin Configurations 51002-03 MOSEL VITELIC V29LC51002 Functional Block Diagram 2,097,152 Bit Memory Cell Array X-Decoder A0–A17 Address buffer & latches CE OE WE Control Logic Y-Decoder I/O Buffer & Data Latches I/O0–I/O7 51002-07 Capacitance (1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test Setup Typ. Max. Units VIN = 0 6 8 pF VOUT = 0 8 12 pF VIN = 0 8 10 pF NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz. Latch Up Characteristics(1) Parameter Min. Max. Unit Input Voltage with Respect to GND on A9, OE -1 +13 V Input Voltage with Respect to GND on I/O, address or control pins -1 VCC + 1 V -100 +100 mA VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time. AC Test Load +5.0 V IN3064 or Equivalent 2.7 kΩ Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent 51002-08 V29LC51002 Rev. 0.5 October 2000 3 MOSEL VITELIC V29LC51002 Absolute Maximum Ratings(1) Symbol Parameter Commercial Unit VIN Input Voltage (input or I/O pins) -2 to +7 V VIN Input Voltage (A9 pin, OE) -2 to +13 V VCC Power Supply Voltage -0.5 to +5.5 V TSTG Storage Temerpature (Plastic) -65 to +125 °C TOPR Operating Temperature 0 to +70 °C IOUT Short Circuit Current(2) 200 (Max.) mA NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. DC Electrical Characteristics (over the commercial operating range) Parameter Name Parameter Test Conditions VIL Input LOW Voltage VIH Min. Max. Unit VCC = VCC Min. — 0.8 V Input HIGH Voltage VCC = VCC Max. 2 — V IIL Input Leakage Current VIN = GND to VCC, VCC = VCC Max. — ±1 µA IOL Output Leakage Current VOUT = GND to VCC, VCC = VCC Max. — ±10 µA VOL Output LOW Voltage VCC = VCC Min., IOL = 2.1mA — 0.4 V VOH Output HIGH Voltage VCC = VCC Min, IOH = -400µA 2.4 — V ICC1 Read Current CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. — 40 mA ICC2 Write Current CE = WE = VIL, OE = VIH, VCC = VCC Max. — 50 mA ISB TTL Standby Current CE = OE = WE = VIH, VCC = VCC Max. — 2 mA ISB1 CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 100 µA VH Device ID Voltage for A9 CE = OE = VIL, WE = VIH 11.5 12.5 V IH Device ID Current for A9 CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA V29LC51002 Rev. 0.5 October 2000 4 MOSEL VITELIC V29LC51002 AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -90 Parameter Min. Max. Unit tRC Read Cycle Time 90 — ns tAA Address Access Time — 90 ns tACS Chip Enable Access Time — 90 ns tOE Output Enable Access Time — 45 ns tCLZ CE Low to Output Active 0 — ns tOLZ OE Low to Output Active 0 — ns tDF OE or CE High to Output in High Z 0 40 ns tOH Output Hold from Address Change 0 — ns Program (Erase/Program) Cycle -90 Parameter Name Parameter Min. Typ. Max. Unit tWC Write Cycle Time 90 — — ns tAS Address Setup Time 0 — — ns tAH Address Hold Time 45 — — ns tCS CE Setup Time 0 — — ns tCH CE Hold Time 0 — — ns tOES OE Setup Time 0 — — ns tOEH OE High Hold Time 0 — — ns tWP WE Pulse Width 45 — — ns WE Pulse Width High 30 — — ns tDS Data Setup Time 30 — — ns tDH Data Hold Time 0 — — ns tWHWH1 Programming Cycle — — 30 µs tWHWH2 Sector Erase Cycle — — 10 ms tWHWH3 Chip Erase Cycle — 3 — sec tWPH V29LC51002 Rev. 0.5 October 2000 5 MOSEL VITELIC V29LC51002 Waveforms of Read Cycle tRC ADDRESS tAA tCE CE tOE tDF OE tOLZ WE tCLZ HIGH-Z I/O tOH VALID DATA OUT HIGH-Z VALID DATA OUT 51002-09 tAA Waveforms of WE Controlled-Program Cycle 3rd bus cycle tWC tAS 5555H ADDRESS PA tCH tRC tAH CE OE tOES tWP tWHWH1 WE tDF tWPH tCS tDS tOH tOE tDH I/O A0H Valid Data PD(3) C51002-10 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. V29LC51002 Rev. 0.5 October 2000 6 MOSEL VITELIC V29LC51002 Waveforms of Erase Cycle(1) tWC ADDRESS (5555H for Chip Erase) tAS 5555H 2AAAH 5555H 5555H 2AAAH SA tAH CE OE tWP WE tWHWH 2 tWPH tCS 3 tDS (10H for Chip Erase) tDH I/O AAH 55H 80H AAH 55H 30H 51002-12 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. V29LC51002 Rev. 0.5 October 2000 7 MOSEL VITELIC V29LC51002 FUNCTIONAL DESCRIPTION V29LC51002 Read Cycle 512 A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). 512 • • • 512 Output Disable 512 Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. 00000H C51002-15 The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state. During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled. Command Sequence Sector Erase Cycle The V29LC51002 does not provide the “reset” feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. In this case, normal operation (Read Mode) can be restored by issuing a “non-existent” command sequence, for example Address: 5555H, Data FFH. The V29LC51002 features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be re-written. While in the internal erase mode, the device ignores any program attempt into the device. Sector erase is completed in 10ms max. The V29LC51002 is shipped fully erased (all bits = 1). Standby Byte Write Cycle The V29LC51002 is programmed on a byte-bybyte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). Table 1. Operation Modes Decoding Decoding Mode CE OE WE A0 A1 A9 I/O Read Byte Write Standby Output Disable VIL VIL VIH VIL VIL VIH X VIH VIH VIL X VIH A0 A0 X X A1 A1 X X A9 A9 X X READ PD HIGH-Z HIGH-Z NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. V29LC51002 Rev. 0.5 October 2000 8 MOSEL VITELIC V29LC51002 Table 2. Command Codes First Bus Program Cycle Second Bus Program Cycle Third Bus Program Cycle Fourth Bus Program Cycle Fifth Bus Program Cycle Six Bus Program Cycle Command Sequence Address Data Address Data Address Data Address Data Address Data Address Data Read XXXXH F0H Read 5555H AAH 2AAAH 55H 5555H F0H RA(1) RD(2) Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H 40H(6) 01H 82H(7) Byte Program 5555H AAH 2AAAH 55H 5555H A0H PA PD(4) Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5) 30H NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address 6. 40H: Manufacturing ID 7. 82H: Device ID Chip Erase Cycle The V29LC51002 features a chip-erase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). V29LC51002 Rev. 0.5 October 2000 The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and is completed in 3 sec max. 9 MOSEL VITELIC V29LC51002 Byte Program Algorithm Chip/Sector Erase Algorithm Write Byte-Write Command Sequence Write Erase Command Sequence Add/Data 5555H/AAH Add/Data 5555H/AAH 2AAAH/55H 2AAAH/55H Four Bus Cycle Sequence 5555H/A0H 5555H/80H Six Bus Cycle Sequence PA/PD 5555H/AAH Time Out 30µS 2AAAH/55H Writing Complete 5555H/10H (Chip Erase) SA/30H (Sector Erase) Time Out for Sector or Chip Erase Erase Complete C51002-16 V29LC51002 Rev. 0.5 October 2000 10 MOSEL VITELIC V29LC51002 Package Diagrams 32-pin Plastic DIP 1.660 MAX. 15° MAX INDEX-1 EJECTOR MARK .600 TYP 0.545/0.555 INDEX-2 +.004 .010 – .0004 .050 MAX 0.210 MAX 0.120 MIN .100 TYP +.006 .018 – .002 +.012 .047 – 0 0.010 MIN .032 +.012 –0 32-pin PLCC 20 19 18 17 16 15 14 21 13 22 12 23 11 24 10 25 9 26 8 27 7 28 .590 ± .005 .550 ± .003 6 29 30 31 32 1 2 3 4 5 .045X45° .450 ± .003 .110 .490 ± .005 .136 ± .003 .046 ± .003 .025 .050 TYP 30° .017 .420 ± .003 V29LC51002 Rev. 0.5 October 2000 3° - 6° 3° - 6° 11 3° - 6° MOSEL VITELIC WORLDWIDE OFFICES V29LC51002 U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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