SyncMOS F29C51001T/F29C51001B Functional Block Diagram 1,048,576 Bit Memory Cell Array X-Decoder A0–A16 Address buffer & latches CE OE WE Control Logic Y-Decoder I/O Buffer & Data Latches I/O0–I/O7 51001-05 Capacitance (1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test mSetup Typ. Max. Units VIN = 0 6 8 pF VOUT = 0 8 12 pF VIN = 0 8 10 pF NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz. Latch Up Characteristics(1) Parameter Min. Max. Unit Input Voltage with Respect to GND on A9, OE -1 +13 V Input Voltage with Respect to GND on I/O, address or control pins -1 VCC + 1 V -100 +100 mA VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time. AC Test Load +5.0 V IN3064 or Equivalent 2.7 kΩ Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent 51001-06 F29C51001T/F29C51001B V1.0 May 1999 3 SyncMOS F29C51001T/F29C51001B Absolute Maximum Ratings(1) Symbol Parameter Commercial Extended Unit VIN Input Voltage (input or I/O pins) -2 to +7 -2 to +7 V VIN Input Voltage (A9 pin, OE) -2 to +13 -2 to +13 V VCC Power Supply Voltage -0.5 to +5.5 -0.5 to +5.5 V TSTG Storage Temerpature (Plastic) -65 to +125 -65 to +150 °C TOPR Operating Temperature 0 to +70 -40 to + 125 °C IOUT Short Circuit Current(2) 200 (Max.) 200 (Max.) mA NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. DC Electrical Characteristics (over the commercial operating range) Parameter Name Parameter Test Conditions VIL Input LOW Voltage VIH Min. Max. Unit VCC = VCC Min. — 0.8 V Input HIGH Voltage VCC = VCC Max. 2 — V IIL Input Leakage Current VIN = GND to VCC, VCC = VCC Max. — ±1 µA IOL Output Leakage Current VOUT = GND to VCC, VCC = VCC Max. — ±1 µA VOL Output LOW Voltage VCC = VCC Min., IOL = 2.1mA — 0.4 V VOH Output HIGH Voltage VCC = VCC Min, IOH = -400µA 2.4 — V ICC1 Read Current CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. — 40 mA ICC2 Program Current CE = WE = VIL, OE = VIH, VCC = VCC Max. — 50 mA ISB TTL Standby Current CE = OE = WE = VIH, VCC = VCC Max. — 2 mA ISB1 CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 100 µA VH Device ID Voltage for A9 CE = OE = VIL, WE = VIH 11.5 12.5 V IH Device ID Current for A9 CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA F29C51001T/F29C51001B V1.0 May 1999 4 SyncMOS F29C51001T/F29C51001B AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -45 Parameter -70 -90 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 45 — 70 — 90 — ns tAA Address Access Time — 45 — 70 — 90 ns tACS Chip Enable Access Time — 45 — 70 — 90 ns tOE Output Enable Access Time — 25 — 35 — 45 ns tCLZ CE Low to Output Active 0 — 0 — 0 — ns tOLZ OE Low to Output Active 0 — 0 — 0 — ns tDF Output Enable or Chip Disable to Output in High Z 0 15 0 20 0 30 ns tOH Output Hold from Address Change 0 — 0 — 0 — ns Program (Erase/Program) Cycle Parameter Name -45 Parameter -70 -90 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tWC Program Cycle Time 45 — — 70 — — 90 — — ns tAS Address Setup Time 0 — — 0 — — 0 — — ns tAH Address Hold Time 35 — — 45 — — 45 — — ns tCS CE Setup Time 0 — — 0 — — 0 — — ns tCH CE Hold Time 0 — — 0 — — 0 — — ns tOES OE Setup Time 0 — — 0 — — 0 — — ns tOEH OE High Hold Time 0 — — 0 — — 0 — — ns tWP WE Pulse Width 25 — — 35 — — 45 — — ns WE Pulse Width High 20 — — 35 — — 38 — — ns tDS Data Setup Time 20 — — 25 — — 30 — — ns tDH Data Hold Time 0 — — 0 — — 0 — — ns tWHWH1 Programming Cycle — — 20 — — 20 — — 20 µs tWHWH2 Sector Erase Cycle — — 10 — — 10 — — 10 ms tWHWH3 Chip Erase Cycle — 500 — — 500 — — 500 — ms tWPH F29C51001T/F29C51001B V1.0 May 1999 5 SyncMOS F29C51001T/F29C51001B Waveforms of Read Cycle tRC ADDRESS tAA tCE CE tOE tDF OE tOLZ WE tCLZ HIGH-Z I/O tOH VALID DATA OUT HIGH-Z VALID DATA OUT 51001-07 tAA Waveforms of WE Controlled-Program Cycle 3rd bus cycle tWC tAS 5555H ADDRESS PA(2) PA tCH tRC tAH CE OE tWHWH1 tWP tOES WE tDF tWPH tCS tDS tOE tDH I/O A0H PD(3) I/O7(1) DOUT tOH 51001-08 NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed. F29C51001T/F29C51001B V1.0 May 1999 6 SyncMOS F29C51001T/F29C51001B Waveforms of CE Controlled-Program Cycle tWC ADDRESS 5555H PA(1) PA tAS tRC tAH WE OE tWP tWHWH1 CE tDF tWPH tOES tDS tOE tDH I/O PD(2) A0H I/O7 DOUT tOH 51001-09 Waveforms of Erase Cycle(1) tWC ADDRESS tAS 5555H 2AAAH 5555H 5555H 2AAAH SA tAH CE OE tWP WE tWPH tCS tDS 10H for Chip Erase tDH I/O AAH 55H 80H AAH 55H 30H 51001-10 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. Address = don’t care for Chip Erase. F29C51001T/F29C51001B V1.0 May 1999 7 SyncMOS F29C51001T/F29C51001B Waveforms of DATA Polling Cycle tCH CE tDF tOE OE tOEH tCE WE tOH tWHWH1 I/O7 I/O0-I/O6 I/O7 I/O7 INVALID I/O0-I/O6 VALID DATA OUT VALID DATA OUT HIGH-Z HIGH-Z 51001-11 Waveforms of Toggle Bit Cycle CE tOEH WE OE I/O6 51001-12 F29C51001T/F29C51001B V1.0 May 1999 8 SyncMOS F29C51001T/F29C51001B Functional Description F29C51001T The F29C51001T/F29C51001B consists of 256 equally-sized sectors of 512 bytes each. The 8 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The F29C51001 is available in two versions: the F29C51001T with the Boot Block address starting from 1E000H to 1FFFFH, and the F29C51001B with the Boot Block address starting from 00000H to 1FFFFH. 8KB Boot Block F29C51001B 1FFFFH 512 1E000H 512 512 512 • • • • • • 512 512 512 01FFFH 512 8KB Boot Block 00000H 00000H Read Cycle 51001-13 A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). 8KB Boot Block = 16 Sectors During the byte program cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte program cycle can be CE controlled or WE controlled. Output Disable Sector Erase Cycle Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. The F29C51001T/F29C51001B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be reprogrammed. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit. The F29C51001T/F29C51001B is shipped with pre-erased sectors (all bits = 1). Standby The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE signal. Byte Program Cycle The F29C51001T/F29C51001B is programmed on a byte-by-byte basis. The byte program operation is initiated by using a specific four-buscycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). Table 1. Operation Modes Decoding Decoding Mode CE OE WE A0 A1 A9 I/O Read VIL VIL VIH A0 A1 A9 READ Byte Write VIL VIH VIL A0 A1 A9 PD Standby VIH X X X X X HIGH-Z Autoselect Device ID VIL VIL VIH VIH VIL VH CODE Autoselect Manufacture ID VIL VIL VIH VIL VIL VH CODE Enabling Boot Block Protection Lock VIL VH VIL X X VH X F29C51001T/F29C51001B V1.0 May 1999 9 SyncMOS F29C51001T/F29C51001B Decoding Mode CE OE WE A0 A1 A9 I/O Disabling Boot Block Protection Lock VH VH VIL X X VH X Output Disable VIL VIH VIH X X X HIGH-Z NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW. VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. Table 2. Command Codes First Bus Program Cycle Second Bus Program Cycle Third Bus Program Cycle Fourth Bus Program Cycle Fifth Bus Program Cycle Six Bus Program Cycle Command Sequence Address Data Address Data Address Data Address Data Address Data Address Data Read XXXXH F0H Read 5555H AAH 2AAAH 55H 5555H F0H RA RD Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H 40H 01H 01H(1) A1H(2) Byte Program 5555H AAH 2AAAH 55H 5555H A0H PA PD(4) Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(3) 30H NOTES: 1. Top Boot Sector 2. Bottom Boot Sector 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. Chip Erase Cycle DATA Polling (I/O7) The F29C51001T/F29C51001B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). The chip erase operation is performed sequentially, one sector at a time. When the automated on chip erase algorithm is requested with the chip erase command sequence, the device automatically programs and verifies the entire memory array for an all zero pattern prior to erasure The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is “1”. The F29C51001T/F29C51001B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle. Toggle Bit (I/O6) The F29C51001T/F29C51001B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle. Program Cycle Status Detection There are two methods for determining the state of the F29C51001T/F29C51001B during a program (erase/program) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6). F29C51001T/F29C51001B V1.0 May 1999 10 SyncMOS F29C51001T/F29C51001B Boot Block Protection Device ID The F29C51001T/F29C51001B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin lOW. The sector protection is desabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1. In Autoselect mode, performing a read at address XXXXH will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 01H, the device is a Top Boot Block. If the data is A1H, the device is a Bottom Boot Block device (see Table 3). In addition, the device ID can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the A9 pin. When A0 is HIGH, the device ID is presented at the outputs. Autoselect The F29C51001T/F29C51001B features an Autoselect mode to identify the Boot Block (protected/unprotected), the Device (Top/Bottom), and the manufacturer ID. To get to the Autoselect mode, a high voltage (VH) must be applied to the A9 pin. Once the A9 signal is returned to LOW or HIGH, the device will return to the previous mode. Manufacturer ID In Autoselect mode, performing a read at address. XXXX0H will determine the manufacturer ID. 40H is the manufacturer code for SyncMOS Flash. In addition the manufacturer ID can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the A9 pin. when A0 is LOW, the manufacturer ID is presented at the outputs. Boot Block Protection Status In Autoselect mode, performing a read at address 3CXX2H or address 0CXX2H will indicate if the Top Boot Block sector or the Bottom Boot Block sector is locked out. If the data is 01H, the Top/Bottom Boot Block is protected. If the data is 00H, the Top/Bottom Boot Block is unprotected. (see Table 3.) Hardware Data Protection VCC Sense Protection: the program operation is inhibited when VCC is less than 2.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit Protection: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle. Table 3. Autoselect Decoding Address Decoding Mode Boot Block A0 A1 A2–A13 A14–A16 Boot Block Protection Top VIL VIH X VIH 01H: protected Bottom VIL VIH X VIL 00H: unprotected Top VIH VIL X X Device ID Bottom Manufacture ID 01H A1H VIL VIL NOTE: 1. X = Don’t Care, VIH = HIGH, VIL = LOW. F29C51001T/F29C51001B V1.0 May 1999 Data I/O0–I/O7 11 X X 40H SyncMOS F29C51001T/F29C51001B Byte Program Algorithm Chip/Sector Erase Algorithm Write Program Command Sequence Write Erase Command Sequence Add/Data 5555H/AAH Add/Data 5555H/AAH 2AAAH/55H 2AAAH/55H Four Bus Cycle Sequence 5555H/A0H 5555H/80H Six Bus Cycle Sequence PA/PD 5555H/AAH DATA Polling (I/O7) or Toggle Bit (I/O6) 2AAAH/55H 5555H/10H (Chip Erase) PA/30H (Sector Erase No Verify Byte? Yes DATA Polling or Toggle Bit Successfully Completed Programming Completed Erase Complete 51001-14 F29C51001T/F29C51001B V1.0 May 1999 12 SyncMOS F29C51001T/F29C51001B DATA Polling Algorithm No Toggle Bit Algorithm Read I/O7 Address = PBA(1) Read I/O6 I/O7 = Data Read I/O6 Yes Yes I/O6 Toggle Program Done No Program Done 51002-17 NOTE: 1. PBA: The byte address to be programmed. F29C51001T/F29C51001B V1.0 May 1999 13 SyncMOS F29C51001T/F29C51001B Package Diagrams 32-pin Plastic DIP 1.660 MAX. 15° MAX INDEX-1 EJECTOR MARK .600 TYP 0.545/0.555 INDEX-2 +.004 .010 – .0004 .050 MAX 0.210 MAX 0.120 MIN .100 TYP +.006 .018 – .002 +.012 .047 – 0 0.010 MIN .032 +.012 –0 32-pin PLCC 20 19 18 17 16 15 14 21 13 22 12 23 11 24 10 25 9 26 8 27 7 28 .590 ± .005 .550 ± .003 6 29 30 31 32 1 2 3 4 5 .045X45° .450 ± .003 .110 .490 ± .005 .136 ± .003 .046 ± .003 .025 .050 TYP 30° .017 .420 ± .003 F29C51001T/F29C51001B V1.0 May 1999 3° - 6° 3° - 6° 14 3° - 6° SyncMOS F29C51001T/F29C51001B 32-pin TSOP-I Units in inches Detail “A” 0.787 ± 0.008 0.010 0.315 TYP. (0.319 MAX.) 0.024 ± 0.004 0.724 TYP. (0.728 MAX.) 0.035 ± 0.002 SEATING PLANE See Detail “A” 0.005 MIN. 0.007 MAX. F29C51001T/F29C51001B V1.0 May 1999 0.032 TYP. 0.047 MAX. 0.020 MAX. 0.020 SBC 0.003 MAX 15 0.009 ± 0.002 SyncMOS Technology Inc. Sales Office : No. 1, Creation Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5792926 Fax : 886-3-5792953 Note 1 : publication date : May 1999. Rev. A Note 2 : all data and specification are subject to change without notice. F29C51001T/F29C51001B V1.0 May 1999 16