54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
•
•
•
•
•
•
•
•
•
Eight D-Type Flip-Flops in a Single Package
3-State Bus Driving Inverting Outputs
Full Parallel Access for Loading
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54AC11534 . . . JT PACKAGE
74AC11534 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
t
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OC
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
54AC11534 . . . FK PACKAGE
(TOP VIEW)
The eight flip-flops of the ′AC11534 are edgetriggered, D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
complement of the logic levels at the D inputs. The
′AC11534 is functionally equivalent to the
′AC11374 except for having inverted outputs.
An output-control input (OC) is used to place the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly.
The
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operation of the
flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
4
5
2D
1D
OC
NC
1Q
2Q
3Q
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
7D
8D
CLK
NC
8Q
7Q
6Q
4Q
GND
GND
NC
GND
GND
5Q
These eight flip-flops feature 3-state outputs
designed for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
3D
4D
VCC
NC
VCC
5D
6D
description
NC – No internal connection
FUNCTION TABLE
(each filp-flop)
INPUTS
OC
CLK
D
OUTPUT
Q
L
L
L
H
↑
↑
L
X
H
L
X
X
L
H
Q0
Z
The 54AC11534 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74AC11534 is characterized for
operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
logic symbol†
OC
CLK
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
logic diagram (positive logic)
OC
EN
CLK
C1
1D
1
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
2Q
1D
3Q
4Q
2D
24
13
23
22
5Q
6Q
7Q
3D
8Q
4D
21
20
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
6D
7D
8D
17
16
15
14
C1
1
1D
C1
2
1D
C1
3
1D
C1
4
1D
C1
9
1D
C1
10
1D
C1
11
1D
C1
1D
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
recommended operating conditions
54AC11534
VCC
Supply voltage
VIH
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
3
5
5.5
Dt /Dv
Input transition rise or fall rate
TA
Operating free-air temperature
NOM
MAX
3
5
5.5
2.1
3.15
3.15
3.85
3.85
UNIT
V
V
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
Low-level output current
MIN
2.1
VCC = 3 V
VCC = 4.5 V
High-level output current
IOL
MAX
0
Output voltage
IOH
NOM
VCC = 4.5 V
VCC = 5.5 V
Input voltage
74AC11534
MIN
0
VCC
VCC
0
–4
–4
– 24
– 24
VCC = 5.5 V
VCC = 3 V
– 24
– 24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
V
V
V
mA
mA
24
OC
0
5
0
5
D
0
10
0
10
– 55
125
– 40
85
ns/ V
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 mA
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 50 mA{
IOH = – 75 mA{
IOL = 24 mA
IOL = 50 mA{
IOL = 75 mA{
VO = VCC or GND
VI = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
TA = 25°C
TYP
MAX
54AC11534
MIN
MAX
MIN
3V
2.9
2.9
2.9
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
1.65
5.5 V
± 0.5
5.5 V
5.5 V
± 10
±5
± 0.1
±1
±1
8
160
80
4
Co
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
POST OFFICE BOX 655303
V
1.65
5.5 V
5V
UNIT
3.85
5.5 V
IO = 0
74AC11534
4.5 V
5.5 V
IOL = 12 mA
IOZ
II
MIN
5.5 V
IOL = 50 mA
VOL
VCC
• DALLAS, TEXAS 75265
mA
mA
mA
pF
pF
2–3
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1)
TA = 25°C
MIN
MAX
0
54AC11534
MIN
MAX
0
50
50
74AC11534
MIN
MAX
0
50
UNIT
fclock
tw
Clock frequency
Pulse duration, CLK low or CLK high
10
10
10
MHz
ns
tsu
th
Setup time, data before CLK ↑
3.5
3.5
3.5
ns
Hold time, data after CLK ↑
5.5
5.5
5.5
ns
timing requirements, VCC = 5 V ± 0.5 V (see Figure 1)
TA = 25°C
MIN
MAX
0
54AC11534
MIN
MAX
0
75
75
74AC11534
MIN
MAX
0
75
UNIT
fclock
tw
Clock frequency
Pulse duration, CLK low or CLK high
6.5
6.5
6.5
MHz
ns
tsu
th
Setup time, data before CLK ↑
3.5
3.5
3.5
ns
Hold time, data after CLK ↑
4.5
4.5
4.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tPZH
tPZL
OC
Q
tPHZ
tPLZ
OC
Q
MIN
TA = 25°C
TYP
MAX
54AC11534
MIN
74AC11534
MAX
MIN
50
MAX
50
75
1.5
11
15.3
1.5
19.1
1.5
50
17.6
1.5
11
15.7
1.5
19
1.5
17.7
1.5
9
12.8
1.5
15.8
1.5
14.6
1.5
9
12.6
1.5
15.6
1.5
14.3
1.5
10
12.6
1.5
13.8
1.5
13.3
1.5
8
13
1.5
14.2
1.5
13.8
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
OC
Q
OC
Q
MIN
TA = 25°C
TYP
MAX
54AC11534
MIN
MAX
75
74AC11534
MIN
MAX
75
100
75
1.5
7
10.3
1.5
12.7
1.5
11.7
1.5
7
10.7
1.5
13.2
1.5
12.1
1.5
6
9.2
1.5
11.2
1.5
10.4
1.5
6
9.2
1.5
11.3
1.5
10.4
1.5
9
11.1
1.5
11.9
1.5
11.6
1.5
6
8.8
1.5
9.6
1.5
9.2
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
2–4
TEST CONDITIONS
Power dissipation capacitance per flip
flip-flop
flop
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
CL = 50 pF,
pF
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
75
65
UNIT
pF
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Timing Input
(see Note B)
0V
tw
50%
th
tsu
VCC
Input
VCC
50%
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
Input
(see Note B)
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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