NEC UPA2751GR

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2751GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
The µPA2751GR is asymmetrical dual N-Channel MOS
Field Effect Transistor designed for DC/DC converters of
notebook computers and so on.
8
5
CH2
FEATURES
PART NUMBER
PACKAGE
µPA2751GR
Power SOP8
1.44
CH1
3 ; Source 2
4 ; Gate 2
5, 6 ; Drain 2
6.0 ±0.3
4
4.4
0.8
0.15
+0.10
–0.05
5.37 Max.
0.05 Min.
ORDERING INFORMATION
1 ; Source 1
2 ; Gate 1
7, 8 ; Drain 1
CH1
1
1.8 Max.
• Asymmetric dual chip type
• Low on-state resistance, Low Ciss
CH1: RDS(on)2: 21.0 mΩ MAX. (VGS = 4.5 V, ID = 4.5 A)
Ciss = 1040 pF TYP. (VDS = 10 V, VGS = 0 V)
CH2: RDS(on)2: 35.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A)
Ciss = 480 pF TYP. (VDS = 10 V, VGS = 0 V)
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
CH2
1.27
0.40
0.5 ±0.2
0.10
0.78 Max.
+0.10
–0.05
0.12 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Total Power Dissipation (1 unit)
Note2
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Note3
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
Single Avalanche Current
Note3
Single Avalanche Energy
CH1/CH2
CH1/CH2
CH1
CH2
CH1
CH2
CH1/CH2
CH1/CH2
CH1/CH2
CH1/CH2
CH1
CH1
CH2
CH2
VDSS
VGSS
ID(DC)
ID(DC)
ID(pulse)
ID(pulse)
PT
PT
Tch
Tstg
IAS
EAS
IAS
EAS
30
±20
±9.0
±8.0
±36
±32
1.7
2.0
150
–55 to + 150
9.0
8.1
8.0
6.4
V
V
A
A
A
A
W
W
°C
°C
A
mJ
A
mJ
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2
2. TA = 25°C, Mounted on ceramic substrate of 2000 mm x 1.6 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15781EJ1V0DS00 (1st edition)
Date Published March 2002 NS CP(K)
Printed in Japan
©
2001
µPA2751GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CH1
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
| yfs |
VDS = 10 V, ID = 4.5 A
5
11
RDS(on)1
VGS = 10 V, ID = 4.5 A
12.5
15.5
mΩ
RDS(on)2
VGS = 4.5 V, ID = 4.5 A
16.0
21.0
mΩ
RDS(on)3
VGS = 4.0 V, ID = 4.5 A
17.9
23.9
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = 10 V
1040
pF
Output Capacitance
Coss
VGS = 0 V
390
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
130
pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 4.5 A
13
ns
tr
VGS = 10 V
10
ns
td(off)
RG = 10 Ω
43
ns
9
ns
Rise Time
Turn-off Delay Time
Fall Time
tf
Total Gate Charge
QG
VDD = 24 V
21
nC
Gate to Source Charge
QGS
VGS = 10 V
3.3
nC
Gate to Drain Charge
QGD
ID = 9.0 A
5.1
nC
VF(S-D)
IF = 9.0 A, VGS = 0 V
0.84
V
Reverse Recovery Time
trr
IF = 9.0 A, VGS = 0 V
34
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/ µs
34
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
BVDSS
IAS
VDS
VDS
ID
Starting Tch
τ
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
PG.
2
50 Ω
10%
0
10%
Wave Form
VDD
D.U.T.
IG = 2 mA
90%
VDS
VGS
0
RL
VDD
Data Sheet G15781EJ1V0DS
td(on)
tr
ton
td(off)
tf
toff
µPA2751GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CH2
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±18 V, VDS = 0 V
±10
µA
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
| yfs |
VDS = 10 V, ID = 4.0 A
3.5
7
RDS(on)1
VGS = 10 V, ID = 4.0 A
18.0
23.0
mΩ
RDS(on)2
VGS = 4.5 V, ID = 4.0 A
25.0
35.0
mΩ
RDS(on)3
VGS = 4.0 V, ID = 4.0 A
28.5
41.0
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = 10 V
480
pF
Output Capacitance
Coss
VGS = 0 V
190
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
70
pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 4.0 A
9.9
ns
tr
VGS = 10 V
6.2
ns
td(off)
RG = 10 Ω
25
ns
5.8
ns
Rise Time
Turn-off Delay Time
Fall Time
tf
Total Gate Charge
QG
VDD = 24 V
10
nC
Gate to Source Charge
QGS
VGS = 10 V
1.9
nC
Gate to Drain Charge
QGD
ID = 8.0 A
2.6
nC
VF(S-D)
IF = 8.0 A, VGS = 0 V
0.81
V
Reverse Recovery Time
trr
IF = 8.0 A, VGS = 0 V
28
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/ µs
23
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
BVDSS
IAS
90%
VDS
VGS
0
VDS
10%
0
10%
Wave Form
VDS
ID
τ
VDD
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
td(on)
tr
ton
td(off)
tf
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG.
50 Ω
RL
VDD
Data Sheet G15781EJ1V0DS
3
µPA2751GR
TYPICAL CHARACTERISTICS (TA = 25°C)
A) CH1
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
40
4.5 V
35
10
1
ID - Drain Current - A
ID - Drain Current - A
Pulsed
VDS = 10 V
TA = −25˚C
25˚C
75˚C
150˚C
0.1
VGS = 10 V
30
4V
25
20
15
10
5
0.01
0
1
2
3
4
Pulsed
0
5
0
0.2
0.4
0.6
0.8
VDS - Drain to Source Voltage - V
100
VDS = 10 V
Pulsed
10
TA = 150˚C
75˚C
25˚C
−25˚C
1
0.1
0.01
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
4
1.0
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
Pulsed
40
ID = 9.0 A
30
4.5 A
20
10
0
0
5
10
15
20
VGS - Gate to Source Voltage - V
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
80
3.0
Pulsed
60
40
VGS = 4 V
20
4.5 V
10 V
0
0.1
1
10
VGS(off) - Gate Cut-off Voltage - V
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
VGS - Gate to Source Voltage - V
VDS = 10 V
ID = 1 mA
2.5
2.0
1.5
1.0
0.5
100
ID - Drain Current - A
0
−75 −50 −25
0
25
50
75 100 125 150 175
Tch - Channel Temperature - ˚C
Data Sheet G15781EJ1V0DS
µPA2751GR
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
100
Pulsed
ID = 4.5 A
VGS = 10 V
30
VGS = 4 V
4.5 V
20
10 V
10
0
−50 −25
0
25
50
75
4V
1
0.1
Pulsed
0.01
100 125 150 175
0
0.5
Tch - Channel Temperature - ˚C
1.5
SWITCHING CHARACTERISTICS
1000
td(on), tr, td(off), tf - Switching Time - ns
10000
Ciss, Coss, Crss - Capacitance - pF
1.0
VSD - Source to Drain Voltage - V
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
Ciss
1000
Coss
100
Crss
VGS = 0 V
f = 1 MHz
10
0.1
1
10
tr
100
td(off)
td(on)
10
tf
1
VDD = 15 V
VGS = 10 V
RG = 10 Ω
0.1
0.1
100
1
VDS - Drain to Source Voltage - V
di/dt = 100 A/ µ s
VGS = 0 V
100
10
1
0.1
1
10
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
VDS - Drain to Source Voltage - V
1000
10
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
trr - Reverse Recovery Time - ns
0V
10
35
14
30
12
VDD = 24 V
15 V
6V
25
20
10
8
VGS
15
6
10
4
100
IF - Drain Current - A
5
2
VDS
ID = 9 A
0
0
2
4
6
8
VGS - Gate to Source Voltage - V
40
ISD - Diode Forward Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
A) CH1
0
10 12 14 16 18 20 22
QG - Gate Charge - nC
Data Sheet G15781EJ1V0DS
5
µPA2751GR
A) CH1
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
PT - Total Power Dissipation - W/package
dT - Percentage of Rated Power - %
120
100
80
60
40
20
0
0
20
40
60
80
2.8
Mounted on ceramic
substrate of
2000 mm2 × 2.2 mm
2.4
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
0
0
100 120 140 160
20
TA - Ambient Temperature - ˚C
40
60
80
100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
)
ID - Drain Current - A
on
S(
RD GS
(V
10
d
ite
Lim0 V)
1
=
PW
ID(pulse)
=1
00
ID(DC)
1m
µs
s
10
Po
we
r
1
ms
10
Di
0m
s
ss
ipa
tio
nL
im
ite
d
0.1 Mounted on2ceramic substrate
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
Single Pulse
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1000 Mounted on ceramic substrate
2
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
Rth(ch-A) = 73.5˚C/W
100
10
1
0.1
0.0001
0.001
0.01
0.1
1
PW - Pulse Width - s
6
Data Sheet G15781EJ1V0DS
10
100
1000
µPA2751GR
A) CH1
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
10
RG = 25 Ω
VDD = 15 V
0V
VGS = 20
Starting Tch = 25˚C
IAS = 9 A
EAS = 8.1 mJ
1
10 µ
100 µ
1m
RG = 25 W
VDD = 15 V
0V
VGS = 20
IAS 9 A
120
Energy Derating Factor - %
IAS - Single Avalanche Current - A
100
100
80
60
40
20
10 m
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
Data Sheet G15781EJ1V0DS
7
µPA2751GR
TYPICAL CHARACTERISTICS (TA = 25°C)
B) CH2
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
40
35
10
1
ID - Drain Current - A
ID - Drain Current - A
Pulsed
VDS = 10 V
TA = −25˚C
25˚C
75˚C
150˚C
0.1
30
VGS = 10 V
4.5 V
25
20
4.0 V
15
10
5
0.01
0
1
2
3
4
Pulsed
0
5
0
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
VDS = 10 V
Pulsed
10
TA = 150˚C
75˚C
25˚C
−25˚C
1
0.1
0.01
0.1
1
10
100
8
1.4
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
80
Pulsed
60
ID = 8.0 A
40
4.0 A
20
0
0
5
10
15
20
VGS - Gate to Source Voltage - V
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
100
3.0
Pulsed
VGS(off) - Gate Cut-off Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
VGS - Gate to Source Voltage - V
0.2
0.4
0.6
0.8
1.0
1.2
VDS - Drain to Source Voltage - V
80
VGS = 4.0 V
60
40
4.5 V
20
10 V
0
0.1
1
10
VDS = 10 V
ID = 1 mA
2.5
2.0
1.5
1.0
0.5
100
ID - Drain Current - A
0
−75 −50 −25
0
25
50
75 100 125 150 175
Tch - Channel Temperature - ˚C
Data Sheet G15781EJ1V0DS
µPA2751GR
B) CH2
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
50 Pulsed
ID = 4.0 A
ISD - Diode Forward Current - A
100
40
VGS = 4 V
4.5 V
30
10 V
20
10
0
−50 −25
Pulsed
4V
10
0.1
0.01
0
25
50
75
0
100 125 150 175
1.0
0.5
1.5
VSD - Source to Drain Voltage - V
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
1000
td(on), tr, td(off), tf - Switching Time - ns
10000
Ciss, Coss, Crss - Capacitance - pF
0V
1
Tch - Channel Temperature - ˚C
1000
Ciss
Coss
100
Crss
VGS = 0 V
f = 1 MHz
10
0.1
1
10
100
tf
td(off)
td(on)
10
tr
1
VDD = 15 V
VGS = 10 V
RG = 10 Ω
0.1
0.1
100
1
VDS - Drain to Source Voltage - V
di/dt = 100 A/ µ s
VGS = 0 V
100
10
1
0.1
1
10
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
14
35
VDS - Drain to Source Voltage - V
1000
10
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
trr - Reverse Recovery Time - ns
VGS = 10 V
12
30
VDD = 24 V
15 V
6V
25
10
VGS
20
8
15
6
10
4
100
IF - Drain Current - A
5
2
VDS
ID = 8.0 A
0
0
2
4
6
8
10
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
0
12
QG - Gate Charge - nC
Data Sheet G15781EJ1V0DS
9
µPA2751GR
B) CH2
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
PT - Total Power Dissipation - W/package
dT - Percentage of Rated Power - %
120
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160
2.8
Mounted on ceramic
substrate of
2000 mm2 × 2.2 mm
2.4
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
0
0
20
TA - Ambient Temperature - ˚C
40
60
80
100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
ID - Drain Current - A
)
10
on
S(
RD GS
(V
d
ite
Lim0 V)
1
=
ID(pulse)
PW
1m
ID(DC)
10
Po
we
r
10
0m
=1
00
µs
ms
s
Dis
sip
ati
1
s
on
Lim
ite
d
0.1 Mounted on2ceramic substrate
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
Single Pulse
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1000 Mounted on ceramic substrate
2
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
Rth(ch-A) = 73.5˚C/W
100
10
1
0.1
0.0001
0.001
0.01
0.1
1
PW - Pulse Width - s
10
Data Sheet G15781EJ1V0DS
10
100
1000
µPA2751GR
B) CH2
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE ENERGY vs.
INDUCTIVE LOAD
10
RG = 25 Ω
VDD = 15 V
0V
VGS = 20
Starting Tch = 25˚C
IAS = 8 A
EAS = 6.4 mJ
1
10 µ
100 µ
1m
RG = 25 W
VDD = 15 V
0V
VGS = 20
IAS 8 A
120
Energy Derating Factor - %
IAS - Single Avalanche Energy - A
100
100
80
60
40
20
10 m
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
Data Sheet G15781EJ1V0DS
11
µPA2751GR
• The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4