ETC 2SK3062-Z

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3062
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
★ ORDERING INFORMATION
DESCRIPTION
The 2SK3062 is N-Channel MOS Field Effect Transistor
PART NUMBER
PACKAGE
2SK3062
TO-220AB
FEATURES
2SK3062-S
TO-262
• Low on-state resistance
2SK3062-ZJ
TO-263
2SK3062-Z
TO-220SMD
designed for high current switching applications.
RDS(on)1 = 8.5 mΩ MAX. (VGS = 10 V, ID = 35 A)
RDS(on)2 = 12 mΩ MAX. (VGS = 4.0 V, ID = 35 A)
Notes TO-220SMD package is produced only in
• Low Ciss: Ciss = 5200 pF TYP.
• Built-in gate protection diode
Japan
ABSOLUTE MAXIMUM RATINGS (T A = 25 °C)
(TO-220AB)
Drain to Source Voltage (VGS = 0 V)
VDSS
60
V
Gate to Source Voltage (VDS = 0 V)
VGSS(AC)
±20
V
Gate to Source Voltage (VDS = 0 V)
VGSS(DC)
+20, −10
V
ID(DC)
±70
A
ID(pulse)
±280
A
Total Power Dissipation (TC = 25°C)
PT
100
W
Total Power Dissipation (TA = 25°C)
PT
1.5
W
Channel Temperature
Tch
150
°C
Drain Current (DC) (TC = 25°C)
Drain Current (Pulse)
Note1
Tstg
–55 to +150
°C
Single Avalanche Current
Note2
IAS
35
A
Single Avalanche Energy
Note2
EAS
122.5
mJ
Storage Temperature
(TO-262)
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1 %
2. Starting Tch = 25 °C, VDD = 30 V, RG = 25 Ω, VGS = 20 → 0 V
(TO-263, TO-220SMD)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D13101EJ2V0DS00 (2nd edition)
Date Published April 2001 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1998,1999
2SK3062
ELECTRICAL CHARACTERISTICS (T A = 25 °C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 60 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
Gate Cut-off Voltage
VGS(off)
VDS = 10 V, ID = 1 mA
1.0
1.5
2.0
V
| yfs |
VDS = 10 V, ID = 35 A
20
87
RDS(on)1
VGS = 10 V, ID = 35 A
6.3
8.5
mΩ
RDS(on)2
VGS = 4.0 V, ID = 35 A
8.2
12
mΩ
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = 10 V
5200
pF
Output Capacitance
Coss
VGS = 0 V
1300
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
480
pF
Turn-on Delay Time
td(on)
VDD = 30 V ,ID = 35 A
75
ns
VGS(on) = 10 V
1150
ns
RG = 10 Ω
360
ns
480
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = 48 V
95
nC
Gate to Source Charge
QGS
VGS(on) = 10 V
13
nC
Gate to Drain Charge
QGD
ID = 70 A
30
nC
Body Diode Forward Voltage
VF(S-D)
IF = 70 A, VGS = 0 V
0.97
V
Reverse Recovery Time
trr
IF = 70 A, VGS = 0 V
70
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µ s
140
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90%
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10%
0 10%
Wave Form
τ
VDD
PG.
90%
BVDSS
VDS
ID
90%
VDD
ID
IAS
VGS(on)
10%
Data Sheet D13101EJ2V0DS
tr td(off)
td(on)
ton
tf
toff
2SK3062
TYPICAL CHARACTERISTICS (T A = 25 °C)
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
140
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
0
25
50
75
120
100
80
60
40
20
0
100 125 150 175 200
25
TC - Case Temperature - °C
★
50
75
100 125 150 175 200
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
1000
ID - Drain Current - A
ID(pulse)
100
d
ite )
Lim 10 V
n)
(o
=
S
S
RD t VG
(a
1m
s
ID(DC)
PW
10
0µ
s
=1
0µ
s
10
ms
10
0m
s
DC
Po
Lim wer
ite Dis
d
sip
ati
on
10
1
0.1
0.1
TC = 25˚C
Single Pulse
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1000
100
Rth(ch-A)= 83.3 ˚C/W
10
Rth(ch-C)= 1.25 ˚C/W
1
0.1
0.01
0.001
10 µ
TC = 25˚C
Single Pulse
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet D13101EJ2V0DS
3
2SK3062
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
10
ID - Drain Current - A
ID - Drain Current - A
Pulsed
TA = 125˚C
75˚C
25˚C
−25˚C
1
VGS = 10 V
200
VGS = 4.0 V
100
0.1
0
1
2
Pulsed
VDS = 10 V
4
5
3
0
10
1
0.1
1.0
VDS = 10 V
Pulsed
100
10
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
Tch = −25˚C
25˚C
75˚C
125˚C
20
10
ID = 35 A
0
20
VGS = 4.0 V
10
10 V
0
0.1
1
10
100
10
15
1000
VDS = 10 V
ID = 1 mA
2.0
1.5
1.0
0.5
0
ID - Drain Current - A
4
5
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
Pulsed
30
4
3
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
30
Pulsed
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
VGS(off) - Gate to Source Cut-off Voltage - V
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
2
1
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
−50
0
50
100
150
Tch - Channel Temperature - ˚C
Data Sheet D13101EJ2V0DS
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
VGS = 4.0 V
15
10 V
10
5
Ciss, Coss, Crss - Capacitance - nF
0V
10
1
0.1
ID = 35 A
−50
0
50
100
Pulsed
0
150
0.5
VSD - Source to Drain Voltage - V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
VGS = 0 V
f = 1 MHz
10
Ciss
1
Coss
Crss
1
10
VDS = 30 V
VGS = 10 V
RG = 10 Ω
10000
100
tr
1000
tf
td(off)
td(on)
100
10
1
0.1
VDS - Drain to Source Voltage - V
di/dt = 100 A /µ s
VGS = 0 V
100
10
1
10
100
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
1000
10
100
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1
0.1
1.5
1
Tch - Channel Temperature - ˚C
100
0.1
0.1
VGS = 4.0 V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
80
16
ID = 70 A
14
60
12
VDD = 12 V
30 V
48 V
40
10
8
6
4
20
2
0
25
50
75
100
VGS - Gate to Source Voltage - V
0
100
ISD - Diode Forward Current - A
20
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
td(on), tr, td(off), tf - Switching Time - ns
RDS(on) - Drain to Source On-state Resistance - mΩ
2SK3062
0
QG - Gate Charge - nC
IF - Drain Current - A
Data Sheet D13101EJ2V0DS
5
2SK3062
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
160
IAS = 35 A
EAS
10
=1
22.
5m
120
100
80
60
40
20
1m
L - Inductive Load - H
6
J
1.0
RG = 25 Ω
VDD = 30 V
VGS = 20 V → 0 V
Starting
Tch = 25 °C
0.1
100 µ
10 µ
VDD = 30 V
RG = 25 Ω
VGS = 20 V → 0 V
IAS ≤ 35 A
140
Energy Derating Factor - %
IAS - Single Avalanche Current - A
100
10 m
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
Data Sheet D13101EJ2V0DS
2SK3062
PACKAGE DRAWINGS (Unit : mm)
4.8 MAX.
10.6 MAX.
φ 3.6±0.2
(10)
1.3±0.2
10.0
4.8 MAX.
1.3±0.2
4
1
1 2 3
3
12.7 MIN.
6.0 MAX.
1.3±0.2
1.3±0.2
2.54 TYP.
2.8±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
3)TO-263 (MP-25ZJ)
4) TO-220SMD(MP-25Z)
4.8 MAX.
(10)
4.8 MAX.
1.3±0.2
4
2.8±0.2
3 2.54 TYP.
(
0.5±0.2
1.0±0.3
2.54 TYP. 1
1.Gate
2.Drain
3.Source
4.Fin (Drain)
3.0±0.5
1.4±0.2
)
R
0.8
8.5±0.2
1.0±0.5
)
.5R
(0
1.1±0.4
0.7±0.2
2
)
.5R R)
.8
0
(
(0
0.5±0.2
3 2.54 TYP.
2.8±0.2
5.7±0.4
8.5±0.2
1.0±0.5
4
1.4±0.2
2
Note
(10)
1.3±0.2
2.54 TYP. 1
2.8±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.75±0.1
2.54 TYP.
2
8.5±0.2
15.5 MAX.
5.9 MIN.
4
12.7 MIN.
3.0±0.3
2)TO-262 (MP-25 Fin Cut)
1.0±0.5
1)TO-220AB (MP-25)
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Note This Package is produced only in Japan.
EQUIVALENT CIRCUIT
Drain
Remark
Body
Diode
Gate
The diode connected between the gate and source of the transistor
serves as a protector against ESD. When this device actually used,
an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Gate
Protection
Diode
Source
Data Sheet D13101EJ2V0DS
7
2SK3062
• The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
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(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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M8E 00. 4