DATA SHEET MOS INTEGRATED CIRCUIT µPD23C16340, 23C16380 16M-BIT MASK-PROGRAMMABLE ROM 2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE Description The µPD23C16340 and µPD23C16380 are 16,777,216 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits). The active levels of OE (Output Enable Input) can be selected with mask-option. The µPD23C16340 and µPD23C16380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA. Features • Pin compatible with NOR Flash Memory • Word organization 2,097,152 words by 8 bits (BYTE mode) 1,048,576 words by 16 bits (WORD mode) • Page access mode BYTE mode : 8 byte random page access (µPD23C16340) 16 byte random page access (µPD23C16380) WORD mode : 4 word random page access (µPD23C16340) 8 word random page access (µPD23C16380) • Operating supply voltage : VCC = 2.7 V to 3.6 V Operating supply Access time / Power supply current (Active mode) Standby current voltage Page access time mA (MAX.) (CMOS level input) VCC ns (MAX.) µPD23C16340 µPD23C16380 µA (MAX.) 3.0 V ± 0.3 V 90 / 25 40 55 30 3.3 V ± 0.3 V 85 / 25 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15709EJ2V0DS00 (2nd edition) Date Published February 2003 NS CP(K) Printed in Japan The mark shows major revised points. 2001 µPD23C16340, 23C16380 Ordering Information Part Number Package µPD23C16340GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) µPD23C16340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6) µPD23C16380GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) µPD23C16380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6) (xxx : ROM code suffix No.) 2 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 Pin Configurations /xxx indicates active low signal. 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) [ µPD23C16340GZ-xxx-MJH ] [ µPD23C16380GZ-xxx-MJH ] Marking Side A15 1 48 A16 A14 2 47 WORD, /BYTE A13 3 46 GND A12 4 45 O15, A−1 A11 5 44 O7 A10 6 43 O14 A9 7 42 O6 A8 8 41 O13 A19 9 40 O5 NC 10 39 O12 NC 11 38 O4 NC 12 37 VCC NC 13 36 O11 NC 14 35 O3 NC 15 34 O10 A18 16 33 O2 A17 17 32 O9 A7 18 31 O1 A6 19 30 O8 A5 20 29 O0 A4 21 28 /OE or OE or DC A3 22 27 GND A2 23 26 /CE A1 24 25 A0 A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M15709EJ2V0DS 3 µPD23C16340, 23C16380 48-pin TAPE FBGA (8 x 6) [ µPD23C16340F9-xxx-BC3 ] [ µPD23C16380F9-xxx-BC3 ] Top View Bottom View 6 5 4 3 2 1 A 6 B C D E F G H H A B C D E F G H A13 A12 A14 A15 A16 WORD, O15, GND /BYTE A–1 6 G F E D C B A H G F E D C B A GND O15, WORD, A16 A15 A14 A12 A13 A–1 /BYTE 5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9 4 NC NC NC A19 O5 O12 VCC O4 4 O4 VCC O12 O5 A19 NC NC NC 3 NC NC A18 NC O2 O10 O11 O3 3 O3 O11 O10 O2 NC A18 NC NC 2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7 1 A3 A4 A2 A1 A0 /CE /OE or GND 1 GND /OE or /CE A0 A1 A2 A4 A3 OE A0 to A19 OE : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark. 4 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 Input / Output Pin Functions Pin name WORD, /BYTE Input / Output Input Function The pin for switching WORD mode and BYTE mode. High level : WORD mode (1M-word by 16-bit) Low level : BYTE mode (2M-word by 8-bit) A0 to A19 Input (Address inputs) Address input pins. A0 to A19 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) A0 to A19 are used as 20 bits address signals. BYTE mode (2M-word by 8-bit) A0 to A19 are used as the upper 20 bits of total 21 bits of address signal. (The least significant bit (A−1) is combined to O15.) O0 to O7, O8 to O14 Output (Data outputs) Data output pins. O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) The lower 15 bits of 16 bits data outputs to O0 to O14. (The most significant bit (O15) combined to A−1.) BYTE mode (2M-word by 8-bit) 8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. O15, A−1 Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) (Data output 15, LSB Address input) The most significant output data bus (O15). BYTE mode (2M-word by 8-bit) The least significant address bus (A−1). /CE Input (Chip Enable) Chip activating signal. When the OE is active, output states are following. High level : High-Z Low level : Data out /OE or OE or DC Input (Output Enable, Don't care) Output enable signal. The active level of OE is mask option. The active level of OE can be selected from high active, low active and Don’t care at order. VCC − Supply voltage GND − Ground NC − Not internally connected. (The signal can be connected.) Data Sheet M15709EJ2V0DS 5 µPD23C16340, 23C16380 Block Diagram O9 O8 O0 A0 O1 O10 O2 O11 O3 O13 O12 O4 O5 O6 O14 O15, A 1 O7 A2 A3 Y-Selector A4 Logic/Input Y-Decoder Output Buffer A1 WORD, /BYTE /OE or OE or DC A5 A9 A10 A11 A12 A13 Memory Cell Matrix 1,048,576 words by 16 bits / 2,097,152 words by 8 bits A14 A15 A16 A17 A18 A19 6 Data Sheet M15709EJ2V0DS Input Buffer A8 X-Decoder A7 Address Input Buffer A6 /CE µPD23C16340, 23C16380 Mask Option The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. Option /OE or OE or DC OE active level 0 /OE L 1 OE H x DC Don’t care Operation modes for each option are shown in the tables below. Operation mode (Option : 0) /CE /OE Mode Output state L L Active Data out H H H or L High-Z Standby High-Z Operation mode (Option : 1) /CE OE Mode Output state L L Active High-Z H H H or L Data out Standby High-Z Operation mode (Option : x) /CE DC Mode Output state L H or L Active Data out H H or L Standby High-Z Remark L : Low level input H : High level input Data Sheet M15709EJ2V0DS 7 µPD23C16340, 23C16380 Electrical Specifications Absolute Maximum Ratings Parameter Rating Unit VCC –0.3 to +4.6 V Input voltage VI –0.3 to VCC+0.3 V Output voltage VO –0.3 to VCC+0.3 V Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Supply voltage Symbol Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 °C) Parameter Symbol Input capacitance CI Output capacitance CO Test condition MIN. TYP. MAX. Unit 10 pF 12 pF MAX. Unit 2.0 VCC + 0.3 V VCC = 3.0 V ± 0.3 V –0.3 +0.5 V VCC = 3.3 V ± 0.3 V –0.5 +0.8 2.4 f = 1 MHz DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol High level input voltage VIH Low level input voltage VIL Test conditions High level output voltage VOH IOH = –100 µA Low level output voltage VOL IOL = 2.1 mA MIN. TYP. V 0.4 V Input leakage current ILI VI = 0 V to VCC –10 +10 µA Output leakage current ILO VO = 0 V to VCC, Chip deselected –10 +10 µA Power supply current ICC1 /CE = VIL (Active mode), µPD23C16340 40 mA µPD23C16380 55 IO = 0 mA Standby current 8 ICC3 /CE = VCC – 0.2 V (Standby mode) Data Sheet M15709EJ2V0DS 30 µA µPD23C16340, 23C16380 AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V MIN. TYP. MAX. VCC = 3.3 V ± 0.3 V MIN. TYP. Unit MAX. Address access time tACC 90 85 ns Page access time tPAC 25 25 ns Address skew time tSKEW 10 10 ns Note Chip enable access time tCE 90 85 ns Output enable access time tOE 25 25 ns Output hold time tOH 0 Output disable time tDF 0 WORD, /BYTE access time tWB 0 25 0 90 ns 25 ns 85 ns Note tSKEW indicates the following three types of time depending on the condition. 1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the next address is determined. 2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the /CE high level input point. 3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched from high level to low level following address determination, or when the address is changed after /CE is switched from low level to high level. Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. AC Test Conditions Input waveform (Rise / Fall time ≤ 5 ns) 1.4 V Test points 1.4 V 1.4 V Test points 1.4 V Output waveform Output load 1TTL + 100 pF Data Sheet M15709EJ2V0DS 9 µPD23C16340, 23C16380 Cautions on power application To ensure normal operation, always apply power using /CE following the procedure shown below. 1) Input a high level to /CE during and after power application. 2) Hold the high level input to /CE for 200 ns or longer (wait time). 3) Start normal operation after the wait time has elapsed. Power Application Timing Chart 1 (When /CE is made high at power application) Wait time Normal operation /CE (Input) 200 ns or longer VCC Power Application Timing Chart 2 (When /CE is made high after power application) Wait time /CE (Input) 200 ns or longer VCC Caution Other signals can be either high or low during the wait time. 10 Data Sheet M15709EJ2V0DS Normal operation µPD23C16340, 23C16380 Read Cycle Timing Chart 1 tSKEW tSKEW tSKEW A0 to A19, (Input) A−1 Note1 tACC tACC tACC /CE (Input) tDF Note2 tCE tDF Note2 /OE or OE (Input) tOE O0 to O7, (Input) O8 to O15 Note3 High-Z tOH Data out tOH High-Z Data out tOH Data out Notes 1. During WORD mode, A–1 is O15. 2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. Data Sheet M15709EJ2V0DS 11 µPD23C16340, 23C16380 Read Cycle Timing Chart 2 (Page Access Mode) Upper address Note 1 (Input) A2 to A19 A3 to A19 tACC /CE (Input) tCE /OE or OE (Input) tOE Page address Note 1 A–1 Note 2, A0, A1 A–1 Note 2, A0, A1, A2 (Input) tPAC Note 5 tPAC Note 5 tDF Note 3 tOH tOH Data Out Data Out tOH High-Z O0 to O7, (Output) O8 to O15 Note 4 High-Z Data Out Notes 1. The address differs depending on the product as follows. Part Number Upper address Page address µPD23C16340 A2 to A19 A–1, A0, A1 µPD23C16380 A3 to A19 A–1, A0, A1, A2 2. During WORD mode, A–1 is O15. 3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. 5. The definition of page access time is as follows. [ µPD23C16340 ] Page access time Upper address (A2 to A19) /CE input condition /OE or OE input condition Before tCE – tPAC Before stabilizing of page inputs condition tPAC Before tACC – tPAC address (A–1, A0, A1) [ µPD23C16380 ] Page access time Upper address (A3 to A19) /CE input condition /OE or OE input condition Before tCE – tPAC Before stabilizing of page inputs condition tPAC Before tACC – tPAC address (A–1, A0, A1, A2) 12 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 WORD, /BYTE Switch Timing Chart A–1 (Input) High-Z High-Z WORD, /BYTE (Input) tOH O0 to O7 (Output) tACC Data Out tOH Data Out tWB Data Out tDF O8 to O15 (Output) Remark High-Z Data Out Data Out Chip Enable (/CE) and Output Enable (/OE or OE) : Active. Data Sheet M15709EJ2V0DS 13 µPD23C16340, 23C16380 Package Drawings 48-PIN PLASTIC TSOP (I) (12x20) detail of lead end 1 48 F G R Q 24 L 25 S E P I A J C S K N S NOTES 1) Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) B D M M ITEM A MILLIMETERS 12.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 18.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 20.0±0.2 Q 3° +5° −3° R 0.25 S 0.60±0.15 S48GZ-50-MJH-1 14 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 48-PIN TAPE FBGA(8x6) ZD w S B E ZE B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A y1 A2 S S y e S φb φx A1 M S AB ITEM D MILLIMETERS 6.0±0.1 E 8.0±0.1 w 0.2 e 0.80 A 0.97±0.10 A1 0.27±0.05 A2 0.70 b 0.45±0.05 x 0.08 y 0.1 y1 0.2 ZD 1.00 ZE 1.20 P48F9-80-BC3 Data Sheet M15709EJ2V0DS 15 µPD23C16340, 23C16380 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD23C16340 and µPD23C16380. Types of Surface Mount Device µPD23C16340GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) µPD23C16340F9-BC3 : 48-pin TAPE FBGA (8 x 6) µPD23C16380GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) µPD23C16380F9-BC3 : 48-pin TAPE FBGA (8 x 6) 16 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 Revision History Edition/ Page Date Type of This Previous edition edition Location Preliminary Data Sheet → Data Sheet 2nd edition/ Throughout Throughout Modification Feb. 2003 p.9 p.9 Addition Description (Previous edition → This edition) revision AC Characteristics Address skew time (tSKEW ) Note p.10 – Addition Cautions on power application p.11 p.10 Modification Read Cycle Timing Chart 1 p.15 p.14 Modification Package Drawings Data Sheet M15709EJ2V0DS Preliminary version → Standard version 17 µPD23C16340, 23C16380 [MEMO] 18 Data Sheet M15709EJ2V0DS µPD23C16340, 23C16380 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS FOR CMOS Note: Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or NMOS devices. If the input of a CMOS device stays in an area that is between V IL (MAX.) and V IH (MIN.) due to the effects of noise or some other irregularity, malfunction may result. Therefore, not only the input waveform is fixed, but also the waveform changes, it is important to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS devices should not be operated in a state where nothing is connected, so input levels of CMOS devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15709EJ2V0DS 19 µPD23C16340, 23C16380 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of February, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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