DATA SHEET MOS INTEGRATED CIRCUIT µPD23C64300 64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE) Description The µPD23C64300 is a 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits). The active levels of OE (Output Enable Input) can be selected with mask-option. The µPD23C64300 is packed in 48-pin TAPE FBGA. Features • Pin compatible with NOR Flash Memory • Word organization 8,388,608 words by 8 bits (BYTE mode) 4,194,304 words by 16 bits (WORD mode) • Operating supply voltage : VCC = 2.7 V to 3.6 V Operating supply voltage Access time Power supply current (Active mode) Standby current (CMOS level input) VCC ns (MAX.) mA (MAX.) µA (MAX.) 3.0 V ± 0.3 V 100 40 30 3.3 V ± 0.3 V 90 55 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. 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Document No. M16056EJ4V1DS00 (4th edition) Date Published July 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2002 µPD23C64300 Ordering Information Part Number Package µPD23C64300F9-xxx-BC3 48-pin TAPE FBGA (8 x 6) (xxx : ROM code suffix No.) Marking Image Part Number Marking ( F ) µPD23C64300F9-xxx-BC3 A J R64 -xxx ROM code suffix No. INDEX MARK 2 Lot No. Data Sheet M16056EJ4V1DS µPD23C64300 Pin Configuration /xxx indicates active low signal. 48-pin TAPE FBGA (8 x 6) Top View Bottom View 6 5 4 3 2 1 A 6 B C D E F G H H A B C D E F G H A13 A12 A14 A15 A16 WORD, O15, GND /BYTE A–1 6 G F E D C B A H G F E D C B A GND O15, WORD, A16 A15 A14 A12 A13 A–1 /BYTE 5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9 4 NC NC A21 A19 O5 O12 VCC O4 4 O4 VCC O12 O5 A19 A21 NC NC 3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC 2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7 1 A3 A4 A2 A1 A0 /CE /OE or GND 1 GND /OE or /CE A0 A1 A2 A4 A3 OE A0 to A21 OE : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawing for the index mark. Data Sheet M16056EJ4V1DS 3 µPD23C64300 Input / Output Pin Functions Pin name WORD, /BYTE Input / Output Input Function The pin for switching WORD mode and BYTE mode. High level : WORD mode (4M-word by 16-bit) Low level : BYTE mode (8M-word by 8-bit) A0 to A21 Input (Address inputs) Address input pins. A0 to A21 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) A0 to A21 are used as 22 bits address signals. BYTE mode (8M-word by 8-bit) A0 to A21 are used as the upper 22 bits of total 23 bits of address signal. (The least significant bit (A−1) is combined to O15.) O0 to O7, O8 to O14 Output (Data outputs) Data output pins. O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) The lower 15 bits of 16 bits data outputs to O0 to O14. (The most significant bit (O15) combined to A−1.) BYTE mode (8M-word by 8-bit) 8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. O15, A−1 Output, Input (Data output 15, O15, A−1 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) LSB Address input) The most significant output data bus (O15). BYTE mode (8M-word by 8-bit) The least significant address bus (A−1). /CE Input (Chip Enable) Chip activating signal. When the OE is active, output states are following. High level : High-Z Low level : Data out /OE or OE or DC Input Output enable signal. The active level of OE is mask option. The active level of OE can be selected from high active, low active and Don’t care at order. (Output Enable, Don't care) VCC − Supply voltage GND − Ground NC − Not internally connected. (The signal can be connected.) 4 Data Sheet M16056EJ4V1DS µPD23C64300 Block Diagram A0 O10 O9 O8 O0 O1 O2 O11 O3 O13 O12 O4 O5 O6 O14 O15, A−1 O7 A2 A3 Y-Selector A4 Logic/Input Y-Decoder Output Buffer A1 WORD, /BYTE /OE or OE or DC A5 A9 A10 A11 A12 A13 Memory Cell Matrix 4,194,304 words by 16 bits / 8,388,608 words by 8 bits A14 Input Buffer A8 X-Decoder A7 Address Input Buffer A6 /CE A15 A16 A17 A18 A19 A20 A21 Data Sheet M16056EJ4V1DS 5 µPD23C64300 Mask Option The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. Option /OE or OE or DC OE active level 0 /OE L 1 OE H x DC Don’t care Operation modes for each option are shown in the tables below. Operation mode (Option : 0) /CE /OE Mode Output state L L Active Data out H H H or L High-Z Standby High-Z Operation mode (Option : 1) /CE OE Mode Output state L L Active High-Z H H H or L Data out Standby High-Z Operation mode (Option : x) /CE DC Mode Output state L H or L Active Data out H H or L Standby High-Z Remark L : Low level input H : High level input 6 Data Sheet M16056EJ4V1DS µPD23C64300 Electrical Specifications Absolute Maximum Ratings Parameter Rating Unit VCC –0.3 to +4.6 V Input voltage VI –0.3 to VCC+0.3 V Output voltage VO –0.3 to VCC+0.3 V Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Supply voltage Symbol Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 °C) Parameter Symbol Input capacitance CI Output capacitance CO Test condition MIN. TYP. MAX. Unit 10 pF 12 pF MAX. Unit 2.0 VCC + 0.3 V VCC = 3.0 V ± 0.3 V –0.3 +0.5 V VCC = 3.3 V ± 0.3 V –0.3 +0.8 2.4 f = 1 MHz DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol High level input voltage VIH Low level input voltage VIL Test conditions High level output voltage VOH IOH = –100 µA Low level output voltage VOL IOL = 2.1 mA MIN. TYP. V 0.4 V Input leakage current ILI VI = 0 V to VCC –10 +10 µA Output leakage current ILO VO = 0 V to VCC, Chip deselected –10 +10 µA Power supply current ICC1 /CE = VIL (Active mode), VCC = 3.0 V ± 0.3 V 40 mA VCC = 3.3 V ± 0.3 V 55 IO = 0 mA Standby current ICC3 /CE = VCC – 0.2 V (Standby mode) Data Sheet M16056EJ4V1DS 30 µA 7 µPD23C64300 AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V MIN. Address access time tACC Address skew time tSKEW TYP. Note MAX. VCC = 3.3 V ± 0.3 V MIN. TYP. Unit MAX. 100 90 ns 10 10 ns Chip enable access time tCE 100 90 ns Output enable access time tOE 25 25 ns Output hold time tOH 0 Output disable time tDF 0 WORD, /BYTE access time tWB 0 25 0 100 ns 25 ns 90 ns Note tSKEW indicates the following three types of time depending on the condition. 1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the next address is determined. 2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the /CE high level input point. 3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched from high level to low level following address determination, or when the address is changed after /CE is switched from low level to high level. Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. AC Test Conditions Input waveform (Rise / Fall time ≤ 5 ns) 1.4 V Test points 1.4 V 1.4 V Test points 1.4 V Output waveform Output load 1TTL + 100 pF 8 Data Sheet M16056EJ4V1DS µPD23C64300 Cautions on power application To ensure normal operation, always apply power using /CE following the procedure shown below. 1) Input a high level to /CE during and after power application. 2) Hold the high level input to /CE for 200 ns or longer (wait time). 3) Start normal operation after the wait time has elapsed. Power Application Timing Chart 1 (When /CE is made high at power application) Wait time Normal operation /CE (Input) 200 ns or longer VCC Power Application Timing Chart 2 (When /CE is made high after power application) Wait time Normal operation /CE (Input) 200 ns or longer VCC Caution Other signals can be either high or low during the wait time. Data Sheet M16056EJ4V1DS 9 µPD23C64300 Read Cycle Timing Chart tSKEW tSKEW tSKEW A0 to A21, (Input) A−1 Note1 tACC tACC tACC /CE (Input) tDF Note2 tDF Note2 tCE /OE or OE (Input) tOH tOE O0 to O7, (Input) O8 to O15 Note3 High-Z tOH High-Z Data out tOH Data out Data out Notes 1. During WORD mode, A–1 is O15. 2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. WORD, /BYTE Switch Timing Chart A–1 (Input) High-Z High-Z WORD, /BYTE (Input) tOH O0 to O7 (Output) tACC Data Out tOH Data Out tWB Data Out tDF O8 to O15 (Output) Remark 10 High-Z Data Out Chip Enable (/CE) and Output Enable (/OE or OE) : Active. Data Sheet M16056EJ4V1DS Data Out µPD23C64300 Package Drawing 48-PIN TAPE FBGA(8x6) ZD w S B E ZE B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A y1 A2 S S y e S φb φx A1 M S AB ITEM D MILLIMETERS 6.0±0.1 E 8.0±0.1 w 0.2 e 0.80 A 0.97±0.10 A1 0.27±0.05 A2 0.70 b 0.45±0.05 x 0.08 y 0.1 y1 0.2 ZD 1.00 ZE 1.20 P48F9-80-BC3 Data Sheet M16056EJ4V1DS 11 µPD23C64300 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD23C64300. Type of Surface Mount Device µPD23C64300F9-BC3 12 : 48-pin TAPE FBGA (8 x 6) Data Sheet M16056EJ4V1DS µPD23C64300 Revision History Edition/ Date 4th edition/ Feb. 2004 Page Type of This Previous edition edition Throughout Throughout Location Deletion Description (Previous edition → This edition) revision Ordering Information µPD23C64300GZ-xxx-MJH Package 48-pin PLASTIC TSOP (I) (12 x 20) (Normal bent) Data Sheet M16056EJ4V1DS 13 µPD23C64300 [MEMO] 14 Data Sheet M16056EJ4V1DS µPD23C64300 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. Data Sheet M16056EJ4V1DS 15 µPD23C64300 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of July, 2004. The information is subject to change without notice. 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