ETC UPD23C128000LGY-XXX-MK

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD23C128000L
128M-BIT MASK-PROGRAMMABLE ROM
16M-WORD BY 8-BIT (BYTE MODE) / 8M-WORD BY 16-BIT (WORD MODE)
Description
The µPD23C128000L is a 134,217,728 bits mask-programmable ROM. The word organization is selectable (BYTE
mode : 16,777,216 words by 8 bits, WORD mode : 8,388,608 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The µPD23C128000L is packed in 48-pin plastic TSOP(I).
Features
• Word organization
16,777,216 words by 8 bits (BYTE mode)
8,388,608 words by 16 bits (WORD mode)
• Operating supply voltage : VCC = 2.7 to 3.6 V
Operating supply voltage
Access time
Power supply current (Active mode)
Standby current (CMOS level input)
VCC
ns (MAX.)
mA (MAX.)
µA (MAX.)
3.3 V ± 0.3 V
110
55
30
3.0 V ± 0.3 V
120
50
30
Ordering Information
Part Number
Package
µPD23C128000LGY-xxx-MJH
48-pin Plastic TSOP(I) (12 x 18) (Normal bent)
µPD23C128000LGY-xxx-MKH
48-pin Plastic TSOP(I) (12 x 18) (Reverse bent)
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13644EJ3V0DS00 (3rd edition)
Date Published November 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1998
µPD23C128000L
•
Pin Configurations (Marking Side)
/xxx indicates active low signal.
48-pin plastic TSOP(I) (12 x 18) (Normal bent)
[ µPD23C128000LGY-xxx-MJH ]
WORD, /BYTE
1
48
GND
A16
2
47
GND
A15
3
46
O15, A–1
A14
4
45
O7
A13
5
44
O14
A12
6
43
O6
A11
7
42
O13
A10
8
41
O5
A9
9
40
O12
A8
10
39
O4
A19
11
38
VCC
A21
12
37
VCC
A20
13
36
A22
A18
14
35
O11
A17
15
34
O3
A7
16
33
O10
A6
17
32
O2
A5
18
31
O9
A4
19
30
O1
A3
20
29
O8
A2
21
28
O0
A1
22
27
/OE, OE, DC
A0
23
26
GND
/CE
24
25
GND
A0 - A22
: Address inputs
O0 - O7, O8 - O14
: Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select
/CE
: Chip Enable
/OE, OE
: Output Enable
VCC
: Supply voltage
GND
: Ground
DC
: Don’t Care
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M13644EJ3V0DS00
µPD23C128000L
48-pin plastic TSOP(I) (12 x 18) (Reverse bent)
[ µPD23C128000LGY-xxx-MKH ]
GND
48
1
WORD, /BYTE
GND
47
2
A16
O15, A–1
46
3
A15
O7
45
4
A14
O14
44
5
A13
O6
43
6
A12
O13
42
7
A11
O5
41
8
A10
O12
40
9
A9
O4
39
10
A8
VCC
38
11
A19
VCC
37
12
A21
A22
36
13
A20
O11
35
14
A18
O3
34
15
A17
O10
33
16
A7
O2
32
17
A6
O9
31
18
A5
O1
30
19
A4
O8
29
20
A3
O0
28
21
A2
/OE, OE, DC
27
22
A1
GND
26
23
A0
GND
25
24
/CE
A0 - A22
: Address inputs
O0 - O7, O8 - O14
: Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select
/CE
: Chip Enable
/OE, OE
: Output Enable
VCC
: Supply voltage
GND
: Ground
DC
: Don’t Care
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M13644EJ3V0DS00
3
µPD23C128000L
Input / Output Pin Functions
Pin name
WORD, /BYTE
Input / Output
Input
Function
The pin for switching WORD mode and BYTE mode.
High level : WORD mode (8M-word by 16-bit)
Low level : BYTE mode (16M-word by 8-bit)
A0 to A22
Input
(Address inputs)
Address input pins.
A0 to A22 are used differently in the WORD mode and the BYTE mode.
WORD mode (8M-word by 16-bit)
A0 to A22 are used as 23 bits address signals.
BYTE mode (16M-word by 8-bit)
A0 to A22 are used as the upper 23 bits of total 24 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
Output
(Data outputs)
Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (8M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (16M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
(Data output 15,
WORD mode (8M-word by 16-bit)
LSB Address input)
The most significant output data bus (O15).
BYTE mode (16M-word by 8-bit)
The least significant address bus (A−1).
/CE
Input
(Chip Enable)
Chip activating signal.
When the OE is active, output states are following.
High level : High impedance
Low level : Data out
/OE, OE, DC
Input
(Output Enable, Don’t Care)
Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
VCC
−
Supply voltage
GND
−
Ground
4
Data Sheet M13644EJ3V0DS00
µPD23C128000L
Block Diagram
O9
O8
O0
A0
O1
O10
O2
O11
O3
O13
O12
O4
O5
O6
O14
O15, A–1
O7
A2
A3
Y-Selector
A4
Logic/Input
Y-Decoder
Output Buffer
A1
WORD, /BYTE
/OE, OE, DC
A5
A9
A10
A11
A12
A13
Memory Cell Matrix
8,388,608 words by 16 bits /
16,777,216 words by 8 bits
A14
Input Buffer
A8
X-Decoder
A7
Address Input Buffer
A6
/CE
A15
A16
A17
A18
A19
A20
A21
A22
Data Sheet M13644EJ3V0DS00
5
µPD23C128000L
Mask Option
The active levels of output enable pin (/OE, OE, DC) are mask programmable and optional, and can be selected from
among " 0 " " 1 " " x " shown in the table below.
Option
/OE, OE, DC
OE active level
0
/OE
L
1
OE
H
x
DC
Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE
/OE
Mode
Output state
L
L
Active
Data out
H
H
H or L
High impedance
Standby
High impedance
Operation mode (Option : 1)
/CE
OE
Mode
Output state
L
L
Active
High impedance
H
H
H or L
Data out
Standby
High impedance
Operation mode (Option : x)
/CE
DC
Mode
Output state
L
H or L
Active
Data out
H
H or L
Standby
High impedance
Remark L : Low level input
H : High level input
6
Data Sheet M13644EJ3V0DS00
µPD23C128000L
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC
–0.3 to +4.6
V
Input voltage
VI
–0.3 to VCC+0.3
V
Output voltage
VO
–0.3 to VCC+0.3
V
Operating ambient temperature
TA
–10 to +70
°C
Storage temperature
Tstg
–65 to +150
°C
Supply voltage
Condition
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter
Symbol
MAX.
Unit
10
pF
12
pF
MAX.
Unit
2.2
VCC + 0.3
V
VCC = 3.0 V ± 0.3 V
–0.3
+0.5
V
VCC = 3.3 V ± 0.3 V
–0.3
+0.8
2.4
Input capacitance
CI
Output capacitance
CO
Test condition
MIN.
TYP.
f = 1 MHz
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
High level input voltage
VIH
Low level input voltage
VIL
Test conditions
High level output voltage
VOH
IOH = –100 µA
Low level output voltage
VOL
IOL = 2.1 mA
MIN.
TYP.
V
0.4
V
Input leakage current
ILI
VI = 0 V to VCC
–10
+10
µA
Output leakage current
ILO
VO = 0 V to VCC, Chip deselected
–10
+10
µA
Power supply current
ICC1
/CE = VIL (Active mode), VCC = 3.0 V ± 0.3 V
50
mA
VCC = 3.3 V ± 0.3 V
55
IO = 0 mA
Standby current
ICC3
/CE = VCC – 0.2 V (Standby mode)
Data Sheet M13644EJ3V0DS00
30
µA
7
µPD23C128000L
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
Test condition
VCC = 3.0 V ± 0.3 V
VCC = 3.3 V ± 0.3 V
MIN.
MIN
TYP.
MAX.
TYP.
Unit
MAX.
Address access time
tACC
120
110
ns
Chip enable access time
tCE
120
110
ns
Output enable access time
tOE
40
30
ns
Output hold time
tOH
0
Output disable time
tDF
0
WORD, /BYTE access time
tWB
Remark
0
30
120
tDF is the time from inactivation of /CE or /OE, OE to high-impedance state output.
AC Test Conditions
Input waveform (Rise / Fall Time ≤ 5 ns)
1.4 V
Test points
1.4 V
1.4 V
Test points
1.4 V
Output waveform
Output load
1TTL + 100 pF
8
0
Data Sheet M13644EJ3V0DS00
ns
25
ns
110
ns
µPD23C128000L
Read Cycle Timing Chart
A0 to A22, (Input)
A–1Note 1
tACC
/CE (Input)
tDFNote 2
tCE
/OE, OE (Input)
tOE
tOH
High impedance
O0 to O7,
(Output)
O8 to O15Note 3
Data Out
Notes 1. During WORD mode, A–1 is O15.
2. tDF is specified when one of /CE, /OE, OE is inactivated.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
WORD, /BYTE Switch Timing Chart
A–1 (Input)
High impedance
High impedance
WORD, /BYTE (Input)
tOH
O0 to O7 (Output)
Data Out
tACC
tOH
Data Out
tWB
Data Out
tDF
O8 to O15 (Output)
Data Out
High impedance
Data Out
Remark /OE, OE and /CE : Active.
Data Sheet M13644EJ3V0DS00
9
µPD23C128000L
•
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
1
detail of lead end
48
F
G
R
Q
24
L
25
S
E
P
I
A
J
C
S
D
K
N
B
M M
S
NOTES
ITEM
MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
12.0±0.1
B
0.45 MAX.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
C
0.5 (T.P.)
D
0.22±0.05
E
0.1±0.05
F
1.2 MAX.
G
1.0±0.05
I
16.4±0.1
J
0.8±0.2
K
0.145±0.05
L
0.5
M
0.10
N
0.10
P
18.0±0.2
Q
+5°
3° −3°
R
S
0.25
0.60±0.15
S48GY-50-MJH1-1
10
Data Sheet M13644EJ3V0DS00
µPD23C128000L
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
24
G
25
F
K
N
S
D
S
I
J
M M
B
C
A
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM
A
MILLIMETERS
12.0±0.1
B
0.45 MAX.
C
0.5 (T.P.)
D
0.22±0.05
E
0.1±0.05
F
1.2 MAX.
G
1.0±0.05
I
16.4±0.1
J
0.8±0.2
K
0.145±0.05
L
0.5
M
0.10
N
0.10
P
18.0±0.2
Q
3° +5°
−3°
R
0.25
S
0.60±0.15
S48GY-50-MKH1-1
Data Sheet M13644EJ3V0DS00
11
µPD23C128000L
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD23C128000L.
Types of Surface Mount Device
µPD23C128000LGY-MJH : 48-pin plastic TSOP(I) (12 x 18) (Normal bent)
µPD23C128000LGY-MKH : 48-pin plastic TSOP(I) (12 x 18) (Reverse bent)
12
Data Sheet M13644EJ3V0DS00
µPD23C128000L
[ MEMO ]
Data Sheet M13644EJ3V0DS00
13
µPD23C128000L
[ MEMO ]
14
Data Sheet M13644EJ3V0DS00
µPD23C128000L
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M13644EJ3V0DS00
15
µPD23C128000L
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8