DATA SHEET MOS INTEGRATED CIRCUIT µ PD3747 7400 PIXELS CCD LINEAR IMAGE SENSOR The µ PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The µ PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on. FEATURES • Valid photocell : 7400 pixels • Photocell pitch : 4.7 µ m • Photocell size : 4.7 × 4.7 µ m • Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side) • Data rate : 44 MHz MAX. (22 MHz/1 output) • Output type : 2 outputs in phase • High sensitivity : 19.0 V/lx•s TYP. (Light source: Daylight color fluorescent lamp) • Low image lag : 1 % MAX. • Power supply : +12 V 2 • Drive clock level : CMOS output under 5 V operation • On-chip circuits : : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD3747D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14892EJ1V0DS00 (1st edition) Date Published June 2000 NS CP (K) Printed in Japan © 2000 2 BLOCK DIAGRAM VOUT2 (Even) GND GND φ CP φ 2L φ2 φ1 21 11 20 18 14 13 22 CCD analog shift register ··· D140 D135 S7400 Photocell S7399 S2 S1 ··· D134 Data Sheet S14892EJ1V0DS00 D33 Transfer gate 12 φ TG Transfer gate VOUT1 (Odd) 1 CCD analog shift register 2 4 5 9 10 VOD φR φ 2L φ1 φ2 µ PD3747 µ PD3747 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) • µ PD3747D Output signal 1 (Odd) VOUT1 1 22 VOUT2 Output signal 2 (Even) Output drain voltage VOD 2 21 GND Ground No connection NC 3 20 φ CP Reset feed-through level clamp clock Reset gate clock φR 4 19 NC No connection Last stage shift register clock 2 φ 2L 5 18 φ 2L Last stage shift register clock 2 No connection NC 6 17 NC No connection No connection NC 7 16 NC No connection No connection NC 8 15 NC No connection Shift register clock 1 φ1 9 14 φ2 Shift register clock 2 Shift register clock 2 φ2 10 13 φ1 Shift register clock 1 Ground GND 11 12 φ TG Transfer gate clock PHOTOCELL STRUCTURE DIAGRAM 3.2 µ m 4.7 µ m 1.5 µ m Channel stopper Aluminum shield Data Sheet S14892EJ1V0DS00 3 µ PD3747 ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +14 V Shift register clock voltage Vφ 1, Vφ 2, Vφ 2L −0.3 to +8 V Reset gate clock voltage Vφ R −0.3 to +8 V Reset feed-through level clamp clock voltage Vφ CP −0.3 to +8 V Transfer gate clock voltage Vφ TG −0.3 to +8 V Operating ambient temperature TA −25 to +55 °C Storage temperature Tstg −40 to +100 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Parameter 4 Symbol MIN. TYP. MAX. Unit 11.4 12.0 12.6 V Output drain voltage VOD Shift register clock high level Vφ 1H, Vφ 2H, Vφ 2LH 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L, Vφ 2LL −0.3 0 +0.5 V Reset gate clock high level Vφ RH 4.5 5.0 5.5 V Reset gate clock low level Vφ RL −0.3 0 +0.5 V Reset feed-through level clamp clock high level Vφ CPH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CPL −0.3 0 +0.5 V Transfer gate clock high level Vφ TGH 4.5 5.0 5.5 V Transfer gate clock low level Vφ TGL −0.3 0 +0.5 V Data rate 2fφ R 1 2 44 MHz Data Sheet S14892EJ1V0DS00 µ PD3747 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, fφ R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol MIN. TYP. MAX. Unit 1.5 2.0 − V Daylight color fluorescent lamp − 0.10 − lx•s PRNU VOUT = 500 mV − 5 10 % ADS Light shielding − 0.5 3.0 mV Dark signal non-uniformity DSNU Light shielding − 8.0 14.0 mV Power consumption PW − 350 600 mW Output impedance ZO Response RF Daylight color fluorescent lamp IL VOUT = 500 mV Saturation voltage Vsat Saturation exposure SE Photo response non-uniformity Average dark signal Image lag Offset level Note 1 Test Conditions VOS Note 2 − 0.2 0.3 kΩ 13.3 19.0 24.7 V/lx•s − 0.5 1.0 % 3.7 4.7 5.7 V td VOUT = 500 mV − 14 − ns Register imbalance RI VOUT = 500 mV 0 1.0 4.0 % Total transfer efficiency TTE VOUT = 1 V, data rate = 44 MHz 94 98 − % − 550 − nm Output fall delay time Response peak Dynamic range Reset feed-through noise Random noise Shot noise Note 1 DR1 Vsat/DSNU − 250 − times DR2 Vsat/σ bit − 1000 − times RFTN Light shielding −300 +300 +900 mV σ bit Light shielding, bit clamp mode − 2.0 − mV σ line Light shielding, line clamp mode − 8.0 − mV σ shot VOUT = 500 mV, bit clamp mode − 8.0 − mV Notes 1. Refer to TIMING CHART 2, 3. 2. When the fall time of φ 2L (t2’) is the TYP. value (refer to TIMING CHART 2, 3). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. Data Sheet S14892EJ1V0DS00 5 µ PD3747 INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 12 V) Parameter Symbol Shift register clock pin capacitance 1 Cφ 1 Shift register clock pin capacitance 2 Cφ 2 Last stage shift register clock pin capacitance 6 Cφ L Pin name φ1 φ2 φ 2L Pin No. MIN. TYP. MAX. Unit 9 − 250 300 pF 13 − 250 300 pF 10 − 250 300 pF 14 − 250 300 pF 5 − 10 20 pF 18 − 10 20 pF Reset gate clock pin capacitance Cφ R φR 4 − 10 20 pF Reset feed-through level clamp clock pin capacitance Cφ CP φ CP 20 − 10 20 pF Transfer gate clock pin capacitance Cφ TG φ TG 12 − 100 150 pF Data Sheet S14892EJ1V0DS00 TIMING CHART 1 φ TG φ1 φ2 φ 2L φ CP (Bit clamp mode) φ CP (Line clamp mode) 7533 7535 7537 7539 7541 7534 7536 7538 7540 7542 135 136 7531 133 134 7532 131 132 137 129 130 138 127 128 33 34 125 31 32 126 29 30 35 5 6 36 3 4 Note 1 Note 2 Data Sheet S14892EJ1V0DS00 φR VOUT1 VOUT2 Optical black (96 pixels) Valid photocell (7400 pixels) Note Set the φ R and φ CP to low level during this period. Invalid photocell (6 pixels) 7 µ PD3747 Invalid photocell (6 pixels) µ PD3747 TIMING CHART 2 (Bit clamp mode) φ1 φ2 φ 2L t1 t2 t1' t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 φR t6 90% 10% t10 t8 t7 t9 t11 90% φ CP 10% + td RFTN VOUT1, 2 RFTN − VOS 10% Symbol t1, t2 8 MIN. TYP. MAX. Unit 0 50 − ns t1’, t2’ 0 5 − ns t3 10 125 − ns t4, t5 0 5 − ns t6 0 125 − ns t7 5 125 − ns t8, t9 0 5 − ns t10 t3 125 − ns t11 0 250 − ns Data Sheet S14892EJ1V0DS00 µ PD3747 TIMING CHART 3 (Line clamp mode) φ1 φ2 φ 2L t1 t2 t1' t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 φR φ CP t12 90% 10% "L" + td RFTN VOUT1, 2 RFTN − VOS 10% Symbol t1, t2 MIN. TYP. MAX. Unit 0 50 − ns t1’, t2’ 0 5 − ns t3 10 125 − ns t4, t5 0 5 − ns t12 5 250 − ns Data Sheet S14892EJ1V0DS00 9 µ PD3747 TIMING CHART 4 (Bit clamp mode, Line clamp mode) t14 t15 t13 90% φ TG 10% t16 φ1 90% φ 2, φ 2L t4 t3 t5 t17 t6 90% φR 10% t8 t7 t9 t10 t11 90% φ CP 10% Note Note Set the φ R and φ CP to low level during this period. Symbol t3 MIN. TYP. MAX. Unit 10 125 − ns t4, t5 0 5 − ns t6 0 125 − ns t7 5 125 − ns t8, t9 0 5 − ns t10 t3 125 − ns t11 0 250 − ns t13 1000 1500 − ns t14, t15 0 50 − ns t16, t17 200 300 − ns φ 1, φ 2 cross points φ 1, φ 2L cross points φ1 φ1 2 V or more φ2 2 V or more 2 V or more φ 2L Remark Adjust cross points of (φ 1, φ 2) and (φ 1, φ 2L) with input resistance of each pin. 10 Data Sheet S14892EJ1V0DS00 0.5 V or more µ PD3747 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x x × 100 ∆x: maximum of xj − x 7400 Σx x= j j=1 7400 xj: Output voltage of valid pixel number j VOUT Register dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 7400 Σd j ADS (mV) = j=1 7400 dj: Dark signal of valid pixel number j Data Sheet S14892EJ1V0DS00 11 µ PD3747 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of dj − ADS j = 1 to 7400 dj: Dark signal of valid pixel number j VOUT ADS Register dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j=1 RI (%) = n 1 n ∑ Vj × 100 j=1 n : Number of valid pixels Vj : Output voltage of each pixel 12 Data Sheet S14892EJ1V0DS00 µ PD3747 10. Random noise : σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). 100 Σ (V – V) i σ (mV) = i=1 100 2 , V= 1 100 ΣV i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 11. Shot noise : σ shot Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. This includes the random noise. The formula is the same with that of random noise. Data Sheet S14892EJ1V0DS00 13 µ PD3747 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 2 8 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.2 0.25 0.1 0.1 0 10 20 30 40 1 50 5 10 Storage Time (ms) Operating Ambient Temperature TA (°C) SPECTRAL RESPONSE CHARACTERISTIC (TA = +25°C) 100 Response Ratio (%) 80 60 40 20 0 400 600 800 Wavelength (nm) 14 Data Sheet S14892EJ1V0DS00 1000 1200 µ PD3747 APPLICATION CIRCUIT EXAMPLE +5 V +12 V +5 V + + µ PD3747 10 µ F/16 V 0.1 µ F B1 + 0.1 µ F 47 µ F/25 V 47 Ω φR 47 Ω φ 2L 1 2 VOD GND NC φ CP 4 φR NC 5 φ 2L φ 2L NC NC NC NC NC NC 3 6 7 8 φ1 φ2 VOUT2 VOUT1 22 0.1 µ F 10 µ F/16 V B2 21 47 Ω 20 19 47 Ω 18 16 15 9 φ1 φ2 14 2Ω 2Ω 10 φ2 φ1 13 2Ω φ TG GND φ 2L 17 2Ω 11 φ CP φ2 φ1 12 10 Ω Remarks 1. φ TG It is recommended that pins 5 and 18 (φ 2L) are separately driven a driver other than that of pins 10, 14 (φ 2). 2. The inverters shown in the above application circuit example are the 74AC04. B1, B2 EQUIVALENT CIRCUIT +12 V 47 µ F/25V 4.7 kΩ 110 Ω CCD VOUT 47 Ω + 2SC945 2SA1005 1 kΩ Data Sheet S14892EJ1V0DS00 15 µ PD3747 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400)) (Unit : mm) The 1st valid pixel 1 9.65 ± 0.3 3.2 ± 0.3 1.60±0.25 42.2 ± 0.25 48.6 ± 0.5 10.16 3 (1.95) 2 2.38 ±0.3 1.02 ± 0.15 2.54 (5.37) 4.68±0.5 0.46 ± 0.06 25.4 0~10° .05 0.25±0 4.33±0.5 Name Dimensions Refractive index Glass cap 47.5×9.25×0.7 1.5 1 1st valid pixel Center of pin 1 2 Photosensitive surface of CCD chip 3 Photosensitive surface of CCD chip Bottom of package Top of glass cap 22D-1CCD-PKG10 16 Data Sheet S14892EJ1V0DS00 µ PD3747 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (C10535E). Type of Through-hole Device µ PD3747D : CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin) Data Sheet S14892EJ1V0DS00 17 µ PD3747 [MEMO] 18 Data Sheet S14892EJ1V0DS00 µ PD3747 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14892EJ1V0DS00 19 µ PD3747 • The information in this document is current as of May, 2000. The information is subject to change without notice. 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