NEC UPD3788

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD3788
7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3788 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The µPD3788 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Moreover, the spectral response characteristics of the µPD3788 is modified from the previous device µPD3728 to be
suitable for Xe-lamp. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell
: 7300 pixels × 3
• Photocell pitch
: 10 µm
• Photocell size
: 10 × 10 µm2
• Line spacing
: 40 µm (4 lines) Red line-Green line, Green line-Blue line
• Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution
: 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 40 MHz MAX. (20 MHz/1 output)
• Output type
: 2 outputs in phase/color
• Power supply
: +12 V
• On-chip circuits
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µPD3788D
CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14664EJ1V0DS00(1st edition)
Date published June 2000 N CP(K)
Printed in Japan
©
2000
µPD3788
COMPARISON CHART
Item
µPD3728
ABSOLUTE MAXIMUM
Shift register clock voltage (V)
–0.3 to +8
–0.3 to +15
RATINGS
Reset gate clock voltage (V)
–0.3 to +8
–0.3 to +15
Reset feed-through level clamp clock voltage (V)
–0.3 to +8
–0.3 to +15
Transfer gate clock voltage (V)
–0.3 to +8
–0.3 to +15
ELECTRICAL
Saturation exposure (Ix·s)
CHARACTERISTICS
Red
TYP.
0.36
0.35
Green
TYP.
0.37
0.39
Blue
TYP.
0.80
0.31
Red
MIN.
3.85
3.9
TYP.
5.5
5.6
MAX.
7.15
7.3
MIN.
3.78
3.6
TYP.
5.4
5.1
MAX.
7.02
6.6
MIN.
1.75
4.5
TYP.
2.5
6.4
MAX.
3.25
8.3
Red
TYP.
645
630
Green
TYP.
540
540
Blue
TYP.
445
460
tcp = 20 ns
t7 = 150 ns
Response (V/Ix·s)
Green
Blue
Response peak (nm)
Random noise test conditions
TIMING CHART
t3 (ns)
MIN.
17
20
t7 (ns)
MIN.
17
20
t10 (ns)
MIN.
–20
–10
tCP (ns)
MIN.
5
–
TYP.
150
–
modified
–
STANDARD
TOTAL SPECTRAL
CHARACTERISTIC
RESPONSE CHARACTERISTICS
CURVES
2
µPD3788
Data Sheet S14664EJ1V0DS00
µPD3788
BLOCK DIAGRAM
23
24
VOUT5
(Red, odd)
5
GND
6
.....
D134
4
Photocell
21
φ TG2
(Green)
(Green)
15
φ TG3
(Red)
CCD analog shift register
Transfer gate
.....
D128
GND
φ TG1
(Blue)
D134
.....
D128
D27
3
.....
22
Transfer gate
CCD analog shift register
D27
VOUT6
(Red, even)
.....
CCD analog shift register
Transfer gate
VOUT4
1
(Green, even)
2
(Blue)
Transfer gate
CCD analog shift register
VOUT3
36
(Green, odd)
GND
Photocell
D134
.....
D129
CCD analog shift register
Transfer gate
D129
35
16
D129
GND
28
S7299
S7300
34
29
S7299
S7300
VOUT1
(Blue, odd)
30
Photocell
(Red)
S7299
S7300
33
φ2
S1
S2
GND
φ1
D128
32
GND
S1
S2
VOUT2
(Blue, even)
φ 20
S1
S2
31
φ 1L
D27
GND
φ CLB
Transfer gate
CCD analog shift register
7
8
9
13
14
VOD
φ RB
φ10
φ1
φ2
Data Sheet S14664EJ1V0DS00
3
µPD3788
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
• µPD3788D
Output signal 4 (Green, even) VOUT4 1
Ground
1
Output signal 6 (Red, even) VOUT6 3
1
GND 2
1
Ground
GND 4
Output signal 5 (Red, odd) VOUT5 5
36 VOUT3
Output signal 3 (Green, odd)
35 GND
Ground
34 VOUT1
Output signal 1 (Blue, odd)
33 GND
Ground
32 VOUT2
Output signal 2 (Blue, even)
Ground
Output drain voltage
VOD 7
30 φ CLB
Reset feed-through level
clamp clock
Reset gate clock
φ RB 8
29 φ 1L
Last stage shift register clock 1
Shift register clock 10
φ 10 9
28 φ 20
Shift register clock 20
No connection
NC 10
27 NC
No connection
No connection
NC 11
26 NC
No connection
No connection
NC 12
25 NC
No connection
Shift register clock 1
φ 1 13
24 φ 2
Shift register clock 2
Shift register clock 2
φ 2 14
23 φ 1
Shift register clock 1
22 φ TG1
Transfer gate clock 1 (for Blue)
21 φ TG2
Transfer gate clock 2 (for Green)
Blue
31 GND
Red
GND 6
Green
Ground
7300
7300
7300
Transfer gate clock 3 (for Red) φ TG3 15
Ground
GND 16
No connection
NC 17
20 NC
No connection
No connection
NC 18
19 NC
No connection
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
10 µm
10 µ m
7 µm
4 lines
(40 µm)
Channel stopper
10 µm
Green photocell array
4 lines
(40 µm)
10 µm
Aluminum
shield
4
Blue photocell array
3 µm
Data Sheet S14664EJ1V0DS00
Red photocell array
µPD3788
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
–0.3 to +15
V
Shift register clock voltage
Vφ1, Vφ1L, Vφ10, Vφ2, Vφ20
–0.3 to +8
V
Reset gate clock voltage
VφRB
–0.3 to +8
V
Reset feed-through level clamp clock voltage
VφCLB
–0.3 to +8
V
Transfer gate clock voltage
VφTG1 to VφTG3
–0.3 to +8
V
Operating ambient temperature
TA
–25 to +60
°C
Storage temperature
Tstg
–40 to +100
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
VOD
11.4
12.0
12.6
V
Shift register clock high level
Vφ1H, Vφ1LH, Vφ10H, Vφ2H, Vφ20H
4.5
5.0
5.5
V
Shift register clock low level
Vφ1L, Vφ1LL, Vφ10L, Vφ2L, Vφ20L
–0.3
0
+0.5
V
Reset gate clock high level
VφRBH
4.5
5.0
5.5
V
Reset gate clock low level
VφRBL
–0.3
0
+0.5
V
Reset feed-through level clamp clock high level
VφCLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
VφCLBL
–0.3
0
+0.5
V
Transfer gate clock high levelNote
VφTG1H to VφTG3H
4.5
Vφ1H
(Vφ10H)
Vφ1H
(Vφ10H)
V
Transfer gate clock low level
VφTG1L to VφTG3L
–0.3
0
+0.5
V
Data rate
2fφRB
–
2
40
MHz
Note
When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H (Vφ10H)),
Image lag can increase.
Remark Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal
waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
Data Sheet S14664EJ1V0DS00
5
µPD3788
ELECTRICAL CHARACTERISTICS
TA = +25 °C, VOD = 12 V, fφRB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) +HA-50 (heat absorbing filter, t = 3mm)
Parameter
Symbol
Saturation voltage
Test Conditions
Vsat
Saturation exposure
MIN.
TYP.
MAX.
Unit
1.5
2.0
–
V
Red
SER
0.36
lx•s
Green
SEG
0.37
lx•s
Blue
SEB
0.80
lx•s
Photo response non-uniformity
6
18
%
1.0
5.0
mV
0.5
5.0
mV
2.0
5.0
mV
DSNU2
1.0
5.0
mV
Power consumption
PW
600
800
mW
Output impedance
ZO
0.3
0.5
kΩ
Average dark signal
Note 1
PRNU
VOUT = 1 V
ADS1
Light shielding
ADS2
Dark signal non-uniformity
Response
Image lag
Note 1
DSNU1
Light shielding
Red
RR
3.85
5.5
7.15
V/lx•s
Green
RG
3.78
5.4
7.02
V/lx•s
Blue
RB
1.75
2.5
3.25
V/lx•s
2.0
5.0
%
1.0
5.0
%
5.0
6.0
V
Note 1
IL1
VOUT = 1 V
IL2
Offset level
Note 2
Output fall delay time
VOS
Note 3
4.0
td
VOUT = 1 V
20
Register imbalance
RI
VOUT = 1 V
0
Total transfer efficiency
TTE
VOUT = 1 V,
95
ns
4.0
%
98
%
Red
645
nm
Green
540
nm
Blue
445
nm
data rate = 40 MHz
Response peak
Dynamic range
Note 1
Reset feed-through noise
Random noise
Note 1
Note 2
DR11
Vsat/DSNU1
1000
times
DR12
Vsat/DSNU2
2000
times
DR21
Vsat/σbit1
2000
times
DR22
Vsat/σbit2
4000
times
RFTN
Light shielding
σbit1
–500
+200
+500
mV
Light shielding, bit clamp
–
1.0
–
mV
σbit2
mode (tcp = 20 ns)
–
0.5
–
mV
σline1
Light shielding, line
–
4.0
–
mV
σline2
clamp mode (t19 = 3 µs)
–
2.0
–
mV
Notes 1. ADS1, DSNU1, IL1, DR11, DR21, σbit1 and σline1 show the specification of VOUT1 and VOUT2.
ADS2, DSNU2, IL2, DR12, DR22, σbit2 and σline2 show the specification of VOUT3 to VOUT6.
2. Refer to TIMING CHART 2, 5.
3. When the fall time of φ1L (t2’) is the TYP. value (refer to TIMING CHART 2, 5).
6
Data Sheet S14664EJ1V0DS00
µPD3788
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter
Symbol Pin name Pin No.
Shift register clock pin capacitance 1
C φ1
Shift register clock pin capacitance 2
C φ2
TYP.
MAX.
Unit
13
350
500
pF
23
350
500
pF
φ10
9
350
500
pF
φ2
14
350
500
pF
24
350
500
pF
φ20
28
350
500
pF
φ1
MIN.
Last stage shift register clock pin capacitance
C φL
φ1L
29
10
pF
Reset gate clock pin capacitance
CφRB
φRB
8
10
pF
Reset feed-through level clamp clock pin capacitance
CφCLB
φCLB
30
10
pF
Transfer gate clock pin capacitance
CφTG
φTG1
22
100
pF
φTG2
21
100
pF
φTG3
15
100
pF
Remark Pins 13, 23 (φ1) and pin 9 (φ10) are connected each other inside of the device.
Pins 14, 24 (φ2) and pin 28 (φ20) are connected each other inside of the device.
Data Sheet S14664EJ1V0DS00
7
8
TIMING CHART 1 (Bit clamp mode, for each color)
φ TG1 to
φ TG3
φ 1 (φ 10)
φ 2 (φ 20)
φ 1L
φ CLB
119
121
123
125
127
129
131
120
122
124
126
128
130
132
7435
7437
27
29
28
30
7436
7438
23
25
24
26
7425
7427
7429
7431
7433
21
22
7426
7428
7430
7432
7434
15
17
19
16
18
20
Note
1
3
5
7
9
11
13
Note
2
4
6
8
10
12
14
Data Sheet S14664EJ1V0DS00
φ RB
VOUT1, 3, 5
VOUT2, 4, 6
Optical black
(96 pixels)
Valid photocell
(7300 pixels)
Note
Input the φRB and φCLB pulses continuously during this period, too.
Invalid photocell
(6 pixels)
µPD3788
Invalid photocell
(6 pixels)
µPD3788
TIMING CHART 2 (Bit clamp mode, for each color)
t1
t2
90 %
φ 1 (φ 10)
10 %
90 %
φ 2 (φ 20)
10 %
90 %
φ 1L
10 %
t5
φ RB
t4
t6
t1'
90 %
t2'
t3
t10 t8
10 %
90 %
φ CLB
tcp
t9
t11
t7
10 %
td
VOUT1 to
VOUT6
RFTN
VOS
10 %
Symbol
MIN.
TYP.
t1, t2
0
50
ns
t1’, t2’
0
5
ns
t3
17
50
ns
t4
5
200
t5, t6
0
20
ns
t7
17
150
ns
ns
t8, t9
MAX.
–
Unit
ns
0
20
t10
–20Note 1
+50
t11
–5Note 2
+50
ns
tcp
5
150
ns
Data Sheet S14664EJ1V0DS00
–
ns
9
µPD3788
Notes 1. MIN. of t10 shows that the φRB and φCLB overlap each other.
90 %
φ RB
t10
φ CLB
90 %
2. MIN. of t11 shows that the φ1L and φCLB overlap each other.
φ 1L
φ CLB
10
90 %
t11
90 %
Data Sheet S14664EJ1V0DS00
µPD3788
TIMING CHART 3 (Bit clamp mode, for each color)
t13
t12
t14
90 %
10 %
φ TG1 to φ TG3
t15
φ 1 (φ 10)
t16
90 %
φ 2 (φ 20)
φ 1L
90 %
φ RB
t11
90 %
φ CLB
Note 1
Symbol
MIN.
TYP.
MAX.
Unit
t11
–5Note 2
+50
ns
t12
3000
10000
ns
t13, t14
0
50
ns
t15, t16
900
1000
ns
Notes 1. Input the φRB and φCLB pulses continuously during this period, too.
2. MIN. of t11 shows that the φ1L and φCLB overlap each other.
90 %
φ 1L
t11
φ CLB
φ1 (φ10), φ2 (φ20) cross points
φ 1 (φ 10)
Remark
φ1L, φ2 (φ20) cross points
φ 2 (φ 20)
2 V or more
φ 2 (φ 20)
90 %
2 V or more
2 V or more
0.5 V or more
φ 1L
Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin.
Data Sheet S14664EJ1V0DS00
11
12
TIMING CHART 4 (Line clamp mode, for each color)
φ TG1 to
φ TG3
φ 1 (φ 10)
φ 2 (φ 20)
φ 1L
φ CLB
21
23
25
27
29
119
121
123
125
127
129
131
22
24
26
28
30
120
122
124
126
128
130
132
7425
7427
7429
7431
7433
7435
7437
15
17
19
16
18
20
Note
1
3
5
7
9
11
13
Note
2
4
6
8
10
12
14
VOUT1, 3, 5
7426
7428
7430
7432
7434
7436
7438
Data Sheet S14664EJ1V0DS00
φ RB
VOUT2, 4, 6
Optical black
(96 pixels)
Note
Set the φRB to high level during this period.
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
µPD3788
Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB.
Valid photocell
(7300 pixels)
µPD3788
TIMING CHART 5 (Line clamp mode, for each color)
t1
t2
90 %
φ 1(φ 10)
10 %
90 %
φ 2(φ 20)
10 %
90 %
φ 1L
10 %
t5
t4
t6
t1'
90 %
t2'
t3
φ RB
10 %
“H”
φ CLB
td
VOUT1 to
VOUT6
RFTN
VOS
10 %
Symbol
MIN.
TYP.
t1, t2
0
50
ns
t1’, t2’
0
5
ns
t3
17
50
ns
t4
5
200
t5, t6
0
20
Data Sheet S14664EJ1V0DS00
MAX.
–
Unit
ns
ns
13
µPD3788
TIMING CHART 6 (Line clamp mode, for each color)
t13
t12
t14
90 %
10 %
φ TG1 to φ TG3
t15
t16
90 %
φ 1 (φ 10)
φ 2 (φ 20)
90 %
φ 1L
Note
φ RB
t17
90 %
10 %
t20
φ CLB
Symbol
t21
t19
MIN.
TYP.
3000
10000
ns
t13, t14
0
50
ns
t15, t16
900
1000
ns
t17, t18
100
1000
ns
t19
200
t12
ns
0
20
ns
t12
t20, t21
Note
t18
MAX.
Unit
Set the φRB to high level during this period.
Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB.
φ1 (φ10), φ2 (φ20) cross points
φ 1 (φ 10)
φ 2 (φ 20)
2 V or more
φ 2 (φ 20)
φ1L, φ2 (φ20) cross points
2 V or more
2 V or more
0.5 V or more
φ 1L
Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin.
14
Data Sheet S14664EJ1V0DS00
µPD3788
DEFINITIONS OF CHARACTERISTIC ITEMS
1.
Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2.
Saturation exposure: SE
Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs.
3.
Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
PRNU (%) =
∆x
× 100
x
∆x : maximum of xj − x 
7300
Σx
x=
j
j=1
7300
xj : Output voltage of valid pixel number j
VOUT
Register Dark
DC level
4.
x
∆x
Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7300
Σd
ADS (mV) =
j
j=1
7300
dj : Dark signal of valid pixel number j
Data Sheet S14664EJ1V0DS00
15
µPD3788
5.
Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj − ADS j = 1 to 7300
dj : Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6.
Output impedance: ZO
Impedance of the output pins viewed from outside.
7.
Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).
8.
Image lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
φTG
ON
Light
OFF
VOUT
V1
VOUT
V1
IL (%) =
16
VOUT
×100
Data Sheet S14664EJ1V0DS00
µPD3788
9.
Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
n
∑ (V2j – 1 – V2j)
j= 1
RI (%) =
× 100
n
1
n
∑ Vj
j= 1
n : Number of valid pixels
Vj : Output voltage of each pixel
10. Random noise: σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines)
data sampling at dark (light shielding).
100
σ (mV) =
Σ (V – V)
i
2
i=1
100
, V=
1
100
ΣV
i
100 i=1
Vi: A valid pixel output signal among all of the valid pixels for each color
VOUT
V1
line 1
V2
line 2
…
…
V100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
Data Sheet S14664EJ1V0DS00
17
µPD3788
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (TA = +25 °C)
2
Relative Output Voltage
Relative Output Voltage
4
2
1
0.5
1
0.2
0.25
0.1
0
10
20
30
40
0.1
50
Operating Ambient Temperature TA(°C)
1
5
10
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (TA = +25 °C)
100
B
R
G
Response Ratio (%)
80
60
B
40
20
0
400
18
G
500
600
Wavelength (nm)
Data Sheet S14664EJ1V0DS00
700
800
µPD3788
APPLICATION CIRCUIT EXAMPLE
+5 V
+12 V
10 Ω
+
B4
10 µ F/16 V 0.1 µ F
1
2
B6
3
4
B5
5
6
7
φ RB
VOUT4
VOUT3
GND
GND
VOUT6
VOUT1
GND
GND
VOUT5
VOUT2
GND
VOD
GND
36
34
32
B1
+
0.1 µ F 10 µ F/16 V
B2
31
φ CLB
30
47 Ω
47 Ω
2Ω
2Ω
φ RB
φ 1L
29
9
φ 10
φ 20
28
NC
NC
NC
NC
NC
NC
12
26
25
13
φ2
24
2Ω
2Ω
φ1
14
φ1
23
2Ω
2Ω
φ2
15
φ TG1
22
2Ω
φ TG2
21
2Ω
17
18
φ TG3
GND
NC
NC
NC
NC
φ CLB
27
2Ω
16
+5 V
0.1 µ F 47 µ F/25 V
33
8
11
B3
35
47 Ω
10
φ2
+
µ PD3788
φ1
φ TG
20
19
Remarks 1. Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output
signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
2. The inverters shown in the above application circuit example are the 74AC04.
Data Sheet S14664EJ1V0DS00
19
µPD3788
B1 to B6 EQUIVALENT CIRCUIT
+12 V
47 µ F/25 V
+
0.1 µ F
4.7 kΩ
110 Ω
CCD
VOUT
47 Ω
2SC945
2SA1005
1 kΩ
20
Data Sheet S14664EJ1V0DS00
µPD3788
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24mm (600))
(Unit : mm)
94.00±0.50
1
14.99±0.3
9.5±0.9
(35.0)
2
The 1st valid pixel
15.24
(4.33)
(2.33)
1.27±0.05
0.46±0.05
3
2.54
20.32
2.0±0.3
88.9±0.6
4
0.25±0.05
3.50±0.5
0.97±0.3
3.30±0.35
Name
Dimensions
Refractive index
Glass cap
93.0 × 13.6 × 1.0
1.5
1 The 1st valid pixel
2 The 1st valid pixel
3 The surface of the chip
4 The bottom of the package
The center of the pin1
The center of the package (Reference)
The top of the glass cap (Reference)
The surface of the chip
36D-1CCD-PKG1-2
Data Sheet S14664EJ1V0DS00
21
µPD3788
NOTES ON THE USE OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to
come off internally. Particular care should be taken when mounting the package on the circuit board.
When mounting the package, use a circuit board which will not subject the package to bending stress, or use a
socket.
For this product, the reference value for the three-point bending strengthNote is 300 [N]. Avoid imposing a load,
however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body
(ceramic).
Note
Three-point bending strength test
Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min.
22
Load
Load
70 mm
70 mm
Data Sheet S14664EJ1V0DS00
µPD3788
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14664EJ1V0DS00
23
µPD3788
• The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4