DATA SHEET MOS INTEGRATED CIRCUIT µPD78CP18(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD78CP18(A) is a version of the µPD78C18(A) in which the internal mask ROM is replaced by one-time PROM. The one-time PROM version can be programmed once only by users, and is ideally suited for small-scall of many differnt products, and rapid development and time-to-market of a new product. The detailed functions are descrived in the following user's manual. Read this manual before starting design work. 87AD series µPD78C18 user's manual: IEU-1314 FEATURES • High reliability compared to the µPD78CP18 • Compatible with the µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A) • Internal PROM: 32768 W × 8 • Internal PROM capacity can be changed by software to conform to the µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A). • PROM programming characteristics: µPD27C256A compatible • Power supply voltage range: 5 V ± 10 % • Supports QTOP microcomputer Remark ★ QTOP microcomputer is the generic name of NEC's single-chip microcomputers for which NEC provides total service including writing, marking, screening, and inspection. ORDERING INFORMATION Part Number µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36 Package Internal ROM 64-pin plastic QFP (14 × 20 mm) One-time PROM 64-pin plastic QUIP One-time PROM QUALITY GRADE Part Number Quality Grade µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36 Special Special Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. The mark Document No. IC-3233A (O. D. No. IC-8702A) Date Published March 1995 P Printed in Japan ★ shows major revised points. © 1994 1993 µPD78CP18(A) PIN CONFIGURATION (TOP VIEW) 1 64 V DD A1/PA1 2 63 STOP/V PP A2/PA2 3 62 PD7/O7 A3/PA3 4 61 PD6/O6 A4/PA4 5 60 PD5/O5 A5/PA5 6 59 PD4/O4 A6/PA6 7 58 PD3/O3 A7/PA7 8 57 PD2/O2 PB0 9 56 PD1/O1 PB1 10 55 PD0/O0 PB2 11 54 PF7 PB3 12 53 PF6/A14 PB4 13 52 PF5/A13 51 PF4/A12 50 PF3/A11 49 PF2/A10 48 PF1 47 PF0/A8 PB5 14 CE/PB6 15 OE/PB7 16 PC0/T X D 17 PC1/R X D 18 µPD78CP18GQ(A)-36 2 A0/PA0 PC2/SCK 19 46 ALE PC3/INT2 20 45 WR PC4/TO 21 44 RD AV DD PC5/CI 22 43 PC6/CO0 23 42 V AREF PC7/CO1 24 41 AN7 A9/NMI 25 40 AN6 INT1 26 39 AN5 MODE1 27 38 AN4 RESET 28 37 AN3 MODE0 29 36 AN2 X2 30 35 AN1 X1 31 34 AN0 V SS 32 33 AV SS PD0/O0 PF7 PF6/A14 PF5/A13 PF4/A12 PF3/A11 PF2/A10 PF1 PF0/A8 ALE WR RD AV DD V AREF AN7 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 O4/PD4 AN5 PD1/O1 51 52 50 O3/PD3 AN6 PD2/O2 µPD78CP18(A) 34 33 32 AN4 53 31 AN3 O5/PD5 54 30 AN2 O6/PD6 55 29 AN1 O7/PD7 56 28 AN0 V PP/ STOP 57 27 AV SS V DD 58 26 V SS A0/PA0 59 25 X1 A1/PA1 60 24 X2 A2/PA2 61 23 MODE0 A3/PA3 62 22 RESET A4/PA4 63 21 MODE1 A5/PA5 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 A6/PA6 A7/PA7 PB0 PB1 PB2 PB3 PB4 PB5 CE/PB6 OE/PB7 PC0/T X D PC1/R X D PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 A9/NM1 µPD78CP18GF(A)-3BE INT1 3 8 MAIN G.R 16 10 PROM (32-KBYTE) EA' 8 INT1 V' B' D' H' INT. CONTROL 4 A' C' E' L' 8 TIMER PC4/TO 8/16 8 8 8 PC5/CI PC6/CO0 PC7/CO1 TIMER/EVENT COUNTER 8 8 LATCH 8 PC7 to PC0 8 INTERNAL DATA BUS 16 PD7/O7/AD7 to PD0/O0/AD0 Note DATA MEMORY (1-KBYTE) ALT G.R BUFFER PC3/INT2/TI 8 PF6/A14/AB14 to PF2/A10/AB10 PF1/AB9 PF0/A8/AB8 15 A C E L A9/NMI PORT F V B D H PORT D SERIAL I/O 8 5 16 8 8 6 LATCH PORT B PC0/TXD PC1/RXD PC2/SCK 8 PORT C LATCH INC/DEC PC SP EA BLOCK DIAGRAM 4 OSC X2 PF7/AB15 8 16 X1 OE/PB7 CE/PB6 6 PB5 to PB0 8 PA7/A7 to PA0/A0 8 PSW VAREF AVDD AVSS 8 16 A/D CONVERTER 16 8 8 INST. DECODER ALU (8/16) PORT A INST. REG AN7 to AN0 16 READ/WRITE CONTROL WR ALE MODE1 MODE0 RESET Note Can be used only when RAE bit of MM register is 1. External memory is needed in case of 0. STANDBY CONTROL VPP/STOP VDD VSS µPD78CP18(A) RD SYSTEM CONTROL µPD78CP18(A) DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78CP18 Product Name µPD78CP18(A) µPD78CP18 Special Standard Item Quality grade Electrical specifications Input leakage current AN7 to AN0: ±1 µA (MAX.) Input leakage current AN7 to AN0; ±10 µA (MAX.) Package • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QUIP • • • • 64-pin plastic shrink DIP (750 mil) 64-pin plastic QUIP 64-pin plastic QFP (14 × 20 mm) 64-pin ceramic shrink DIP with window (750 mil) • 64-pin ceramic WQFN 5 µPD78CP18(A) CONTENTS 1. LIST OF PORT FUNCTIONS .......................................................................................................................7 1.1 1.2 PORT FUNCTIONS ...............................................................................................................................................7 NON-PORT FUNCTIONS (IN NORMAL OPERATION) ..................................................................................... 8 1.3 1.4 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ) .....................................................10 HANDLING OF UNUSED PINS .........................................................................................................................10 2. MEMORY CONFIGURATION ....................................................................................................................11 3. MEMORY EXTENSION .............................................................................................................................16 3.1 3.2 4. MODE PINS ........................................................................................................................................................16 MEMORY MAPPING REGISTER (MM) ............................................................................................................17 PROM PROGRAMMING ...........................................................................................................................20 4.1 PROM PROGRAMMING OPERATING MODES ...............................................................................................21 4.2 4.3 PROM WRITING PROCEDURE .........................................................................................................................22 PROM READING PROCEDURE .........................................................................................................................23 5. SCREENING OF ONE-TIME PROM VERSIONS ......................................................................................24 6. ELECTRICAL SPECIFICATIONS ................................................................................................................25 7. CHARACTERISTIC CURVES (REFERENCE VALUE) ..............................................................................39 8. PACKAGE DRAWINGS .............................................................................................................................42 9. RECOMMENDED SOLDERING CONDITIONS ........................................................................................44 10. DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78C18(A) .....................................................45 APPENDIX. 6 DEVELOPMENT TOOLS ..........................................................................................................46 µPD78CP18(A) 1. LIST OF PORT FUNCTIONS 1.1 PORT FUNCTIONS Pin Name PA7 to PA0 (Port A) I/O Input/Output Function 8-bit input-output port, which can specify input/output bit-wise. PB7 to PB0 (Port B) PC7 to PC0 (Port C) PD7 to PD0 (Port D) 8-bit input-output port, which can specify input/output in byte units. PF7 to PF0 (Port F) 8-bit input-output port, which can specify input/output bit-wise. Remark These port pins have alternate function pins as shown in 1.2 “NON-PORT FUNCTIONS (IN NORMAL OPERATION)” and 1.3 “NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)”. 7 µPD78CP18(A) 1.2 NON-PORT FUNCTIONS (IN NORMAL OPERATION) Pin Name I/O Alternate Function Pin Function TXD (Transmit Data) Output PC0 Serial data output pin RXD (Receive Data) Input PC1 Serial data input pin SCK (Serial Clock) Input/output PC2 Serial clock input/output pin. Output when internal clock is used, input when external clock is used. PC3 Edge trigger (falling edge) maskable interrupt input pin INT2 Input (Interrupt Request) TI (Timer Input) Input Timer external clock input pin Zero-cross Input AC input zero-cross detection pin TO (Timer Output) Output PC4 During timer count time, square wave with one internal clock cycle as one half cycle is output. CI (Counter Input) Input PC5 Timer/event counter external pulse input pin CO0 and CO1 (Counter Output 0, 1) Output PC6 and PC7 Square wave output programmable by timer/event counter. AD7 to AD0 (Address/Data Bus 7 to 0) Input/output PD7 to PD0 Multiplexed address/data bus when external memory is used AB15 to AB8 (Address Bus 15 to 8) Output PF7 to PF0 Address bus when external memory is used WR (Write Strobe) Output Strobe signal which is output for write operation of external memory. It becomes high in any cycle other than the data write machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes high-impedance. RD (Read Strobe) Output Strobe signal which is output for read operation of external memory. It becomes high in any cycle other than the data read machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Output ALE (Address Latch Enable) Strobe signal to latch externally the lower address information which is output to PD7 to PD0 pins to access external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes highimpedance. MODE0 MODE1 (Mode) Input Input/output Set MODE0 pin to “0” (low level), and MODE1 pin to “1” (high level)Note NMI (Non-Maskable Interrupt) Input Non-maskable interrupt input pin of the edge trigger (falling edge) Note Pull-up. Pull-up resister R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC is ns unit). 8 µPD78CP18(A) Pin Name I/O Alternate Function Pin Function INT1 (Interrupt Request) Input A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a zero-cross detection pin for AC input. AN7 to AN0 (Analog Input) Input 8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling edge) input. VAREF (Reference Voltage) Input A common pin serving both as a reference voltage input pin for A/D converter and as a control pin for A/D converter operation. AVDD (Analog VDD) Power supply pin for A/D converter. AVSS (Analog VSS) GND pin for A/D converter. X1, X2 (Crystal) Crystal connection pins for system clock oscillation. X1 should be input when a clock is supplied from outside. Inverted clock of X1 should be input in X2. RESET (Reset) Input Low-level active system reset input. STOP (Stop) Input Hardware STOP mode control signal input pin. When the low level is input to this pin, the oscillation stops. VDD Positive power supply pin. VSS GND pin. 9 µPD78CP18(A) 1.3 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ) Pin Name I/O Alternate Function Pin Function A7 to A0 Input PA7 to PA0 Address lower 8 bit input pins CE Input PB6 Chip enable signal input pin OE Input PB7 Output enable signal input pin O7 to O0 Input/output PD7 to PD0 Data input/output pins A14 to A10 Input PF6 to PF2 Address higher 7 bit input pins PF0 A8 A9 Input MODE0 MODE1 Input Set MODE0 pin to “1” (high level), and MODE1 pin to “0” (low level). RESET Input Set to “0” (low level). VPP NMI STOP High-voltage application pin "1" (high level) is input when EPROM is read. 1.4 HANDLING OF UNUSED PINS Pin PA7 PB7 PC7 PD7 PF7 to to to to to Recommended Connection PA0 PB0 PC0 PD0 PF0 RD WR ALE STOP INT1, NMI Leave open. Connect to VDD. Connect to VSS or VDD. AVDD Connect to VDD. VAREF AVSS Connect to VSS. AN7 to AN0 10 Connect to VSS or VDD via resistor. Connect to AVSS or AVDD. µPD78CP18(A) 2. MEMORY CONFIGURATION The µPD78CP18(A) memory can operate in the following 4 modes according to the mode specification. ● ● ● ● µPD78C11A mode (see Figure 2-1) µPD78C12A mode (see Figure 2-2) µPD78C14 mode (see Figure 2-3) µPD78C18 mode (see Figure 2-4) In addition, the internal PROM and internal RAM address ranges can be specified for efficient mapping of external memory (excluding PROM) (see 3.2 “MEMORY MAPPING REGISTER (MM)”). The vector area and call table area are common to all modes. Setting the hardware/software STOP mode or HALT mode enables internal RAM data to be retained at a low consumption current. 11 µPD78CP18(A) Figure 2-1. Memory Map (µPD78C11A Mode) 0000H RESET 0000H 0004H NMI Internal PROM 4096W × 8 0008H INTT0/INTT1 0FFFH 1000H 0010H INT1/INT2 External Memory 61184W × 8 Vector Area 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W × 8 0028H INTSR/INTST FFFFH 0060H SOFTI 0080H 0081H Call Table Area 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS 00BEH LOW ADRS 00BFH 00C0H HIGH ADRS USER'S AREA 0FFFH 12 t=0 t=1 t = 31 µPD78CP18(A) Figure 2-2. Memory Map (µPD78C12A Mode) 0000H RESET 0000H 0004H NMI Internal PROM 8192W × 8 0008H INTT0/INTT1 1FFFH 2000H 0010H INT1/INT2 External Memory 57088W × 8 Vector Area 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W × 8 0028H INTSR/INTST FFFFH 0060H SOFTI Call Table Area LOW ADRS 0080H 0081H HIGH ADRS 0082H 0083H HIGH ADRS 00BEH LOW ADRS 00BFH 00C0H HIGH ADRS LOW ADRS t=0 t=1 t = 31 USER'S AREA 1FFFH 13 µPD78CP18(A) Figure 2-3. Memory Map (µPD78C14 Mode) 0000H RESET 0000H 0004H NMI Internal PROM 16384W × 8 0008H INTT0/INTT1 3FFFH 4000H 0010H INT1/INT2 External Memory 48896W × 8 Vector Area 0018H INTE0/INTE1 0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W × 8 0028H INTSR/INTST FFFFH 0060H SOFTI Call Table Area LOW ADRS 0080H 0081H HIGH ADRS 0082H 0083H HIGH ADRS 00BEH LOW ADRS 00BFH 00C0H HIGH ADRS LOW ADRS USER'S AREA 3FFFH 14 t=0 t=1 t = 31 µPD78CP18(A) Figure 2-4. Memory Map (µPD78C18 Mode) 0000H RESET 0000H 0004H NMI Internal PROM 32768W × 8 0008H INTT0/INTT1 7FFFH 8000H 0010H INT1/INT2 External Memory 31744W × 8 Vector Area 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H Internal RAM 1024W × 8 0028H INTSR/INTST FFFFH 0060H SOFTI Call Table Area LOW ADRS 0080H 0081H HIGH ADRS 0082H 0083H HIGH ADRS 00BEH LOW ADRS 00BFH 00C0H HIGH ADRS LOW ADRS t=0 t=1 t = 31 USER'S AREA 7FFFH 15 µPD78CP18(A) 3. MEMORY EXTENSION The µ PD78CP18(A) allows external memory extension by means of the MEMORY MAPPING register (MM) or the MODE0 and MODE1 pins. Also, the internal PROM and internal RAM access areas can be specified by means of bits MM7, MM6 and MM5 of the MEMORY MAPPING register. 3.1 MODE PINS The µPD78CP18(A) can be switched between programming mode and normal operation mode according to the specification of the MODE0 and MODE1 pins. Table 3-1 shows the modes set by the MODE pins. Table 3-1. Modes Set By MODE Pins MODE1 MODE2 Operating Mode L L Setting prohibited L H Programming modeNote H L Normal operation mode H H Setting prohibited Note See 4. “PROM PROGRAMMING”. When MODE0 and MODE1 are driven high, a 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] pull-up resistor should be used (tCYC: ns units). 16 µPD78CP18(A) 3.2 MEMORY MAPPING REGISTER (MM) The MEMORY MAPPING register is an 8-bit register which performs the following controls: • Port/extension mode specification for PD7 to PD0 and PF7 to PF0 • Enabling/disabling of internal RAM accesses • Specification of internal PROM and RAM access areas The configuration of the MEMORY MAPPING register is shown in Figure 3-1. (1) Bits MM2 to MM0 These bits control the PD7 to PD0 port/extension mode specification, input/output specification, and the PF7 to PF0 address output specification. As shown in Figure 3-1, there is a choice of four capacities for the connectable external memory: • 256 bytes • 4 Kbytes • 16 Kbytes • 32 K/48 K/56 K/60 Kbytes (set by bits MM7 to MM5) Ports of PF7 to PF0 not used as address outputs can be used as general-purpose ports. When RESET signal is input or in the hardware STOP mode, these bits are reset to (0) and PD7 to PD0 are set to input port mode (high-impedance). (2) MM3 bit (RAE) This bit enables (RAE = 1) and disables (RAE = 0) internal RAM access. This bit should be set to “0” during standby operation and when externally connected RAM, not internal RAM, is used. In normal operation this bit retains its value when RESET signal is input. However, the RAE bit is undefined after a power-on reset, and must therefore be initialized by an instruction. (3) Bits MM7 to MM5 These bits specify the access area of the internal PROM. When STOP or RESET signal is input, these bits are reset, selecting the 32-Kbyte mode (µPD78C18 mode). These bits are only valid in the µPD78CG14, 78CP14, 78CP18, 78CP14(A), and 78CP18(A); if data is written to these bits in the µPD78C11A(A), 78C12A(A), 78C14(A), or 78C18(A), it will be ignored. Therefore, a program developed on the µPD78CP18(A) can be directly ported to mask ROM. 17 µPD78CP18(A) Figure 3-1. MEMORY MAPPING Register Format 7 MM7 6 5 MM6 MM5 4 3 2 1 RAE MM2 MM1 0 MM0 0 0 0 Port Single chip mode 0 0 1 0 1 0 Exten- 256 bytes sion mode 1 0 0 4 Kbytes 1 1 0 16 Kbytes 1 1 1 32 K/48 K/ 56K/60KNote bytes Note PD7 to PD0 = Input port PF7 to PF0 = Port mode PD7 to PD0 = Output port PF7 to PF0 = Port mode PD7 to PD0 = Extension mode PF7 to PF0 = Port mode PD7 to PD0 = Extension mode PF3 to PF0 = PF7 to PF4 = Port mode PD7 to PD0 = Extension mode PF5 to PF0 = PF7 & PF6 = Port mode PD7 to PD0 = Extension mode PF7 to PF0 = Depends on MM7 to MM5 bit-setting Internal RAM Access 0 Disable 1 Enable Internal PROM/RAM Access Areas Internal PROM Access Area Internal RAM Access Area 0 0000H to 7FFFH (32 Kbytes: µPD78C18 mode) FC00H to FFFFH (1 Kbyte) 0 1 0000H to 3FFFH (16 Kbytes: µPD78C14 mode) FF00H to FFFFH (256 bytes) 0 1 1 0000H to 1FFFH (8 Kbytes: µPD78C12A mode) FF00H to FFFFH (256 bytes) 1 0 1 0000H to 0FFFH (4 Kbytes: µPD78C11A mode) FF00H to FFFFH (256 bytes) MM7 MM6 MM5 0 0 0 Other than above 18 Setting Prohibited µPD78CP18(A) Figure 3-2. External Extension Modes Set by MEMORY MAPPING Register Port Mode 256-Byte Extension Mode 0 0 4-KByte Extension Mode 0 Internal PROM (4/8/16/32 KBytes) Internal PROM (4/8/16/32 KBytes) Internal PROM (4/8/16/32 KBytes) Not Used Not Used Not Used External Memory(4 KBytes) External Memory(256 Bytes) Not Used Not Used 64K Internal RAM Internal RAM Internal RAM 64K 64K 32-/48-/56-/60-KByte Extension Mode 16-KByte Extension Mode 0 0 Internal PROM (4/8/16/32 KBytes) Internal PROM (4/8/16/32 KBytes) External Memory (16 KBytes) External Memory (32/48/56/ 60 KBytes) Not Used Internal RAM 64K Caution Internal RAM 64K The internal PROM and internal RAM access areas are determined by MM7 to MM5. 19 µPD78CP18(A) 4. PROM PROGRAMMING The µPD78CP18(A) incorporates 32768 × 8-bit PROM as a program memory. The pins shown in Table 4-1 are used for write/verify operations on this PROM. µPD78CP18(A) program timing is compatible with the µPD27C256A. Please read the following in conjunction with documentation of the µPD27C256A. Table 4-1. Pins Used in PROM Programming Pin Name Function RESET Low-level input (at write/verify and read) MODE0 High-level input (at write/verify and read) MODE1 Low-level input (at write/verify and read) Note High-voltage input (at write/verify), high-level input (at read) Note Chip enable input VPP CE OE Note Output enable input A14 to A0 O7 to O0 Note Note VDD Note Address input Data input (at write), data output (at verify, read) Supply voltage input Note These pins correspond to the µPD27C256A. Caution 20 The µPD78CP18(A) one-time PROM version is not equipped with an erasure window, and therefore ultraviolet erasure cannot be performed on it. µPD78CP18(A) 4.1 PROM PROGRAMMING OPERATING MODES The PROM programming operating mode is set as shown in Table 4-2. Pins not used for programming should be handled as shown in Table 4-3. Table 4-2. PROM Programming Modes Operating Mode CENote OENote Program L H Program verify H L Program inhibit H H Read L L Output disable L H Standby H L/H Note VPPNote VDDNote RESET MODE0 MODE1 +12.5 V +6 V L H L +5 V +5 V These pins correspond to the µPD27C256A. Caution When +12.5 V is applied to VPP and +6 V is applied to VDD, setting both CE and OE to “L” is prohibited. Table 4-3. Recommended Connection of Unused Pins (in PROM Programming Mode) Pin Recommended Connection INT1 Connect to VSS. X1 AN0 to AN7 VAREF AVDD AVSS Pins other than the above Connect to VSS via individual resistor. X2 Leave open. 21 µPD78CP18(A) 4.2 PROM WRITING PROCEDURE The PROM writing procedure is as shown below, allowing high-speed writing. (1) Connect unused pins to VSS via a pull-down resistor, and supply +6 V to VDD and +12.5 V to VPP. (2) Provide the initial address. (3) Provide the write data. (4) Provide a 1-ms program pulse (active low) to the CE pin. (5) Verify mode. If written, go to (7); if not written, repeat (3) to (5). If the write operation has failed 25 times, go to (6). (6) Halt write operation due to defective device. (7) Provide write data and program pulse of X times x 3 ms (X; repeated times from (3) to (5)) (additional write). (8) Increment the address. (9) Repeat (3) to (8) until the final address. Figure 4-1. PROM Write/Verify Timing Repeated X Times Write Verify Additional Write A14/PF6-A10/PF2 A9/NMI Address (Higher 7 Bits) A8/PF0 A7/PA7-A0/PA0 O7/PD7-O0/PD0 VPP VPP VIH VDD + 1 VDD VDD VIH CE/PB6 VIL VIH OE/PB7 VIL 22 Address (Lower 8 Bits) Data Input Data Output Data Input µPD78CP18(A) 4.3 PROM READING PROCEDURE PROM contents can be read onto the external data bus (O7 to O0) using the following procedure. (1) Connect unused pins to VSS via a pull-down resistor. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of data to be read to pins A14 to A0. (4) Read mode (5) Output data to pins O7 to O0. Timing for steps (2) to (5) above is shown in Figure 4-2. Figure 4-2. PROM Read Timing A14/PF6-A10/PF2 A9/NMI Address Input A8/PF0 CE/PB6 OE/PB7 O7/PD7-O0/PD0 Data Output 23 µPD78CP18(A) 5. SCREENING OF ONE-TIME PROM VERSIONS Because of their construction, one-time PROM versions cannot be fully tested by NEC before shipment. After the necessary data has been written, it is recommended that screening be implemented in which PROM verification is performed after high-temperature storage under the following conditions. ★ Storage Temperature Storage Time 125 °C 24 hours NEC provides writing, marking, screening, and inspection services for single-chip microcomputers labeld QTOP microcomputers. For details, consult NEC. 24 µPD78CP18(A) 6. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) PARAMETER SYMBOL TEST CONDITIONS VDD RATINGS –0.5 to +7.0 AVDD AVSS to VDD + 0.5 UNIT V V Power supply voltage AVSS –0.5 to +0.5 V VPP –0.5 to +13.5 V –0.5 to VDD + 0.5 V –0.5 to +13.5 V –0.5 to VDD + 0.5 V All output pins 4.0 mA Total of all output pins 100 mA All output pins –2.0 mA Total of all output pins –50 mA Other than NMI/A9 pin Input voltage VI NMI/A9 pin Output voltage VO Output current low IOL Output current high A/D converter reference input voltage IOH VAREF –0.5 to AVDD + 0.3 V Ambient operating temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution ★ If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product with these rated values never exceeded. 25 ★ µPD78CP18(A) OSCILLATOR CHARACTERISTICS RESONATOR (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, V SS = AVSS = 0 V, VDD –0.8 V ≤ AV DD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD) RECOMMENDED CIRCUIT X1 PARAMETER TEST CONDITIONS A/D converter not used X2 Ceramic or crystal resonator MIN. MAX. 4 15 Oscillator frequency (fXX) C1 UNIT MHz C2 A/D converter used A/D converter not used X1 X2 5.8 15 4 15 X1 input frequency (fX) MHz A/D converter used 5.8 15 X1 rise time, fall time (tr, tf) 0 20 ns X1 input high-, lowlevel width (tΦH, tΦ L) 20 250 ns External clock HCMOS Inverter Cautions 26 1. Place the oscillator as close as possible to the X1 and X2 pins. 2. Ensure that no other signal lines pass through the shaded area. µPD78CP18(A) CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) PARAMETER SYMBOL Input capacitance TEST CONDITIONS MIN. TYP. MAX. UNIT 10 pF 20 pF 20 pF CI Output capacitance CO Input-output capacitance CIO fC = 1 MHz Unmeasured pins returned to 0 V DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, V SS = AVSS = 0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. VIL1 All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 0 VIL2 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 0 VIH1 All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 VIH2 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 VOL IOL = 2.0 mA TYP. MAX. UNIT 0.8 V Input voltage low 2.2 0.2VDD V VDD V VDD V 0.45 V Input voltage high Output voltage low Output voltage high 0.8 VDD IOH = –1.0 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V VOH Input current II INT1Note1, TI(PC3)Note2 ; 0 V ≤ VI ≤ VDD ±200 µA Input leakage current All except INT1, TI (PC3), AN7 to AN0; 0 V ≤ VI ≤ VDD ±10 µA ILI AN7 to AN0; 0 V ≤ VI ≤ VDD ±1 µA 0 V ≤ VO ≤ V DD ±10 µA Output leakage current AVDD power supply current VDD power supply current ILO AIDD1 Operating mode fXX = 15 MHz 0.5 1.3 mA AIDD2 STOP mode 10 20 µA IDD1 Operating mode fXX = 15 MHz 16 35 mA IDD2 HALT mode fXX = 15 MHz 7 13 mA Data retention voltage VDDDR Data retention current IDDDR Hardware/software STOP mode 2.5 V Hardware/softwareNote3 VDDDR = 2.5 V 1 15 µA STOP mode VDDDR = 5 V ± 10 % 10 50 µA ★ Notes 1. If self-bias should be generated by ZCM register. 2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register. 3. If self-bias is not generated. 27 µPD78CP18(A) AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, V SS = AVSS = 0 V) READ/WRITE OPERATION: PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. X1 input cycle time tCYC 66 Address setup time (to ALE↓ ) tAL 30 ns Address hold time (from ALE↓ ) tLA 35 ns RD↓ delay time from address tAR 100 ns Address float time from RD↓ tAFR Data input time from address tAD Data input time from ALE↓ tLDR fXX = 15 MHz, CL = 150 pF CL = 150 pF 167 UNIT ns 20 ns 250 ns 135 ns 120 ns fXX = 15 MHz, CL = 150 pF Data input time from RD↓ tRD RD↓ delay time from ALE↓ tLR Data hold time (from RD↑ ) tRDH ALE↑ delay time from RD↑ tRL RD low-level width 15 ns CL = 150 pF 0 ns fXX = 15 MHz, CL = 150 pF 80 ns In data read fXX = 15 MHz, CL = 150 pF 215 ns In OP code fetch fXX = 15 MHz, CL = 150 pF 415 ns fXX = 15 MHz, CL = 150 pF 90 ns 100 ns tRR ALE high-level width tLL WR↓ delay time from address tAW fXX = 15 MHz, CL = 150 pF 197 ns 140 ns Data output time from ALE↓ tLDW Data output time from WR↓ tWD WR↓ delay time from ALE↓ tLW 15 ns Data setup time (to WR↑ ) tDW 127 ns Data hold time (from WR↑ ) tWDH 60 ns ALE↑ delay time from WR↑ tWL 80 ns WR low-level width tWW 215 ns CL = 150 pF fXX = 15 MHz, CL = 150 pF ZERO-CROSS CHARACTERISTICS : PARAMETER SYMBOL Zero-cross detection input VZX Zero-cross accuracy AZX Zero-cross detection input frequency fZX 28 TEST CONDITIONS MIN. MAX. UNIT 1 1.8 VACP-P ±135 mV 1 kHz AC coupling 60-Hz sine wave 0.05 µPD78CP18(A) SERIAL OPERATION : PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT Note1 800 ns Note2 400 ns 1.6 µs Note1 335 ns Note2 160 ns 700 ns Note1 335 ns Note2 160 ns SCK output 700 ns SCK input SCK cycle time tCYK SCK output SCK input SCK low-level width tKKL SCK output SCK input SCK high-level width tKKH RXD setup time (to SCK↑ ) tRXK Note1 80 ns RXD hold time (from SCK↑ ) tKRX Note1 80 ns TXD delay time from SCK↓ tKTX Note1 210 ns MAX. UNIT Notes 1. If clock rate is × 1 in asynchronous mode, synchronous mode, or I/O interface mode. 2. If clock rate is × 16 or × 64 in asynchronous mode. Remark The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF. OTHER OPERATION : PARAMETER TI high-, low-level width SYMBOL TEST CONDITIONS tTIH, tTIL MIN. 6 tCYC 6 tCYC 48 tCYC • Event counter mode tCI1H, tCI1L • Frequency test mode CI high-, low-level width • Pulse width test mode tCI2H, tCI2L • ECNT latch and clear input • INTEIN set input NMI high-, low-level width tNIH, tNIL 10 µs INT1 high-, low-level width tI1H, tI1L 36 tCYC INT2 high-, low-level width tI2H, tI2L 36 tCYC AN4 to AN7, low-level width tANH, tANL 36 tCYC RESET high-, low-level width tRSH, tRSL 10 µs 29 µPD78CP18(A) A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5.0 V ± 10 %, V SS = AVSS = 0 V, VDD – 0.5 V ≤ AV DD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD) PARAMETER SYMBOL TEST CONDITIONS MIN. Resolution Sampling time ★ MAX. 8 Absolute accuracyNote Conversion time TYP. tCONV tSAMP Analog input voltage VIAN Analog input impedance RAN Reference voltage VAREF UNIT Bits 3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns ±0.8 % FSR 4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns ±0.6 % FSR TA = –10 to +70 °C, 4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns ±0.4 % FSR 66 ns ≤ tCYC ≤ 110 ns 576 tCYC 110 ns ≤ tCYC ≤ 167 ns 432 tCYC 66 ns ≤ tCYC ≤ 110 ns 96 tCYC 110 ns ≤ tCYC ≤ 167 ns 72 tCYC –0.3 VAREF + 0.3 50 3.4 V MΩ AVDD V IAREF1 Operating mode 1.5 3.0 mA IAREF2 STOP mode 0.7 1.5 mA AIDD1 Operating mode fXX = 15 MHz 0.5 1.3 mA AIDD2 STOP mode 10 20 µA VAREF current AVDD power supply current Note Quantization error (±1/2 LSB) is not included. AC Timing Test Point VDD – 1.0 V 0.45 V 30 2.2 V 0.8 V Test Points 2.2 V 0.8 V µPD78CP18(A) tCYC-Dependent AC Characteristics Expression PARAMETER EXPRESSION MIN./MAX. UNIT tAL 2T – 100 MIN. ns tLA T – 30 MIN. ns tAR 3T – 100 MIN. ns tAD 7T – 220 MAX. ns tLDR 5T – 200 MAX. ns tRD 4T – 150 MAX. ns tLR T – 50 MIN. ns tRL 2T – 50 MIN. ns MIN. ns 4T – 50 (In data read) tRR 7T – 50 (In OP code fetch) tLL 2T – 40 MIN. ns tAW 3T – 100 MIN. ns tLDW T + 130 MAX. ns tLW T – 50 MIN. ns tDW 4T – 140 MIN. ns tWDH 2T – 70 MIN. ns tWL 2T – 50 MIN. ns tWW 4T – 50 MIN. ns MIN. ns MIN. ns MIN. ns tCYK tKKL 12T (SCK input)Note1 6T (SCK input)Note2 24T (SCK output) 5T + 5 (SCK input)Note1 2.5T + 5 (SCK input)Note2 12T – 100 (SCK output) tKKH 5T + 5 (SCK input)Note1 2.5T + 5 (SCK input)Note2 12T – 100 (SCK output) Notes 1. If clock rate is ×1, in asynchronous mode, synchronous mode, or I/O interface mode. 2. If clock rate is ×16, ×64 in asynchronous mode. Remarks 1. T = tCYC = 1/fXX 2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX). 31 µPD78CP18(A) Timing Waveforms Read Operation tCYC X1 Address (Higher) PF7 to PF0 tAD PD7 to PD0 Read Data Address (Lower) tLL tLDR tLA tRDH tRL tAFR ALE tAL tRD tRR RD tLR tAR Write Operation X1 PF7 to PF0 Address (Higher) tLDW PD7 to PD0 tLL tDW tLA tWDH tWD ALE tWW tAL WR tLW tAW 32 Write Data Address (Lower) tWL µPD78CP18(A) Serial Operation tCYK tKKL tKKH SCK tKTX TXD R XD tRXK tKRX Timer Input Timing tTIH tTIL tCI1H tCI1L tCI2H tCI2L TI Timer/Event Counter Input Timing Event Counter Mode CI Pulse Width Test Mode CI 33 µPD78CP18(A) Interrupt Input Timing tNIH tNIL tI1L tI1H tI2H tI2L tRSH tRSL NMI INT1 INT2 Reset Input Timing RESET 0.8VDD 0.2VDD External Clock Timing tφH 0.8VDD X1 0.8 V tr tf tφL tCYC 34 µPD78CP18(A) DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) PARAMETER SYMBOL Data retention power supply voltage VDDDR Data retention power supply current IDDDR TEST CONDITIONS MIN. TYP. 2.5 MAX. UNIT 5.5 V VDDDR = 2.5 V 1 15 µA VDDDR = 5 V ± 10 % 10 50 µA ★ µs VDD rise/fall time tRVD, tFVD 200 STOP setup time (to VDD) tSSTVD 12T + 0.5 Note µs STOP hold time (from VDD) tHVDST 12T + 0.5 Note µs Note T= tCYC = 1/fXX Data Retention Timing 90 % VDD 10 % tFVD tSSTVD STOP VDDDR tRVD tHVDST VIH2 VIL2 35 µPD78CP18(A) DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5 °C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V) PARAMETER SYMBOL SYMBOLNote TEST CONDITIONS MIN. TYP. MAX. UNIT Input voltage high VIH VIH 2.4 VDDP + 0.3 V Input voltage low VIL VIL –0.3 0.8 V Input leakage current ILIP ILI 0 ≤ V I ≤ VDDP; except INT1, TI (PC3) ±10 µA Output voltage high VOH VOH IOH = –1.0 mA Output voltage low VOL VOL IOL = 2.0 mA 0.45 V Output leakage current ILO –– 0 ≤ V O ≤ VDDP, OE = VIH ±10 µA VDDP supply voltage VDDP VDD VPP supply voltage VPP VPP VPP supply current IDD IPP IDD IPP Note Corresponding µPD27C256A symbol 36 V EPROM programming mode 5.75 6.0 6.25 V EPROM read mode 4.5 5.0 5.5 V EPROM programming mode 12.2 12.5 12.8 V EPROM read mode VDDP supply current VDD – 1.0 VPP = VDDP V EPROM programming mode 5 50 mA EPROM read mode CE = VIL, V I = VIH 5 50 mA EPROM programming mode CE = VIL, OE = V IH 5 30 mA EPROM read mode 1 100 µA µPD78CP18(A) AC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5 °C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V) PARAMETER SYMBOL SYMBOLNote1 TEST CONDITIONS MIN. TYP. MAX. Address setup time (to CE↓) tSAC tAS 2 µs OE↓ delay time from data tDDOO tOES 2 µs Input data setup time (to CE↓) tSIDC tDS 2 µs Address hold time (from CE↑) tHCA tAH 2 µs Input data hold time (from CE↑) tHCID tDH 2 µs Output data hold time (from OE↑) tHOOD tDF 0 VPP setup time (to CE↓) tSVPC tVPS 2 µs VDDP setup time (to CE↓) tSVDC tVDS 2 µs Initial program pulse width tWL1 tPW 0.95 Additional program pulse width tWL2 tOPW 2.85 EPROM programming/read mode setup time (to CE↓)Note2 tSMC –– Data output time from address tDAOD tACC Data output time from CE↓ tDCOD Data output time from OE↓ 130 1.0 UNIT ns 1.05 ms 78.75 ms µs 2 1 µs tCE 1 µs tDOOD tOE 1 µs Data hold time (from OE↑) tHCOD tDF 130 ns Data hold time (from address) tHAOD tOH OE = VIL 0 OE = VIL 0 ns Notes 1. Corresponding µPD27C256A symbol 2. Indicates state in which MODE1 = VIL and MODE0 = VIH. 37 µPD78CP18(A) PROM Programming Mode Timing A12 to A0 Effective Address tHOOD tSAC D7 to D0 Data Input tSIDC tHCA Data Output Data Input tHCID tSIDC tHCID VIH MODE1 = VIL MODE0 = VIH MODE1 MODE0 VIL tSMC VPP VPP VDDP tSVPC VDDP + 1 VDDP VDDP tSVDC VIH CE tDDOO VIL tWL1 OE tWL2 tDOOD VIH VIL Cautions 1. Ensure that VDDP is applied before VPP, and cut after VPP. 2. Ensure that VPP does not exceed +13 V including overshoot. PROM Read Mode Timing A12 to A0 Effective Address CE tDCOD OE tDAOD tDOOD tHCOD tHAOD Hi-Z D7 to D0 Cautions 38 Hi-Z Data Output 1. If you wish to read within the tDAOD range, the OE input delay time from the fall of CE should be a maximum of tDAOD - tDOOD. 2. tHCOD is the time from the point at which OE or CE (whichever is first) reaches VIH. µPD78CP18(A) 7. CHARACTERISTIC CURVES (REFERENCE VALUE) IDD1, IDD2 vs. VDD (TA = 25 ˚C, fXX = 15 MHz) 30 25 VDD Power Supply Current IDD1, IDD2 [mA] IDD1 (TYP.) 20 15 10 5 IDD2 (TYP.) 0 0 4.5 5.0 5.5 6.0 Power Supply Voltage VDD [V] IDD1, IDD2 vs. fXX (TA = 25 ˚C, VDD = 5 V) VDD Power Supply Current IDD1, IDD2 [mA] 30 IDD1 (TYP.) 20 10 IDD2 (TYP.) 0 0 5 10 15 Oscillator Frequency fXX [MHz] 39 µPD78CP18(A) IOL vs. VOL (TA = 25 ˚C, VDD = 5 V) 2.5 TYP. Output Current Low IOL [mA] 2.0 1.5 1.0 0.5 0 0 0.1 0.2 0.3 0.4 0.5 Output Voltage Low VOL [V] IOH vs. VOH (TA = 25 ˚C, VDD = 5 V) –1.5 Output Current High IOH [mA] TYP. –1.0 –0.5 0 0 0.1 0.2 0.3 0.4 Power Supply Voltage – Output Voltage High VDD – VOH [V] 40 0.5 µPD78CP18(A) IDDDR vs. VDDDR (TA = 25 ˚C) Data Retention Power Supply Current IDDDR [ µ A] 10 8 6 TYP. 4 2 0 0 2 3 4 5 6 Data Retention Power Supply Voltage VDDDR [V] 41 µPD78CP18(A) 8. PACKAGE DRAWINGS 64 PIN PLASTIC QUIP A 33 1 32 C 64 W P S X M H I M J N K P64GQ-100-36 NOTE Each lead centerline is located within 0.25 mm (0.010 inch) of its true position (T.P.) at maximum material condition. 42 ITEM MILLIMETERS A 41.5 +0.3 –0.2 INCHES C 16.5 0.650 H – 0.50 +0.10 0.020 +0.004 –0.005 I 0.25 0.010 J 2.54 (T.P.) 0.100 (T.P.) 1.634+0.012 –0.008 K 1.27 (T.P.) 0.050 (T.P.) M 1.1 +0.25 –0.15 0.043+0.011 –0.006 N +0.10 0.25 –0.05 0.010 +0.004 –0.003 P 4.0 – S 3.6 – 0.142 –0.005 W – 24.13 +1.05 0.950 – X – 19.05 +1.05 0.750 – +0.3 +0.1 0.157+0.013 –0.012 +0.004 +0.042 +0.042 µPD78CP18(A) 64 PIN PLASTIC QFP (14×20) A B 33 32 64 1 20 19 detail of lead end F Q 5°±5° D C S 51 52 G H I M J M P K N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.40 ± 0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.8 ± 0.2 0.071–0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.12 0.005 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. +0.008 43 µPD78CP18(A) ★ 9. RECOMMENDED SOLDERING CONDITIONS The µPD78CP18(A) should be soldered and mounted under the following recommended conditions. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual (IEI-1207)". For soldering methods and conditions other than those recommended below, contact an NEC representative. Table 9-1. Surface Mount Type Soldering Conditions µPD78CP18GF(A)-3BE: 64-Pin Plastic QFP (14 × 20 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or higher), Count: Twice or less <Attention> (1) (2) (1) (2) VP15-00-2 Perform the second reflow at the time the device temperature is lowered to the room temperature from the heating by the first reflow. Do not wash the soldered portion with the flux following the first reflow. Wave soldering Solder bath temperature: 260 °C max., Duration: 10 sec. max., Count: Once Preheating temperature: 120 °C max. (package surface temperature) Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side row of pins) Caution IR35-00-2 Perform the second reflow at the time the device temperature is lowered to the room temperature from the heating by the first reflow. Do not wash the soldered portion with the flux following the first reflow. Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or higher), Count: Twice or less <Attention> VPS Recommended Condition Symbol WS60-00-1 —— Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 9-2. Through-Hole Type Soldering Conditions µPD78CP18GQ(A)-36: 64-Pin Plastic QUIP Soldering Method Wave soldering (pin part only) Solder bath temperature: 260 °C max., Duration: 10 sec. max. Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per pin) Caution 44 Soldering Conditions Wave soldering is used on the pin only, and care must be taken to prevent solder from coming into direct contact with the body. µPD78CP18(A) 10. DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78C18(A) Part Number Item µPD78CP18(A) µPD78C18(A) Internal ROM 32 K × 8 bits (PROM) 32 K × 8 bits (mask ROM) Internal RAM 1 K × 8 bits 1 K × 8 bits Pin connection PB7/OE PB7 PB6/CE PB6 STOP/VPP STOP NMI/A9 NMI PA7/A7 to PA0/A0 PA7 to PA0 PF6/A14 to PF2/A10 PF6 to PF2 PF0/A8 PF0 PD7/O7 to PD0/O0 PD7 to PD0 Mode set by MODE pins (when MODE0 is set to 1, and MODE1 to 0) MODE0 pin input/output function Internal memory access area setting by MM register Port A to Port C PROM programming mode • Operates as the µPD78C17(A) (ROM-less mode) • External memory 16 K extension mode Input onlyNote Input/output Yes No Pull-up resistors not incorporated Pull-up resistor incorporation selectable bit-wise by mask option Note An emulation control signal is not output even if the MODE0 pin is pulled high. 45 µPD78CP18(A) APPENDIX DEVELOPMENT TOOLS The following development tools are available to develop a system which uses the µPD78CP18(A). Language Processor 87AD series relocatable assembler (RA87) This is a program which converts a program written in mnemonic to an object code for which microcomputer execution is possible. Moreover, it contains a function to automatically create a symbol/table, and optimize branch instructions. Host Machine PC-9800 series IBM PC/ATTM OS MS-DOSTM Ver. 2.11 to Ver. 5.00ANote Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13RA87 5-inch 2HD µS5A10RA87 3.5-inch 2HC µS7B13RA87 5-inch 2HC µS7B10RA87 PC DOSTM (Ver. 3.1) PROM Write Tools Hardware PG-1500 With a provided board and an optional programmer adapter connected, this PROM programmer can manipulate from a stand-alone or host machine to perform programming on a single-chip microcomputer which incorporates PROM. It is also capable of programming a typical PROM ranging from 256 K to 4 M bits. PA-78CP14GF/ GQ PROM programmer adapter for the µPD78CP18(A). Used by connecting to the PG-1500. PA-78CP14GF For the µPD78CP18GF(A)-3BE PA-78CP14GQ For the µPD78CP18GQ(A)-36 PG-1500 controller Connects the PG-1500 to a host machine by using serial and parallel interface, to control the PG1500 on a host machine. Host Machine Software ★ PC-9800 series IBM PC/AT OS MS-DOS Ver. 2.11 to Ver. 5.00ANote PC DOS (Ver. 3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 5-inch 2HC µS7B10PG1500 Note Versions 5.00 and 5.00A have a task swap function, but this function cannot be used with this software. Remark 46 The operations of the assembler and the PG-1500 controller are guaranteed only on the above host machines and operating systems. µPD78CP18(A) Debugging Tools IE-78C11-M The IE-78C11-M is an in-circuit emulator which works with the 87AD series. It can be connected to a host machine to perform efficient debugging. IE-78C11-M control program (IE controller) Connects the IE-78C11-M to host machine by using the RS-233C, to control the IE-78C11-M on host machine. Software Hardware An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for the µ PD78CP18(A). The following table shows its system configuration. Host Machine PC-9800 series IBM PC/AT Remark OS MS-DOS Ver. 2.11 to Ver. 3.30D PC DOS (Ver. 3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13IE78C11 5-inch 2HD µS5A10IE78C11 5-inch 2HC µS7B10IE78C11 The operations of the IE controller are guaranteed only on the above host machines and operating systems. 47 µPD78CP18(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards wiht semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 48 µPD78CP18(A) [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 QTOP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.