www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 !" FEATURES D Qualification in Accordance With AEC-Q100(1) D Qualified for Automotive Applications D Customer-Specific Configuration Control Can D D D D D D D Be Supported Along With Major-Change Approval 60-mΩ MOSFET Switches for High Efficiency at 3-A Continuous Output Source or Sink Current 0.9-V to 3.3-V Adjustable Output Voltage With 1% Accuracy Externally Compensated for Design Flexibility Fast Transient Response Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost DESCRIPTION As members of the SWIFT family of dc/dc regulators, the TPS54310 low-input-voltage high-output-current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high-performance, voltage error amplifier that provides high performance under transient conditions, an undervoltage-lockout circuit to prevent start up until the input voltage reaches 3 V, an internally and externally set slow-start circuit to limit in-rush currents, and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54310 device is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. Texas Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. (1) Contact Texas Instruments for details. Q100 qualification data available on request. APPLICATIONS D Point of Load Regulation for High D D Performance DSPs, FPGAs, ASICs, and Microprocessors Automotive Systems − Navigation Units − Entertainment Modules − Satellite Radio Industrial High-Density Systems With Power Distributed at 5 V or 3.3 V ORDERING INFORMATION TJ OUTPUT VOLTAGE PACKAGED DEVICES PLASTIC HTSSOP (PWP)(1) −40°C to 125°C 0.9 V to 3.3 V TPS54310QPWPRQ1 (1) The PWP package is taped and reeled as indicated by the R suffix to the device type (i.e., TPS54310QPWPRQ1). See the Application section of the data sheet for PowerPAD drawing and layout information. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. #$%&'()*#&$ # +,''-$* ) &% .,/0#+)*#&$ 1)*-2 '&1,+* +&$%&'( *& .-+#%#+)*#&$ .-' *3- *-'( &% -4) $*',(-$* *)$1)'1 5)'')$*62 '&1,+*#&$ .'&+-#$7 1&- $&* $-+-)'#06 #$+0,1- *-*#$7 &% )00 .)')(-*-'2 Copyright 2007, Texas Instruments Incorporated www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. EFFICIENCY vs LOAD CURRENT Simplified Schematic Input VIN Output PH 96 TPS54310 94 BOOT 92 Efficiency − % PGND COMP VBIAS VSENSE 90 88 86 84 AGND Compensation Network TA = 25°C VI = 5 V VO = 3.3 V 82 80 0 0.5 1 1.5 2 2.5 3 Load Current − A ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Input voltage range, VI Output voltage range, VO TPS54310-Q1 UNIT VIN, SS/ENA, FSEL −0.3 to 7 V RT −0.3 to 6 V VSENSE −0.3 to 4 V BOOT −0.3 to 17 V VBIAS, PWRGD, COMP −0.3 to 7 V PH −0.6 to 10 V PH Source current, IO Sink current COMP, VBIAS 6 PH 6 A COMP 6 mA 10 mA ±0.3 V SS/ENA,PWRGD Voltage differential Internally Limited AGND to PGND mA Continuous power dissipation See Power Dissipation Rating Table Operating virtual junction temperature range, TJ −40 to 150 °C Storage temperature, Tstg −65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS MIN Input voltage range, VI Operating junction temperature, TJ NOM MAX UNIT 3 6 V −40 125 °C PACKAGE DISSIPATION RATINGS(1) (2) 20-pin PWP with solder 26°C/W TA = 25°C POWER RATING 3.85 W(3) 20-pin PWP without solder 57.5°C/W 1.73 W PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 70°C POWER RATING TA = 85°C POWER RATING 2.12 W 1.54 W 0.96 W 0.69 W (1) For more information on the PWP package, see the Texas Instruments technical brief (SLMA002). (2) Test board conditions: 1. 3” × 3”, 2 layers, Thickness: 0.062” 2. 1.5 oz copper traces located on the top of the PCB 3. 1.5 oz copper ground plane on the bottom of the PCB 4. Ten thermal vias (see the recommended land pattern in application section of this data sheet) (3) Maximum power dissipation may be limited by overcurrent protection. 3 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN VIN input voltage range Quiescent current 3 6 fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open 6.2 9.6 fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase pin open 8.4 12.8 1 1.4 2.95 3 Shutdown, SS/ENA = 0 V V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO 2.7 Hysteresis voltage, UVLO Rising and falling edge deglitch, UVLO(1) 2.8 V 0.16 V 2.5 µs BIAS VOLTAGE VO Output voltage, VBIAS Output current, VBIAS(2) I(VBIAS) = 0 2.7 CUMULATIVE REFERENCE Vref Accuracy(1) 0.882 2.8 0.891 2.95 V 100 µA 0.900 V REGULATION Line regulation(1) (3) IL = 1.5 A, fs = 350 kHz, TJ = 125°C IL = 1.5 A, fs = 550 kHz, TJ = 125°C 0.07 Load regulation (1) (3) IL = 0 A to 3 A, fs = 350 kHz, TJ = 125°C IL = 0 A to 3 A, fs = 550 kHz, TJ = 125°C 0.03 0.07 0.03 %/V %/A OSCILLATOR Internally set free-running frequency range Externally set free-running frequency range High-level threshold voltage, FSEL Low-level threshold voltage, FSEL Pulse duration, FSEL(1) Frequency range, FSEL(1) (4) Ramp valley(1) FSEL ≤ 0.8 V, RT open 265 350 440 FSEL ≥ 2.5 V, RT open 415 550 680 RT = 180 kΩ (1% resistor to AGND)(1) 252 280 308 RT = 160 kΩ (1% resistor to AGND) RT = 68 kΩ (1% resistor to AGND)(1) 290 312 350 663 700 762 2.5 Maximum duty cycle(1) 50 V ns 330 700 0.75 kHz V 1 V 200 90% (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 10. (4) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and C ≤ 120 pF. 4 kHz V 0.8 Ramp amplitude (peak-to-peak)(1) Minimum controllable on time(1) kHz ns www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1-kΩ COMP to AGND(1) 90 110 Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (1) 3 5 Powered by internal LDO(1) 0 IIB Error amplifier common-mode input voltage range Input bias current, VSENSE(1) VO Output voltage slew rate (symmetric), COMP(1) VSENSE = Vref 60 1 dB MHz VBIAS V 250 nA 1.4 V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) 10-mV overdrive(1) 70 85 ns 1.2 1.4 V SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 Enable hysteresis voltage, SS/ENA(1) Falling edge deglitch, SS/ENA(1) Internal slow-start time(1) 0.03 V 2.5 µs 2.6 3.35 4.1 Charge current, SS/ENA SS/ENA = 0 V 2.5 5 8 ms µA Discharge current, SS/ENA SS/ENA = 0.2 V, VI = 2.7 V 1.2 2.3 4 mA POWER GOOD Power good threshold voltage VSENSE falling 90 Power good hysteresis voltage(1) Power good falling edge deglitch(1) Output saturation voltage, PWRGD Leakage current, PWRGD %Vref %Vref 3 µs 35 I(sink) = 2.5 mA VI = 5.5 V 0.18 0.3 1 V µA CURRENT LIMIT Current limit trip point VI = 3 V, output shorted(1) VI = 6 V, output shorted(1) 4 6.5 4.5 7.5 A Current limit leading edge blanking time 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) Thermal shutdown hysteresis(1) 135 150 165 °C °C 10 OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches IO = 3 A, IO = 3 A, VI = 6 V(2) VI = 3 V(2) 59 88 85 136 mΩ (1) Specified by design (2) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design 5 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT FSEL SS/ENA VBIAS VIN VIN VIN PGND PGND PGND Terminal Functions TERMINAL NAME DESCRIPTION NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and FSEL pin. Make PowerPAD connection to AGND. BOOT 5 Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect the compensation network from COMP to VSENSE. PGND 11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns and negative terminals of the input and output capacitors. PH 6−10 Phase input/output. Junction of the internal high and low-side power MOSFETs and output inductor. PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active. RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. SS/ENA 18 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. FSEL 19 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1-µF ceramic capacitor. 14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to the device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor. VIN VSENSE 6 2 Error amplifier inverting input. www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator 2.95 V Hysteresis: 0.16 V VIN ILIM Comparator Thermal Shutdown 150°C 3−6V Leading Edge Blanking Falling and Rising Edge Deglitch VIN REG VBIAS SHUTDOWN 100 ns BOOT 30 mΩ 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.35 ms PH + − R Q S Error Amplifier Reference VREF = 0.891 V PWM Comparator LOUT VO CO Adaptive Dead-Time and Control Logic VIN 30 mΩ OSC PGND Powergood Comparator PWRGD VSENSE Falling Edge Deglitch 0.90 Vref TPS54310 Hysteresis: 0.03 Vref VSENSE COMP RT SHUTDOWN 35 µs FSEL ADDITIONAL 3-A SWIFT DEVICES DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE TPS54311 0.9 V TPS54313 1.5 V TPS54315 2.5 V TPS54312 1.2 V TPS54314 1.8 V TPS54316 3.3 V RELATED DC/DC PRODUCTS D UCC3585—dc/dc controller D PT5500 series—3-A plug-in modules D TPS757XX—3-A low dropout regulator 7 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 100 IO = 3 A 80 60 40 20 VI = 5 V 0 25 85 IO = 3 A 80 60 40 20 0 −40 0 −40 125 TJ − Junction Temperature − °C 0 25 800 600 RT = 100 k 500 400 RT = 180 k 300 0.893 0.891 0.889 0.887 −80 −120 40 Gain 20 −140 −160 0 −180 −20 −200 10 k 100 k 1 M 10 M 0 10 100 1k f − Frequency − Hz Figure 7 Internal Slow-Start Time − ms −40 −100 60 f = 350 kHz 0.8870 0 25 85 3 125 4 5 VI − Input Voltage − V 6 Figure 6 DEVICE POWER LOSSES vs LOAD CURRENT 3.80 2.25 3.65 2 −20 −60 Phase 0.8890 INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE Phase − Degrees RL= 10 kΩ, CL = 160 pF, TA = 25°C 125 0.8910 Figure 5 0 140 85 0.8930 TJ − Junction Temperature − °C ERROR AMPLIFIER OPEN LOOP RESPONSE 25 0.8850 0.885 −40 125 Figure 4 80 0 TA = 85°C Device Power Losses − W 85 100 250 −40 0.8950 TJ − Junction Temperature − °C 120 350 OUTPUT VOLTAGE REGULATION vs INPUT VOLTAGE VO − Output Voltage Regulation − V 700 25 FSEL ≤ 0.8 V Figure 3 0.895 0 450 TJ − Junction Temperature − °C RT = 68 k 200 −40 FSEL ≥ 2.5 V 550 VOLTAGE REFERENCE vs JUNCTION TEMPERATURE Vref − Voltage Reference − V f − Externally Set Oscillator Frequency − kHz 125 650 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE Gain − dB 85 750 TJ − Junction Temperature − °C Figure 1 8 f − Internally Set Oscillator Frequency −kHz 100 Drain-Source On-State Resistance − Ω Drain-Source On-State Resistance − Ω 120 VI = 3.3 V INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 3.50 3.35 3.20 3.05 TJ − 125°C fs = 700 kHz 1.75 1.5 VI = 3.3 V 1.25 1 VI = 5 V 0.75 0.5 2.90 0.25 2.75 −40 0 25 85 TJ − Junction Temperature − °C Figure 8 125 0 0 1 2 3 IL − Load Current − A Figure 9 4 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up to 3 A of output current at a nominal output voltage of J1 VI GND 3.3 V. For proper thermal performance, the power pad underneath the TPS54310 integrated circuit needs to be soldered well to the printed circuit board. VIN 2 1 C2 + R3 1 R1 10 kΩ 71.5 kΩ U1 TPS54310PWP 20 19 18 17 C3 0.1 µF 4 PWRGD RT VIN SS/ENA 2 PH C5 3900 pF C4 100 pF R2 3.74 kΩ 9 PH 3 COMP 6 5 BOOT 13 PGND AGND PGND GND C11 1000 pF C7 0.047 µF 11 PGND PwrPAD 2700 pF R5 C9 180 µF 4V VO 12 C6 R4 3.74 kΩ J3 2 + 8 7 PH VSENSE 1 10 PH VBIAS PWRGD L1 1.2 µH 14 VIN PH 1 15 VIN FSEL C8 10 µF 16 R6 R7 732 Ω 49.9 Ω 10 kΩ 1 Optional Figure 10. TPS54310 Schematic INPUT VOLTAGE OUTPUT FILTER The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54310 and must be located as close to the device as possible. The output filter is composed of a 1.2-µH inductor and 180-µF capacitor. The inductor is a low dc-resistance (0.017 Ω) type, Coilcraft DO1813P-122HC. The capacitor used is a 4-V special polymer type with a maximum ESR of 0.015 Ω. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz. FEEDBACK CIRCUIT GROUNDING AND PowerPAD LAYOUT The resistor divider network of R5 and R4 sets the output voltage for the circuit at 3.3 V. R5, along with R2, R6, C4, C5, and C6 forms the loop compensation network for the circuit. For this design, a Type 3 topology is used. The TPS54310 has two internal grounds (analog and power). Inside the TPS54310, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54310, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground planes are recommended. These two planes should tie together directly at the IC to reduce noise between the two grounds. The only components that should tie directly to the power ground plane are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54310. The layout of the TPS54310 evaluation module is representative of a recommended layout for a OPERATING FREQUENCY In the application circuit, the 350-kHz operation is selected by leaving RT and FSEL open. Connecting a 68-kΩ to 180-kΩ resistor between RT (pin 20) and analog ground can be used to set the switching frequency from 280 kHz to 700 kHz. To calculate the RT resistor, use equation 1: R + 100 kW ƒ SW 500 kHz (1) 9 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 2-layer board. Documentation for the TPS54310 evaluation module can be found on the Texas Instruments web site under the TPS54310 product folder and in the application note (SLVA109). LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal 6 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.0227 0.0600 0.0400 0.2560 0.2454 0.0400 0.0600 Minimum Recommended Top Side Analog Ground Area ground plane available and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the 10 recommended that enhance thermal performance should be included in areas not under the device package. Minimum Recommended Thermal Vias: 6 × 0.013 dia. Inside Powerpad Area 4 × 0.018 dia. Under Device as Shown. Additional 0.018 dia. Vias May be Used if Top Side Analog Ground Area is Extended. ÓÓÓ ÓÓÓ ÓÓÓ ÓÓÓ ÓÓÓ ÓÓÓ ÓÓÓ 0.0150 0.06 0.1010 0.0256 0.1700 0.1340 0.0620 0.0400 Minimum Recommended Exposed Copper Area For Powerpad. 5mm Stencils may Require 10 Percent Larger Area Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD 10 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 PERFORMANCE GRAPHS OUTPUT VOLTAGE vs LOAD CURRENT EFFICIENCY vs OUTPUT CURRENT VI = 5 V 3.38 90 VI = 6 V 85 80 75 70 135 Phase 40 90 3.36 3.34 Gain − dB VO − Output Voltage − % 95 3.32 3.3 45 20 Gain 0 0 TA = 25°C 3.28 −45 −20 3.26 0 1 2 3 4 −40 3.24 5 0 1 2 3 4 5 100 Figure 12 Figure 13 OUTPUT RIPPLE VOLTAGE VI = 5 V 40 µs/div 10 k 100 k −90 1M Figure 14 LOAD TRANSIENT RESPONSE VO (AC) 10 mV/div 1k f − Frequency − Hz IL − Load Current − A IO − Output Current − A SLOW-START TIMING VO (AC) 50 mV/div VI 2 V/div VO 2 V/div VPWRGD 5 V/div IO 2 A/div VI = 5 V IO = 3 A 400 ns/div 1 ms/div Figure 16 Figure 15 Figure 17 AMBIENT TEMPERATURE vs LOAD CURRENT 125 115 T A − Ambient Temperature − ° C Efficiency − % TA = 25°C VI = 5 V Phase − Degrees VI = 4 V 65 LOOP RESPONSE 60 3.4 100 VI = 5 V 105 95 85 VI = 3.3 V 75 Safe Operating Area† 65 55 45 35 25 0 1 2 3 IL − Load Current − A 4 † The safe operating area is applicable to the test board conditions listed in the Dissipation Rating Table section of this data sheet. Figure 18 11 www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54310 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. Slow-Start/Enable (SS/ENA) The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: td + C (SS) 1.2 V 5 mA (2) Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. Voltage Reference The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54310, since it cancels offset errors in the scale and error amplifier circuits. Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a static digital input. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: SWITCHING FREQUENCY + 100 kW R 500 kHz (4) External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving a synchronization signal into FSEL and connecting a resistor from RT to AGND. Choose an RT resistor that sets the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection configurations. Table 1. Summary of the Frequency Selection Configurations SWITCHING FREQUENCY FSEL PIN RT PIN 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥ 2.5 V Float The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal rate. Externally set 280 kHz to 700 kHz Float R = 68 kΩ to 180 kΩ VBIAS Regulator (VBIAS) Externally synchronized frequency(1) Synchronization signal R = RT value for 80% of external synchronization frequency t (SS) +C (SS) 0.7 V 5 mA (3) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the 12 (1) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1 kΩ and C ≤ 120 pF. www.ti.com SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 Error Amplifier The high performance, wide bandwidth, voltage error amplifier sets the TPS54310 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type 2 or Type 3 compensation can be employed using external compensation components. PWM Control Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54310 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. Dead-Time Control and MOSFET Drivers Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. Overcurrent Protection The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. Thermal Shutdown The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to 10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault, and then shutting down upon reaching the thermal shutdown point. Power Good (PWRGD) The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold, SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise. 13 PACKAGE OPTION ADDENDUM www.ti.com 15-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS54310QPWPRQ1 ACTIVE HTSSOP PWP Pins Package Eco Plan (2) Qty 20 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Mailing Address: Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated