E2H0093-15-90 ¡ Semiconductor MSC23409C/CL-xxDS9 ¡ Semiconductor This version: Sep. 1995 MSC23409C/CL-xxDS9 4,194,304-Word ¥ 9-Bit DRAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The OKI MSC23409C/CL-xxDS9 is a fully decoded 4,194,304-word ¥ 9-bit CMOS Dynamic Random Access Memory Module composed of nine 4-Mb DRAMs (4M ¥ 1) in SOJ packages mounted with nine decoupling capacitors on a 30-pin glass epoxy single-inline package. This module is generally used for memory expansion in parity applications such as workstations. The low-power version (CL) offers reduced power consumption for mobile computing applications like laptops and palmtops. FEATURES • 4-Meg ¥ 9-bit organization • 30-Pin Socket Insertable Module MSC23409C/CL-xxDS9 : Solder tab • Single 5 V supply ±10% tolerance • Access times : 60, 70, 80 ns • Input : TTL compatible • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms (128 ms : L-version) • CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Fast Page Mode capability PRODUCT FAMILY Family Access Time (Max.) Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) tRAC tAA tCAC MSC23409C/CL-60DS9 60 ns 30 ns 15 ns 110 ns 4950 mW MSC23409C/CL-70DS9 70 ns 35 ns 20 ns 130 ns 4455 mW MSC23409C/CL-80DS9 80 ns 40 ns 20 ns 150 ns 3960 mW 49.5 mW/ 9.9 mW (L-version) 1/13 ¡ Semiconductor MSC23409C/CL-xxDS9 PIN CONFIGURATION MSC23409C/CL-xxDS9 88.9 ±0.2 82.14 Typ. 3.38 Tpy. *1 5.28 Max. f 3.18 20.45 Max. Typ. 10.16 Typ. 6.35 2.03 Typ. 1 30 2.54 Min. 5.59 Typ. 2.54 ±0.1 1.78 Typ. +0.1 1.27 –0.08 73.66 *1 The common size difference of the board width 12.5 mm of its height is specified as ±0.2. The value above 12.5 mm is specified as ±0.5. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VCC 11 A4 21 WE 2 CAS 12 A5 22 VSS 3 DQ0 13 DQ3 23 DQ6 4 A0 14 A6 24 NC 5 A1 15 A7 25 DQ7 6 DQ1 16 DQ4 26 Q8 7 A2 17 A8 27 RAS 8 A3 18 A9 28 CAS8 9 VSS 19 A10 29 D8 10 DQ2 20 DQ5 30 VCC 2/13 ¡ Semiconductor MSC23409C/CL-xxDS9 BLOCK DIAGRAM A0 - A10 RAS0 CAS0 WE A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS VCC DQ4 DQ1 A0 - A10 RAS D CAS Q WE VCC VSS DQ5 DQ2 A0 - A10 RAS D CAS Q WE VCC VSS DQ6 DQ3 A0 - A10 RAS D CAS Q WE VCC VSS DQ7 A0 - A10 RAS D CAS Q WE VCC VSS CAS8 VSS DQ0 A0 - A10 RAS D CAS Q WE VCC VSS C1 D8 Q8 C9 3/13 ¡ Semiconductor MSC23409C/CL-xxDS9 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –1.0 to 7.0 V Voltage VCC Supply Relative to VSS VCC –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 9 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –40 to 125 °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance (Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A10) CIN1 — 64 pF Input Capacitance (RAS, CAS, WE) CIN2 — 73 pF I/O Capacitance (DQ0 - DQ7) CDQ — 19 pF Input Capacitance (CAS8) CIN3 — 13 pF Input Capacitance (D8) CIN4 — 12 pF Output Capacitance (Q8) COUT — 13 pF Parameter Note : Capacitance measured with Boonton Meter. 4/13 ¡ Semiconductor MSC23409C/CL-xxDS9 DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC23409C/CL MSC23409C/CL MSC23409C/CL Parameter Symbol Condition -60DS9 -70DS9 Unit Note -80DS9 Min. Max. Min. Max. Min. Max. –90 90 –90 90 –90 90 µA –10 10 –10 10 –10 10 µA 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V DOUT disable Output Leakage Current ILO Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V — 900 — 810 — 720 mA 1, 2 RAS, CAS = VIH — 18 — 18 — 18 mA 1 RAS, CAS — 9 — 9 — 9 mA 1 ≥ VCC –0.2 V — 1.8 — 1.8 — 1.8 mA 1, 5 — 900 — 810 — 720 mA 1, 2 — 900 — 810 — 720 mA 1, 2 — 720 — 630 — 540 mA 1, 3 — 2.7 — 2.7 — 2.7 mA Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) ICC2 ICC3 tRC = Min. CAS = VIH, tRC = Min. (RAS-only Refresh) RAS cycling, Average Power Supply Current RAS, CAS cycling, RAS cycling, Average Power Supply Current 0 V £ VO £ 5.5 V ICC6 CAS before RAS, (CAS before RAS Refresh) tRC = Min. Average Power RAS = VIL, Supply Current ICC7 CAS cycling, (Fast Page Mode) tPC = Min. Average Power tRC = 125 µs, Supply Current (Battery Backup) Notes: 1. 2. 3. 4. 5. ICC10 CAS before RAS cycling 1, 2 4, 5 Specified values are obtained with the output open. Address can be changed once or less while RAS=VIL. Address can be changed once or less while CAS=VIH. VCC - 0.2 V ≤ VIH ≤ 6.5 V, -1.0 V ≤ VIL ≤ 0.2 V. L-version. 5/13 ¡ Semiconductor MSC23409C/CL-xxDS9 AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,9,10 MSC23409C/CL MSC23409C/CL MSC23409C/CL Parameter Symbol -60DS9 -70DS9 -80DS9 Unit Note Min. Max. Min. Max. Min. Max. tRC 110 — 130 — 150 — ns Fast Page Mode Cycle Time tPC 40 — 45 — 50 — ns Access Time from RAS tRAC — 60 — 70 — 80 Access Time from CAS tCAC — 15 — 20 — 20 ns 4, 5, 6 ns 4, 5 Access Time from Column Address tAA — 30 — 35 — 40 ns 4, 6 Access Time from CAS Precharge tCPA — 35 — 40 — 45 ns 4 Output Low Impedance Time from CAS tCLZ 0 — 0 — 0 — ns 4 Output Buffer Turn-off Delay Time tOFF 0 15 0 20 0 20 ns 7 3 Random Read or Write Cycle Time Transition Time tT 3 50 3 50 3 50 ns Refresh Period tREF — 16 — 16 — 16 ms Refresh Period (L-version) tREF — 128 — 128 — 128 ms RAS Precharge Time tRP 40 — 50 — 60 — ns RAS Pulse Width tRAS 60 10K 70 10K 80 10K ns RAS Pulse Width (Fast Page Mode) tRASP 60 100K 70 100K 80 100K ns RAS Hold Time tRSH 15 — 20 — 20 — ns CAS Precharge Time tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 15 10K 20 10K 20 10K ns CAS Hold Time tCSH 60 — 70 — 80 — ns CAS to RAS Precharge Time tCRP 5 — 5 — 5 — ns RAS to CAS Delay Time tRCD 20 45 20 50 20 60 ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 ns 6 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 15 — 15 — 15 — ns Column Address Hold Time from RAS tAR 50 — 55 — 60 — ns Column Address to RAS Lead Time tRAL 30 — 35 — 40 — ns 6/13 ¡ Semiconductor MSC23409C/CL-xxDS9 AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,9,10 MSC23409C/CL MSC23409C/CL MSC23409C/CL Parameter Symbol -60DS9 Min. -70DS9 Max. Min. -80DS9 Max. Min. Unit Note Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time tWCH 10 — 10 — 10 — ns Write Command Hold Time from RAS tWCR 45 — 50 — 60 — ns Write Command Pulse Width tWP 10 — 10 — 10 — ns Write Command to RAS Lead Time tRWL 15 — 20 — 20 — ns Write Command to CAS Lead Time tCWL 15 — 20 — 20 — ns Data-in Set-up Time tDS 0 — 0 — 0 — ns Data-in Hold Time tDH 15 — 15 — 15 — ns Data-in Hold Time from RAS tDHR 50 — 55 — 60 — ns CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) tCSR 5 — 5 — 5 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 10 — 10 — ns CAS Precharge Time (Refresh Counter Test) tCPT 30 — 35 — 40 — ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 — 10 — 10 — ns WE Hold Time from RAS (CAS before RAS) tWRH 10 — 10 — 10 — ns RAS to WE Set-up Time (Test Mode) tWTS 10 — 10 — 10 — ns RAS to WE Hold Time (Test Mode) tWTH 10 — 10 — 10 — ns 7/13 ¡ Semiconductor Notes: MSC23409C/CL-xxDS9 1. A start-up delay of 200 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times are measured between VIH and VIL. 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. RA10, CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, then data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operational state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 10. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. 8/13 ¡ Semiconductor MSC23409C/CL-xxDS9 TIMING WAVEFORM Read Cycle tRC tRP tRAS VIH – RAS V – IL tCSH tCRP tRCD CAS VIH – CAS8 VIL – tCRP tRSH tCAS , , , ,, , tRAD tASR Address VIH – VIL – tRAH tRAL tCAH tASC Row Column tAR tRRH tRCS WE VIH – VIL – tRCH tCAC tAA DQ0-7 VOH – Q8 VOL – tOFF tCLZ tRAC Open Valid Data-out "H" or "L" Write Cycle (Early Write) tRC tCSH tCRP tRCD CAS VIH – CAS8 VIL – tRSH tAR tASR tRAH tRAL tCAH tASC Row Column tCWL tWCR tWCS VIH – WE VIL – tWCH tWP tRWL tDHR tDS DQ0-7 VIH – D8 VIL – tCRP tCAS tRAD Address VIH – VIL – tRP tRAS VIH – RAS V – IL tDH Valid Data-in Note: Q8 = "Open" "H" or "L" 9/13 ¡ Semiconductor MSC23409C/CL-xxDS9 Fast Page Mode Read Cycle tRASP RAS VIH – VIL – tCSH tRCD tCRP CAS VIH – CAS8 VIL – tPC tCAS tCP tCAS tAR tASC tRP tRSH tCAS tCP tCRP , , , tASR Address VIH – VIL – tRAH Row Column tRAD tRCH VIH – VIL – tCAH tRCS tRRH tRCS tRCH tCAC Valid Data-out tAA tCPA tCPA Valid Data-out tOFF tCLZ tCLZ tCAC tAA tAA tRAC DQ0-7 VOH – Q8 VOL – Column tRCH tCAC tRAL tCAH tASC Column tRCS WE tASC tCAH Valid Data-out tOFF tCLZ tOFF "H" or "L" Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH – VIL – tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – tCAS tRCD tRAH tCSH tAR tASC Row Column tWCR VIH – WE VIL – tWCS tDS DQ0-7 VIH – D8 VIL – tCAH tPC tCAS tCP tASC tCAH Column tRSH tCAS tCP tASC tCRP tRAL tCAH Column tRWL tCWL tWCH tWP tDH Valid Data-in tWCS tDS tCWL tWCH tWP tDH Valid Data-in tWCS tDS tCWL tWCH tWP tDH Valid Data-in tDHR Note: Q8 = "Open" "H" or "L" 10/13 , ,, ¡ Semiconductor MSC23409C/CL-xxDS9 RAS-Only Refresh Cycle tRC tRP RAS tRAS VIH – VIL – tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – tRPC tRAH Row tOFF DQ0-7 VOH – Q8 VOL – Open Note: WE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRAS RAS VIH – VIL – tRPC tRP tRPC tCP tCSR tCHR tWRP tWRH CAS VIH – CAS8 VIL – tWRP WE VIH – VIL – tOFF DQ0-7 VOH – Q8 VOL – Open Note: Address = "H" or "L" "H" or "L" 11/13 ¡ Semiconductor MSC23409C/CL-xxDS9 ,,, ,,, Hidden Refresh Read Cycle tRC tRAS RAS VIH – VIL – tRCD tCRP CAS CAS8 VIH – VIL – VIH – VIL – tRSH tRAH tRAL tCAH tASC Row Column tAR tRCS WE VIH – VIL – tRRH tWRP tWRH tCAC tRAC DQ0-7 Q8 tCHR tRAD tASR Address tRAS tRP VOH – VOL – tAA tOFF Valid Data-out tCLZ "H" or "L" Hidden Refresh Write Cycle tRC tRAS V – RAS IH VIL – tRCD tCRP CAS VIH – CAS8 VIL – tRAD tASR Address VIH – VIL – tRAH Row tRAS tRP tRSH tCHR tAR tRAL tCAH tASC Column tWCR WE VIH – VIL – tRWL tWCH tWP tWCS tWRH tDH tDS DQ0-7 VIH – D8 VIL – tWRP Valid Data-in tDHR Note: Q8 = "Open" "H" or "L" 12/13 ¡ Semiconductor MSC23409C/CL-xxDS9 , , , , , CAS before RAS Refresh Counter Test Cycle tRAS tRP tRSH VIH – VIL – RAS tCSR tCHR tCPT tCAS CAS VIH – CAS8 VIL – tASC V – Address IH VIL – tCAH Column tCAC tRAL Read Cycle tAA DQ0-7 VOH – Q8 VOL – WE tWRH tCLZ tRCS tRCH tWRP tRWL tCWL tWCH tWRH tWCS VIH – VIL – tWP tDH tDS DQ0-7 VIH – D8 VIL – Q8 tRRH VIH – VIL – Write Cycle WE Valid Data-out Open tWRP tOFF Valid Data-in VOH – VOL – Open "H" or "L" WE • CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – tRAS tRPC tCP tCSR tCHR CAS VIH – CAS8 VIL – tWTS tWTH WE VIH – VIL – tOFF DQ0-7 VOH – Q8 VOL – Open Note : Address = "H" or "L" "H" or "L" 13/13