Semiconductor This version:Apr.1999 MSM5117405D 4,194,304-Word ´ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5117405D is a 4,194,304-word ´ 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5117405D achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117405D is available in a 26/24-pin plastic SOJ, 26/24-pin plastic TSOP. FEATURES · 4,194,304-word ´ 4-bit configuration · Single 5V power supply, ±10% tolerance · Input : TTL compatible, low input capacitance · Output : TTL compatible, 3-state · Refresh : 2048 cycles/32 ms · Fast page mode, read modify write capability · CAS before RAS refresh, hidden refresh, RAS-only refresh capability · Multi-bit test mode capability · Package options: 26/24-pin 300mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117405D-xxSJ) 26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5117405D-xxTS-K) (TSOPII26/24-P-300-1.27-L) (Product : MSM5117405D-xxTS-L) xx : indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time Power Dissipation tRAC tAA tCAC tOEA (Min.) Operating (Max.) MSM5117405D-50 50ns 25ns 13ns 13ns 84ns 550mW MSM5117405D-60 60ns 30ns 15ns 15ns 104ns 495mW MSM5117405D-70 70ns 35ns 20ns 20ns 124ns 440mW Standby (Max.) 5.5mW 1/15 MSM5117405D PIN CONFIGRATION (TOP VIEW) 1 2 3 4 5 6 26 25 24 23 22 21 VSS DQ4 DQ3 CAS OE A9 VCC DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS DQ4 DQ3 CAS OE A9 VSS DQ4 DQ3 CAS OE A9 26 25 24 23 22 21 1 2 3 4 5 6 VCC DQ1 DQ2 WE RAS NC A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A8 A7 A6 A5 A4 VSS 19 18 17 16 15 14 8 9 10 11 12 13 A10 A0 A1 A2 A3 VCC VCC DQ1 DQ2 WE RAS NC 26/24-Pin Plastic TSOP (K Type) 26/24-Pin Plastic SOJ Pin Name Function A0 – A10 Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 – DQ4 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5V) VSS Ground (0V) NC No Connection 26/24-Pin Plastic TSOP (L Type) Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 MSM5117405D BLOCK DIAGRAM Timing Generator RAS Timing Generator CAS 11 Column Address Buffers 11 Internal Address Counter A0 – A10 11 Row Address Buffers Refresh Control Clock 11 Row Decoders Word Drivers Column Decoders Sense Amplifiers WE Write Clock Generator 4 I/O Selector OE 4 Output Buffers 4 Input Buffers 4 4 4 DQ1 - DQ4 4 Memory Cells VCC On Chip VBB Generator On Chip IVCC Generator VSS 3/15 MSM5117405D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to VCC + 0.5 V Voltage VCC supply Relative to VSS VCC -0.5 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg -55 to 150 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Notes: Symbol Min. Typ. Max. Unit VCC VSS VIH VIL 4.5 5.0 5.5 V 0 0 0 V 2.4 ¾ VCC + 0.5*1 V ¾ 0.8 V *2 -0.5 *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). Capacitance (VCC = 5V ± 10%, Ta = 25°C, f=1MHz) Parameter Input Capacitance (A0 – A10) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 – DQ4) Symbol Typ. Max. Unit CIN1 ¾ 5 pF CIN2 ¾ 7 pF CI/O ¾ 7 pF 4/15 MSM5117405D DC Characteristics (VCC = 5V ± 10%, Ta = 0°C to 70°C) Parameter Symbol Condition Max Min. Max Min. Max 2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V -10 10 -10 10 -10 10 mA -10 10 -10 10 -10 10 mA ¾ 100 ¾ 90 ¾ 80 mA 1,2 RAS, CAS = VIH ¾ 2 ¾ 2 ¾ 2 RAS, CAS ³ VCC – 0.2V ¾ 1 ¾ 1 ¾ 1 mA 1 ¾ 100 ¾ 90 ¾ 80 mA 1,2 ¾ 5 ¾ 5 ¾ 5 mA 1 ¾ 100 ¾ 90 ¾ 80 mA 1,2 ¾ 100 ¾ 90 ¾ 80 mA 1,3 VOH IOH = -5.0mA Output Low Voltage VOL IOL = 4.2mA 0V £ VI £ 6.5V ; Input Leakage Current ILI Output Leakage Current ILO ICC1 (Operating) Power Supply Current ICC2 (Standby) Average Power Supply Current All other pins not under test = 0V DQ disable 0V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS cycling, ICC3 CAS = VIH, (RAS-only Refresh) tRC = Min. Power Supply Current RAS = VIH, ICC5 (Standby) CAS = VIL, DQ = enable Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Notes: 1. Note Min. Output High Voltage Average Power Supply Current MSM5117405 MSM5117405 MSM5117405 D-50 D-60 D-70 Unit ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/15 MSM5117405D AC Characteristic (1/2) (VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12 MSM5117405 D-50 MSM5117405 D-60 MSM5117405 D-70 Min. Max. Min. Max. Min. Max. tRC 84 ¾ 104 ¾ 124 ¾ ns tRWC 110 ¾ 135 ¾ 160 ¾ ns tPC 20 ¾ 25 ¾ 30 ¾ ns 58 ¾ 68 ¾ 78 ¾ ns ¾ 50 ¾ 60 ¾ 70 ns 4,5,6 tCAC ¾ 13 ¾ 15 ¾ 20 ns 4,5 Access Time from Column Address tAA ¾ 25 ¾ 30 ¾ 35 ns 4,6 Access Time from CAS Precharge tCPA ¾ 30 ¾ 35 ¾ 40 ns 4 Access Time from OE tOEA ¾ 13 ¾ 15 ¾ 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 ¾ 0 ¾ 0 ¾ ns 4 Data Output Hold After CAS Low tDOH 5 ¾ 5 ¾ 5 ¾ ns CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time tCEZ 0 13 0 15 0 20 ns 7,8 tREZ 0 13 0 15 0 20 ns 7,8 tOEZ 0 13 0 15 0 20 ns 7 tWEZ 0 13 0 15 0 20 ns 7 Transition Time tT 1 50 1 50 1 50 ns 3 Refresh Period tREF ¾ 32 ¾ 32 ¾ 32 ms RAS Precharge Time tRP 30 ¾ 40 ¾ 50 ¾ ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 7 ¾ 10 ¾ 13 ¾ ns RAS Hold Time referenced to OE tROH 7 ¾ 10 ¾ 13 ¾ ns CAS Precharge Time (Fast Page Mode) tCP 7 ¾ 10 ¾ 10 ¾ ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time tCSH 35 ¾ 40 ¾ 45 ¾ ns CAS to RAS Precharge Time tCRP 5 ¾ 5 ¾ 5 ¾ ns RAS Hold Time from CAS Precharge tRHCP 30 ¾ 35 ¾ 40 ¾ ns OE Hold Time from CAS (DQ Disable) tCHO 5 ¾ 5 ¾ 5 ¾ ns RAS to CAS Delay Time tRCD 11 37 14 45 14 50 ns 5 RAS to Column Address Delay Time tRAD 9 25 12 30 12 35 ns 6 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Symbol Fast Page Mode Read Modify Write t HPRWC Cycle Time tRAC Access Time from RAS Access Time from CAS Unit Note 6/15 MSM5117405D AC Characteristic (2/2) (VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12 Parameter Symbol MSM517405 D-50 MSM5117405 D-60 MSM5117405 D-70 Min. Max. Min. Max. Min. Max. Unit Note Row Address Set-up Time tASR 0 ¾ 0 ¾ 0 ¾ ns Row Address Hold Time tRAH 7 ¾ 10 ¾ 13 ¾ ns Column Address Set-up Time tASC 0 ¾ 0 ¾ 0 ¾ ns Column Address Hold Time tCAH 7 ¾ 10 ¾ 13 ¾ ns Column Address to RAS Lead Time tRAL 25 ¾ 30 ¾ 35 ¾ ns Read Command Set-up Time tRCS 0 ¾ 0 ¾ 0 ¾ ns Read Command Hold Time tRCH 0 ¾ 0 ¾ 0 ¾ ns 9 Read Command Hold Time referenced to RAS tRRH 0 ¾ 0 ¾ 0 ¾ ns 9 Write Command Set-up Time tWCS 0 ¾ 0 ¾ 0 ¾ ns 10 Write Command Hold Time tWCH 7 ¾ 10 ¾ 13 ¾ ns Write Command Pulse Width tWP 7 ¾ 10 ¾ 10 ¾ ns WE Pulse Width (DQ Disable) tWPE 7 ¾ 10 ¾ 10 ¾ ns OE Command Hold Time tOEH 7 ¾ 10 ¾ 13 ¾ ns OE Precharge Time tOEP 7 ¾ 10 ¾ 10 ¾ ns OE Command Hold Time tOCH 7 ¾ 10 ¾ 10 ¾ ns Write Command to RAS Lead Time tRWL 7 ¾ 10 ¾ 13 ¾ ns Write Command to CAS Lead Time tCWL 7 ¾ 10 ¾ 13 ¾ ns Data-in Set-up Time tDS 0 ¾ 0 ¾ 0 ¾ ns 11 Data-in Hold Time tDH 7 ¾ 10 ¾ 13 ¾ ns 11 OE to Data-in Delay Time tOED 13 ¾ 15 ¾ 20 ¾ ns CAS to WE Delay Time tCWD 30 ¾ 34 ¾ 44 ¾ ns 10 Column Address to WE Delay Time tAWD 42 ¾ 49 ¾ 59 ¾ ns 10 RAS to WE Delay Time tRWD 67 ¾ 79 ¾ 94 ¾ ns 10 CAS Precharge WE Delay Time tCPWD 47 ¾ 54 ¾ 64 ¾ ns 10 tRPC 5 ¾ 5 ¾ 5 ¾ ns tCSR 5 ¾ 5 ¾ 5 ¾ ns tCHR 10 ¾ 10 ¾ 10 ¾ ns tWRP 10 ¾ 10 ¾ 10 ¾ ns tWRH 10 ¾ 10 ¾ 10 ¾ ns RAS to WE Set-up Time (Test Mode) tWTS 10 ¾ 10 ¾ 10 ¾ ns RAS to WE Hold Time (Test Mode) tWTH 10 ¾ 10 ¾ 10 ¾ ns CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) 7/15 MSM5117405D Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max), tREZ (Max), tWEZ (Max), tOEZ (Max) define the time at which the output achived the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS ³ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ³ tCWD (Min.), tRWD ³ tRWD(Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheets is a 2-bit parallel test function, CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/15 MSM5117405D Timing Chart x Read Cycle tRC tRAS VIH RAS VIL tRP tCSH tCRP CAS VIH VIL WE OE VIH VIL tCRP tRSH tCAS tRAD tRAL tASR Address tRCD tRAH tASC Row tCAH Column tRCS tRRH VIH tAA VIL tRCH tROH VIH VIL tCAC tRAC DQ tREZ tAOE tCEZ tOEZ tCLZ VOH VOL Valid Data-out Open “H” or “L” x Write Cycle (Early Write) RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS tRCD VIH tRAD VIL tRAL tASR Address WE OE DQ VIH VIL VIH tCRP tRSH tCAS tRAH tASC Row tCAH Column tCWL tWCS tWP tWCH VIL tRWL VIH VIL VIH VIL tDS Valid Data-in tDH Open “H” or “L” <248 MSM5117405D x Read Modify Write Cycle RAS tRWC tRAS VIH tRP VIL tCSH tCRP CAS VIH VIL VIH VIL tRSH tCAS tCRP tRAD tASR Address tRCD tRAH Row tASC tCWL tRWL tCAH Column tRCS tCWD tWP tRWD WE OE VIH VIL tAWD tAA tOEH tOEA VIH tOED VIL tDH tCAC tRAC DQ VI/OH VI/OL tOEZ tCLZ Valid Data-out tDS Valid Data-in “H” or “L” 43248 MSM5117405D x Fast Page Mode Read Cycle (Part-1) tRASP RAS tRCD VIH VIL tCSH tCRP CAS Address VIH VIL tASR tRAD tRAH tASC Row tRHCP tCP tCP tCAS VIH VIL tRP tHPC tCAH tCAS tASC Column tCAS tASC tCAH Column Column tRCS WE OE tOCH tRRH VIH tAA VIL tCAC tRAC tAA VIH tCHO tOEP tCAC tOEP tOEA tAA VIL tCPA tOEA tCAC DQ tCAH tDOH VOH VOL tOEA tOEZ Valid Data-out Valid Data-out tCLZ tOEZ tREZ Valid * Data-out Valid * Data-out * : Same Dada, x “H” or “L” Fast Page Mode Read Cycle (Part-2) tRASP RAS CAS Address tRCD VIH VIL tCRP tCSH VIH VIL tASR tRAD tRAH tASC Row OE tCAH tRHCP tCAS tCAH tASC Column tRCS WE tCP tCAS VIH VIL tRP tHPC Column tCP tCAS tASC tCAH Column tRCS VIH VIL tAA tRAC VIH tRCH tWPE tOEA tAA tCPA tAA tWEZ tCAC tDOH VIL tCAC tCAC DQ VOH VOL tCLZ Valid * Data-out Valid * Data-out * : Same Dada, tCEZ Valid * Data-out “H” or “L” 44248 MSM5117405D x Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS CAS Address WE OE tCSH VIH VIL tCRP tHPC tRCD tCP VIH VIL tASR tRAD tRAH tASC Row tASC Column tWCS VIH tRSH tCAS tCAS tCAH tASC tCAH Column tWCH tWCS tCAH Column tWCH tWCS tWCH VIL VIH VIL tDS DQ tCP tCAS VIH VIL tHPC VIH tDH tDS tDH Valid * Data-in VIL tDS Valid * Data-in tDH Valid * Data-in “H” or “L” x Fast Page Mode Read Modify Write Cycle tRASP VIH RAS VIL CAS tRWD tCRP tRCD tCP VIH tASC tASC VIL VIH VIL tRAD tRAH Row tHPRWC Column VIH VIL Column OE tAWD tAWD tAA tDS tWP tOED tOEH VIL VI/OH VI/OL tWP tDS tOEA tCAC DQ tCWD tRCS tRAC VIH tCAH tCPA tCWL tCAH tRCS WE tRWL tCWD tASR Address tCPWD tOEZ 9DOLG#'DWD0RXW tCLZ tDH tOED tCAC 9DOLG#'DWD0LQ tOEZ 9DOLG#'DWD0RXW tOEH tDH 9DOLG#'DWD0LQ tCLZ “H” or “L” 45248 MSM5117405D x RAS-Only Refresh Cycle tRC RAS CAS Address tRAS VIH VIL tRP tCRP tRPC VIH VIL tASR tRAH VIH Row VIL tCEZ DQ VOH Open VOL “H” or “L” Note: WE, OE = “H” or “L” x CAS before RAS Refresh Cycle tRP RAS CAS tRC tRAS VIH VIL tRPC tCP tRP tCSR tRPC tCHR VIH VIL tCEZ DQ VOH VOL Open Note: WE, OE, Address = “H” or “L” 46248 MSM5117405D x Hidden Refresh Read Cycle tRC RAS CAS VIH VIL tCRP tRAS tRCD tRSH tCHR tRAD VIL tRAH VIH tASC Row VIL tCAH Column tRCS WE tCAC VIH VIL tRRH tRAL tAA tWRH tROH OE tRP tRP VIH tASR Address tRC tRAS tWRP tOEA VIH VIL tOEZ DQ VOH tRAC Open VOL tCLZ Valid Data-out “H” or “L” x Hidden Refresh Write Cycle tRC RAS CAS VIH VIL tCRP WE tRCD DQ tRSH tRAD VIL VIH VIL tRP tRP tCHR tRAH tASC Row tCAH Column tRAL tRWL tWP VIH VIL tWCS OE tRAS VIH tASR Address tRC tRAS tWCH VIH VIL VIH VIL tDS tDH Valid Data-in “H” or “L” 47248 MSM5117405D CAS before RAS Self-Refresh Cycle tRP RAS tRPS VIH VIL tRCP tCP CAS tPASS tRPC tCSR tCHS VIH VIL tCEZ DQ VOH VOL Open Note: WE, OE, Address = “H” or “L” Only SL Version “H” or “L” 48248