PM7329 S/UNI-APEX-1K800 Released Packet/ATM Traffic Manager and Switch FEATURES via packet-contiguous queuing and scheduling. • Error indication in AAL5 EOM trailer (set by SAR or classifier) can invoke errored packet discard, thereby eliminating need for packet buffers in external devices. • Traffic queuing algorithm is highly configurable on a per connection, per class, and per port basis. • ATM (fixed length cell) and packet/ frame traffic manager and switch. • 128 line ports, 4 WAN ports, and a high speed microprocessor port. Any port to any port switching for 1024 independent connections. • Manages up to 256 Kbyte cell (16 Mbyte) data buffer and 4 Mbyte context memory shared over all ports. • 352-ball SBGA, 35 mm x 35 mm. BUS INTERFACES • 8/16 bit, 52 MHz UTOPIA L2 bus. • Line side: Enhanced UTOPIA Tx master supports 128 ports. Rx master supports 32 ports. • Or single port slave. • WAN side: • • Configurable scheduling of 4 classes of service on every port, with rate shaping available for the 4 WAN ports. Configurable traffic parameters enabling a mix of CBR, VBR, GFR, and UBR classes. • Configurable progressive throttling of buffer consumption, with memory reservation under high consumption. Performs EFCI marking for ABR support. • Buffer congestion controlled via Partial Packet Discard, Early Packet Discard (PPD/EPD). Cell at a time discard also supported. • • • Configurable OAM cell queuing and special handling on all ports. • 66 MHz, 32 bit address/data bus capable of single or burst access to internal registers and cell buffers. • Supports 700 Mb/s ingress traffic and 700 Mb/s egress traffic aggregated across all ports. Supports external wire speed HDLC processor, SAR, and flow classifier Master (with optional cell length expansion) supports 4 Tx or Rx ports. Or single port slave. MICROPROCESSOR INTERFACE • VPI/VCI header mapping. • For frame/packet flows: • • Standard 5-pin P1149 JTAG port. • Supports cell/packet transfer to/from any port, with CRC32 and CRC10 calculation supported in hardware. • Low power 3.3/ 2.5 V CMOS. Loop Rx Any-PHY PMC-2010038 (r3) CMAB[18:17] CMCEB CMRWB CMA[18:0] Que Management & Scheduling WAN Rx Any-PHY TCK Loop Tx Any-PHY LTCLK LTPA LTSX LTSOP LTDAT[15:0] LTPRTY LTENB LTADR[7:0] WAN Tx Any-PHY WTCLK WTPA WTSX WTSOP WTDAT[15:0] WTPRTY WTENB WTADR[2:0] TRSTB TDI TDO CBDQ[31:0] CBDQM[1:0] CBA[11:0] CBBS[1:0] CBRWEB CBCASB CBCSB CBRASB TMS JTAG Test Access Port SDRAM Interface OE WRCLK WRPA WRSX WRSOP WRDAT[15:0] WRPRTY WRENB WRADR[2:0] SSRAM Interface SYSCLK LRCLK LRPA LRSX LRSOP LRDAT[15:0] LRPRTY LRENB LRADR[5:0] Processor Interface RSTB Ctrl Lines AD[31:0] CMP[1:0] CMD[33:0] BLOCK DIAGRAM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2001 Released PM7329 S/UNI-APEX-1K800 Packet/ATM Traffic Manager and Switch CONGESTION CONTROL • Traffic discard thresholds configurable per connection (independent CLP0 and CLP1 thresholds), per class, per port, and per direction. • Guaranteed Frame Rate (GFR) implemented via CLP0 minimum buffer size reservation per connection. • Each port’s queuing and scheduling is configurable as cell at a time or packet at a time. ACCOUNTING • Connections are scheduled into each class queue using configurable weighted fair queuing (cell mode), or FIFO (frame mode). • Error statistics accumulation. • Classes are scheduled into ports using strict priority with configurable minimum bandwidth reservation. QUEUING & SCHEDULING • 1024 traffic staging queues (one per connection) individually assignable to any CoS on any port. • Ports are scheduled onto their corresponding bus using a configurable weighted interleaved round robin algorithm. • 512 + 20 scheduling queues: 4 CoS queues per port, 128 line ports, 4 WAN ports, and 1 processor port. • On the WAN ports: rate shaping, individually configured per connection, within four classes. • Per connection CLP0/CLP1 upstream/ downstream Tx counts. • CLP0/CLP1 cell discard counts with indication of connection ID of last cell discarded. APPLICATIONS • Mini Digital Subscriber Loop Access Multiplexer (mini-DSLAM). • Subscriber Access equipment. • Digital Loop Card traffic aggregation. TYPICAL APPLICATION S/UNI-APEX-1K800 IN OC3 MINI-DSLAM APPLICATION Any-PHY/ SCI-PHY line cards DSL PHY up to 31 Utopia L2 ports PM7350 S/UNIDUPLEX DSL PHY line cards DSL PHY up to 31 Utopia L2 ports PM7350 S/UNIDUPLEX DSL PHY PM7351 S/UNIVORTEX 200 Mbit/s LVDS PM7328 S/UNIATLAS1K800 PM7329 S/UNI-APEX1K800 I- EX UN RT S/ O o I-V t ks UN lin S/ S er D p LV s 8 ice to dev Up X E PL DU Context SSRAM PHY Ingress SSRAM Packet/Cell SDRAM Host CPU Egress SSRAM Core Card S/UNI-APEX-1K800 IN OC3 DIGITAL LOOP CARD APPLICATION line interface Any-PHY/ SCI-PHY Bus DSL PHY PM7329 S/UNI-APEX1K800 DSL PHY expansion DSL PHY Context SSRAM Packet/Cell SDRAM PM7328 S/UNI-ATLAS1K800 Ingress SSRAM PHY Host CPU Egress SSRAM Digital Loop Card Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PMC-2010038 (r3) © Copyright PMC-Sierra, Inc. 2001. All rights reserved. June 2001 S/UNI is a registered trademark of PMC-Sierra, Inc. Any-PHY and SCI-PHY are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE