CXP854P60 CMOS 8-bit Single-chip Microcomputer Description The CXP854P60 are a highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM generator, remote control receiver, HSYNC counter, and watchdog timer. Also, the CXP854P60 provides power-on reset and sleep functions. The designers have ensured low power consumption for these powerful microcomputers. Incorporating a one-time PROM, the CXP854P60 has an equivalent function to the CXP85460 and character ROM for OSD can be written. Therefore, it is suitable for evaluation in system development and for the production of small amounts. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • Instruction set which supports a wide array of data types-213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean operations. • Minimum instruction cycle 0.5µs/8MHz • On-chip PROM 60K bytes (For program) 10K bytes (For OSD) • On-chip RAM 960 bytes • On-screen display function 12 × 18 dots, 384 types, 12lines of 32 characters Black frame output, half blanking, shadow, background color on full screen Double scanning mode supported includes jitter elimination circuit 2 • I C bus interface • 14-bit PWM output, 8-bit PWM output (8 channels) • Remote control receiver circuit • 8-bit A/D converter (4 channels, 20µs conversion time/4MHz, 8MHz) • HSYNC counter (2channels) • Watchdog timer • 8-bit synchronized serial I/O • 8-bit timer, 8-bit timer/counter, 19-bit time-base timer • General purpose input/output 32-line I/O (bit-selectable input/output), also 6-line input, 10-line output (internal 8-line Nch-O/D) • Interrupts 13 factors, 13 vectors, multiple interrupt possible • Standby mode SLEEP • Package 64-pin plastic SDIP/QFP Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95109-ST HSYNC COUNTER 0 HSYNC COUNTER 1 A/D CONVERTER I2C INTERFACE UNIT PD5/HS1 PE2/AN0 to PE5/AN3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 FIFO PD4/HS0 REMOCON TIMER/COUNTER PD7/EC PE7/TO PD6/RMC SERIAL I/O PD3/SI PD2/SO PD1/SCK ON SCREEN DISPLAY 2 2 PE1/INT1 INTERRUPT CONTROLLER PD0/INT2 PE0/INT0 14BIT PWM WATCH DOG TIMER PE6/PWM XLC EXLC R G B I YS YM PA7/HSYNC PA6/VSYNC 8 BIT PWM 8CH PROM 60K SPC700 CPU CORE PF0/PWM0 to PF7/PWM7 Vpp VSS MP VDD XTAL RST EXTAL PRESCALER/ TIME BASE TIMER RAM 960 BYTES CLOCK GEN./ SYSTEM CONTROL PF0 to PF7 PE6 to PE7 PE0 to PE5 PD0 to PD7 PC0 to PC7 PA0 to PA7 PB0 to PB7 PORT A PORT B PORT C PORT D PORT E –2– PORT F Block Diagram CXP854P60 CXP854P60 56 55 54 53 HSYNC/PA7 1 64 VDD VSYNC/PA6 2 63 Vpp PA5 3 62 VSS PA4 4 61 MP PA3 5 60 PF0/PWM0 PA2 6 59 PF1/PWM1 PA1 7 58 PF2/PWM2 PA0 8 57 PF3/PWM3 PB7 9 56 PF4/PWM4/SCL0 PB6 10 55 PF5/PWM5/SCL1 PB5 11 54 PF6/PWM6/SDA0 PB4 12 53 PF7/PWM7/SDA1 PB3 13 52 YM PB2 14 51 YS PB1 15 50 I PB0 16 49 B PC7 17 48 G PC6 18 47 R PC5 19 46 EXLC PC4 20 45 XLC PC3 21 44 PE0/INT0 PC2 22 43 PE1/INT1 PC1 23 42 PE2/AN0 PC0 24 41 PE3/AN1 EC/PD7 25 40 PE4/AN2 RMC/PD6 26 39 PE5/AN3 HS1/PD5 27 38 PE6/PWM HS0/PD4 28 37 PE7/TO SI/PD3 29 36 RST SO/PD2 30 35 EXTAL SCK/PD1 31 34 XTAL VSS 32 33 PD0/INT2 PF2/PWM2 57 PF0/PWM0 58 PF1/PWM1 59 MP 60 VDD VSS 61 Vpp PA7/HSYNC 62 PA5 63 PA6/VSYNC PA3 64 PA4 PA2 Pin Assignment (Top View) Note) 1. Vpp pin 63 must be connected to VDD. 2. Vss pins 32 and 62 must have a common GND. 3. MP pin 61 must be connected to GND. 52 PA1 1 51 PA0 2 50 PF4/PWM4/SCL0 PB7 3 49 PF5/PWM5/SCL1 PB6 4 48 PF6/PWM6/SDA0 PB5 5 47 PF7/PWM7/SDA1 PB4 6 46 YM 45 YS 44 I PF3/PWM3 12 40 EXLC PC5 13 39 XLC PC4 14 38 PE0/INT0 PC3 15 37 PE1/INT1 PC2 16 36 PE2/AN0 PC1 17 35 PE3/AN1 PC0 18 34 PE4/AN2 EC/PD7 19 33 PE5/AN3 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM/PE6 R PC6 TO/PE7 41 RST 11 EXTAL G PC7 XTAL 42 INT2/PD0 10 VSS B PB0 SCK/PD1 43 SI/PD3 9 SO/PD2 PB1 HS0/PD4 8 HS1/PD5 7 PB2 RMC/PD6 PB3 Note) 1. Vpp pin 56 must be connected to VDD. 2. Vss pins 26 and 58 must have a common GND. 3. MP pin 55 must be connected to GND. –3– CXP854P60 Pin Functions Pin Name I/O Function PA0 to PA5 I/O PA6/VSYNC I/O/Input (Port A) Single bit selectable 8-bit port. (8 lines) CRT display vertical synchronization signal input pin. PA7/HSYNC I/O/Input CRT display horizontal synchronization signal input pin. PB0 to PB7 I/O (Port B) Single bit selectable 8-bit port. (8 lines) PC0 to PC7 I/O (Port C) Single bit selectable 8-bit port. (8 lines) PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HS0 I/O/Input PD5/HS1 I/O/Input PD6/RMC I/O/Input Remote control receiver circuit input pin. PD7/EC I/O/Input External event timer/counter input pin. PE0/INT0 PE1/INT1 Input/Input Input pin for external interrupt request. Active falling edge. (2 lines) Input pin for external interrupt request. Active on falling edge. Serial clock pin. (Port D) Single bit selectable Serial data output pin. 8-bit port. Serial data input pin. 12mA sink current drive possible. HSYNC counter (CH0) input pin. (8 lines) HSYNC counter (CH1) input pin. (Port E) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 lines) PE2/AN0 to PE5/AN3 Input/Input PE6/PWM Output/Output PE7/TO Output/Output PF0/PWM0 to PF3/PWM3 Output/Output PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 Output/Output/ I/O PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Output/Output/ I/O (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits middle voltage tolerance (12V), upper 4 bits 5V suppression. (8 lines) R, G, B, I, YS, YM Output CRT display 6-bit output pin. Analog input pin for A/D converter. (4 lines) 14-bit PWM output pin. (CMOS output) Square wave output for timer 1. (50% duty cycle) –4– 8-bit PWM output pin. (8-lines) I2C bus interface transfer clock I/O pin. I2C bus interface transfer data I/O pin. CXP854P60 Pin Name I/O Function EXLC Input XLC Output EXTAL Input XTAL Output RST I/O "L" level active system reset. This pin also acts as an I/O pin during power up. While internal power-on reset function is talking place a "L" level is output. MP Input Test mode input pin. Must be connected to GND. CRT display clock oscillator I/O pin. Oscillator frequency is determined external L, C circuit. System clock oscillator crystal connection pin. When using an external clock, input to EXTAL pin and leave XTAL pin open. Vpp Positive power supply pin for incorporated PROM writing. Under normal operating conditions, connect to VDD. VDD Positive supply voltage pin. Vss GND. Both Vss pins should be connected to common GND. –5– CXP854P60 Pin Equivalent I/O Circuit Pin Circuit format Port A Port B Port C PA0 to PA5 PB0 to PB7 PC0 to PC7 AAAA AAAA AAAA AAAA When reset AA AA AA AA Port A data Port B data Port C data Port A direction Port B direction Port C direction Data bus IP RD (Port A, B, C) 22 lines Port A AAAA AAAA AAAA Port A direction PA6/VSYNC PA7/HSYNC Input protection circuit AA AA AA AA Port A data IP Data bus RD (Port A) Hi-Z Input protection circuit AAAA AAAA AAAA AAAA AA AAAA AA AA AA Hi-Z VSYNC HSYNC Schmitt input Input multiplexer 2 lines Port D PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 Port D data Port D direction Large current source 12mA PD6/RMC PD7/EC Data bus IP RD (Port D) INT2, SI, HS0, HS1, RMC, EC Schmitt input 6 lines –6– Hi-Z CXP854P60 Pin Circuit format When reset Port D SCK or SO Output enable AAAA AAAA PD1/SCK PD2/SO AA AA AA AA Large current source 12mA Port D data IP Port D direction Schmitt input Data bus Hi-Z RD (Port D) SCK only 2 lines Port E PE0/INT0 PE1/INT1 AAAA Schmitt input (To interrupt circuit) IP 2 lines Hi-Z Data bus RD (Port E) Port E AAAA AA Input multiplexer PE2/AN0 to PE5/AN3 IP To A/D converter Hi-Z Data bus RD (Port E) 4 lines Port E TO, PWM PE6/PWM PE7/TO AAAA AAAA A Port E data Port E selection 2 lines –7– H level CXP854P60 Circuit format Pin When reset Port F PF0/PWM0 to PF3/PWM3 AAAA AAAA AAAA AA AA PWM 12V voltage torelance Port F data Large current source 12mA Port F selection 4 lines Port F SCL, SDA PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 AA AA PWM Port F data R G B I YS YM 6 lines EXLC XLC 2 lines Hi-Z IP Port F selection Schmitt input SCL, SDA (To I2C circuit) 4 lines AA Large current source 12mA I2C output enable AAAA AAAA AAAA BUS SW To other I2C pins AAAA AAAA AA AA R, G, B, I, YS, YM Output polarity To output polarity register Writing data to port register brings output from high impedance to active AA AA AA AA AA A AA A EXLC Hi-Z IP IP XLC –8– Hi-Z Oscillator control Oscillation halted CRT display clock CXP854P60 Pin EXTAL XTAL Circuit format EXTAL XTAL 2 lines AA AA AA AA AA AA AA AA When reset • Diagram indicates equivalent circuit during oscillation IP • Feedback resistor is disconnected during STOP Oscillation Pull-up resistor RST 1 line –9– Schmitt input L level From power-on reset circuit CXP854P60 Absolute Maximum Ratings (Vss = 0V) Item Symbol Supply voltage Ratings Unit VDD –0.3 to +7.0 V Vpp V Remarks Input voltage VIN –0.3 to +13.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium voltage tolerance output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Excludes large current output Large current output∗2 Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP 600 mW QFP Low level output current Incorporated PROM V Pins PF0 to PF3 ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current driver for the PD and PF ports is a N-ch transistor. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol VDD Supply voltage Min. Max. Unit 4.5 5.5 V Safe operating range 3.5 5.5 V Safe operating range for low speed data∗1 2.5 5.5 V Vpp = VDD Vpp High level input voltage Low level input voltage Operating temperature (Vss =0V) V Remarks Safe operating range for data retention during STOP ∗5 VIH 0.7VDD VDD V VIHS 0.8VDD VDD V I2C Schmitt input included∗2 CMOS Schmitt input∗3 VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗4 VIL 0 0.3VDD V VILS 0 0.2VDD V I2C Schmitt input included∗2 CMOS Schmitt input∗3 VILEX –0.3 0.4 V EXTAL pin∗4 Topr –10 +75 °C ∗1 Rating for 1/16 frequency mode and sleep mode. ∗2 Normal input port (All pins PA, PB, PC, PE2 to PE5), PF4 to PF7 pins. ∗3 Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HS0, PD5/HS1, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1, HSYNC, VSYNC, RST pins. ∗4 Rating applies to external clock input only. ∗5 Vpp and VDD should be set to a same voltage. – 10 – CXP854P60 DC Characteristics Item High level output voltage Low level output voltage (Ta = –10 to +75°C, Vss = 0V) Symbol VOH VOL IIHE Input current Pin Condition PA to PD, PE6, PE7, VDD = 4.5V, IOH = –0.5mA R, G, B, I, YS, YM VDD = 4.5V, IOH = –1.2mA Min. Typ. Max. Unit 4.0 V 3.5 V PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, I, YS, YM, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, RST 0.4 V 0.6 V PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL IIHL VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leak current (N-ch Tr off case) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA I2C bus switch connection impedance (Output Tr off case) RBS SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω Operating mode (1/2, clock rate) 8MHz crystal oscillator (C1 = C2 = 22pF) All output pins open 20 35 mA IDDSL SLEEP mode 1.0 3 mA IDDST STOP mode∗2 — — µA 10 20 pF IDD VDD∗1 Supply current Input capacitance CIN Pins other than VDD and Vss 1MHz clock 0V for non-measurement pins ∗1 Rating applies only if OSD oscillator is halted. ∗2 This device does not enter in the stop mode. – 11 – — CXP854P60 AC Characteristics (1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item System Pin Condition Min. Max. Unit 9 MHz System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 3.5 System clock input pulse width tXL, tXH EXTAL Fig. 1, Fig. 2 External clock drive 50 System clock rise and fall times tCR, tCF tEH, tEL tER, tEF EXTAL Fig 1, Fig 2 External clock drive EC Fig. 3 EC Fig. 3 Event counter input clock pulse widtth Event counter input clock rise and fall times ns 200 tsys + 50∗ ns ns 20 ms ∗ tsys indicates one of three values according to the contents of the clock control register. (For CPU clock selection.) tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF Fig. 2. Clock applied condition AAAA AAAA AAAA External clock EXTAL XTAL C1 tCR AAAA AAAA AAAA Crystal oscillator Ceramic oscillator EXTAL tXL C2 XTAL OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF – 12 – tEL tER CXP854P60 (2) Serial transfer Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) System Pin tKCY SCK SCK high and low level widths tKH tKL SCK SI input set-up time (referenced to SCK ↑) tSIK SI SI input hold time (referenced to SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Condition Min. Input mode Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) For SCK output mode, in addition to output delay time SO capacitance must be 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tKSI tSIK 0.8VDD Input data SI Unit 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD – 13 – CXP854P60 (3) Interrupt, Reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol tIH tIL tRSL External interrupt high and low level widths Reset input low level width Pin Condition Min. INT0 to INT2 RST Max. Unit 1 µs 8/fc µs Fig. 5. Interrupt input timing tIH tIL 0.8VDD INT0 to INT2 (falling edge) 0.2VDD Fig. 6. RST input timing tRSL RST 0.2VDD (4) Power-on reset Power on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Power supply rise time Power supply cutt-off time tR tOFF Pin VDD Condition Power-on reset Repeated power-on reset Min. Max. Unit 0.05 50 ms 1 ms Fig. 7. Power-on reset 4.5V VDD 0.2V 0.2V tR tOFF Take care when turning on power. – 14 – CXP854P60 (5) A/D converter characteristics Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Max. Unit Resolution 8 Bits Linearity error ±1 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pin Condition Min. Ta = 25°C VDD = 5.0V Vss = 0V Typ. –10 10 70 mV 4910 4970 5030 mV 160/fADC∗3 12/fADC∗3 AN0 to AN3 0 µs µs VDD V Fig. 8. Definitions for A/D converter terms Digital conversion value FFH FEH ∗1 VZT: Digital conversion values change between 00H←→01H. ∗2 VFT: Digital conversion values change between 0EH←→0FH. ∗3 fADC indicates the below values due to the bit6 (CKS) of A/D control registor (address: 00F6H) and the Bit 7 (PCK1) and Bit 6 (PCK0) of clock control registor (address: 00FEH) Linearity error 01H 00H CKS VZT VFT Analog input PCK1, 0 0 (φ/2 selection) 1 (φ/2 selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 – 15 – CXP854P60 (6) I2C bus timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Item Pin Condition Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗ SDA, SCL 0.25 µs Hold time for starting transfer Clock low level width Clock high level width Set-up time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion µs SDA, SCL 1 µs SDA, SCL 0.3 µs SDA, SCL 4.7 µs ∗ Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns. Fig. 9. I2C bus transfer data timing SDA tBUF tR tF tHD; STA SCL tHD; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STA tSU; STO P Fig. 10. I2C device suggested circuit I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 16 – CXP854P60 (7) OSD (On Screen Display) timing Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condiiton Shadow Existent Shadow Non-existent Min. Max. Min. Max. 7∗1 14∗2 4 11∗1 16∗2 Unit OSD clock frequency fOSC EXLC XLC Fig. 12 4 HSYNC pulse width tHWD HSYNC Fig. 11 1.2 HSYNC afterwrite rise and fall times tHCG HSYNC Fig. 11 200 200 ns VSYNC afterwrite rise and fall times tVCG VSYNC Fig. 11 1.0 1.0 µs 1.2 ∗1 Oscillator clock at 4MHz operation ∗2 Oscillator clock at 8MHz operation Fig. 11. OSD timing tHCG tHWD 0.8VDD HSYNC For OPOL register (01FAH) bit 7 at “0” 0.2VDD tVCG 0.8VDD VSYNC For OPOL register (01FAH) bit 6 at “0” 0.2VDD Fig. 12. LC oscillator circuit connection EXLC XLC L C2 C1 – 17 – MHz µs CXP854P60 Supplement Fig. 13. SPC700 Series recommended oscillation circuit AAAA AAAA AAAA AAAA AAAA AAAA (i) EXTAL (ii) EXTAL XTAL Rd Rd C2 C1 XTAL C1 C2 Manufacturer MURATA MFG CO., LTD. Model fc (MHz) CSA4.00MG 4.00 CSA4.19MG 4.19 CSA8.00MTZ 8.00 CST4.00MGW∗ CST4.19MGW∗ CST8.00MTW∗ C1 (pF) C2 (pF) Rd (Ω) Circuit Example (i) 30 30 0 4.00 (ii) 4.19 8.00 4.00 RIVER ELETEC CO., LTD. HC-49/U03 4.19 12 12 0 (i) 27 27 0 (i) 8.00 4.00 KINSEKI LTD. HC-49/U(-S) 4.19 8.00 ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Product List Option item Mask product CXP854P60S-1CXP854P60Q-1- Package 64-pin plastic SDIP/QFP 64-pin plastic SDIP/QFP Program ROM capacitance 52K/60K byte PROM 60K byte Reset pin pull-up resistor Existent/Non-existent Existent Power-on reset circuit Existent/Non-existent Existent User specified User specified (PROM)∗ Font data ∗ The font data for the one-time PROM version is operated in the same way as the program writing. – 18 – CXP854P60 Fig. 14. Characteristics curves IDD vs. VDD IDD vs. fc (fc = 8MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 20 1/2 frequency mode 1/4 frequency mode 18 10 1/2 frequency mode SLEEP mode 1 IDD – Supply current [mA] 14 12 10 1/4 frequency mode 8 6 0.1 2 3 4 5 6 4 1/16 frequency mode VDD – Supply voltage [V] 2 SLEEP mode 0 1 5 10 fc – System clock [MHz] Parameter Curve for OSD Oscillator L vs. C (Analytically calculated value) 100 5.0MHz L – Inductance [µH] IDD – Supply current [mA] 16 1/16 frequency mode 6.5MHz 10 13.0MHz fOSC = 1 2π√ LC C = C1 // C2 0 50 C1, C2 – Capacitance [pF] – 19 – 100 CXP854P60 Package Outline Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) 750mil + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND EPOXY / PHENOL RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 0.8 ± 0.2 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP–64P–L01 LEAD TREATMENT EIAJ CODE ∗ QFP064–P–1420 LEAD MATERIAL SOLDER/PALLADIUM PLATING COPPER /42 ALLOY PACKAGE WEIGHT 1.5g JEDEC CODE – 20 –