CXP971000 CMOS 16-bit Single Chip Microcomputer Description The CXP971000 is a CMOS 16-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP972032/973032/973064. Piggy/ evaluation type 100 pin PQFP (Ceramic) Features (LQFP supported) (QFP supported) • An efficient instruction set as a controller – Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS – Highly quadratic instruction system, general-purpose register of eight 16-bit × 16-bank configuration • Minimum instruction cycle time 50ns at 40MHz operation (2.7 to 3.6V) • Incorporated EPROM CXP27V1000K • Incorporated RAM capacity 23.5K bytes • Peripheral functions — A/D converter 8-bit 12-analog input, successive approximation system, 3-stage FIFO (Conversion time: 1.55µs at 40MHz) — Serial interface Asynchronous serial interface (UART) 128-byte buffer RAM, 3 channels — I2C bus interface 64-byte buffer RAM (supports master/slave and automatic transfer mode) — Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels, watchdog timer — PWM output circuit 14-bit PWM, 4 channels (2-channel of binary output switch function by PPG) — Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel — Remote control receive circuit 8-bit pulse measurement counter, 10-stage FIFO — Parallel interface External register interface (8-bit parallel bus), 4-chip select • Interruption 33 factors, 33 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin Ceramic PQFP • Mask ROM CXP972032/973032/973064 • FLASH EEPROM incorporated type CXP973F064 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00423A08-PS CXP971000 PH1/SCL PH2/RxD PH3/TxD PH4/RMC PH5 PH6/XWR PH7/XRD NC VDD VSS PA0/A0 PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PB0/PPO00/A8 PB1/PPO01/A9 Pin Assignment in Piggyback Mode (Top View) 100-pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2/PPO02/A10 1 80 PH0/SDA PB3/PPO03/A11 2 79 PK6 PB4/PPO04/A12 3 78 PK5 PB5/PPO05/A13 4 77 PK4/ADTRG PB6/PPO06/A14 5 76 PK3/ADTEN PB7/PPO07/A15 6 75 PK2 PC0/PPO08 7 74 PK1 PC1/PPO09 8 73 PK0 72 AVDD A10 1 24 VDD A23 25 48 VDD 71 AVREF 11 A9 2 23 A11 A22 26 47 CE 70 AVSS PC5/PPO13/XCS2 12 A8 3 22 A12 A21 27 46 NC 69 PJ7/AN11/KS11 PC6/PPO14/XCS1 13 A7 4 21 D7 A20 28 45 D15 68 PJ6/AN10/KS10 14 A6 5 20 D6 A19 29 44 D14 67 PJ5/AN9/KS9 6 19 D5 43 PC2/PPO10 9 PC3/PPO11 10 PC4/PPO12/XCS3 PC7/PPO15/XCS0 VSS 15 A5 A18 30 D13 66 PJ4/AN8/KS8 PD0/D0/KS12 16 A4 7 18 D4 A17 31 42 D12 65 PJ3/AN7/KS7 PD1/D1/KS13 17 A3 8 17 D3 A16 32 41 D11 64 PJ2/AN6/KS6 PD2/D2/KS14 18 A2 9 16 D2 A15 33 40 D10 63 PJ1/AN5/KS5 PD3/D3/KS15 19 A1 10 15 D1 A14 34 39 D9 62 PJ0/AN4/KS4 PD4/D4/KS16 20 A0 11 14 D0 A13 35 38 D8 61 PI7/AN3/KS3 PD5/D5/KS17 21 Vss 12 13 Vss Vss 36 37 Vss 60 PI6/AN2/KS2 PD6/D6/KS18 22 59 PI5/AN1/KS1 PD7/D7/KS19 23 58 PI4/AN0/KS0 PE0/INT0 24 57 Vss PE1/INT1 25 56 PI3/SCK2 PE2/INT2 26 55 PI2/SO2 PE3/INT3 27 54 PI1/SI2 PE4/INT4 28 53 PI0/SCS2 PE5/INT5 29 52 PG7/SCK0 PE6/INT6 30 51 PG6/SO0 PG5/SI0 PG4/SCS0 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 VDD XTAL EXTAL VSS RST PF7/T2 PF6/T1 PF4/SO1 PF5/SCK1 PF3/SI1 PF2/SCS1/NMI PF1/EC2 PF0/EC0 PE7/INT7/CINT 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND. 3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. –2– CXP971000 PH1/SCL PH2/RxD PH3/TxD PH4/RMC PH5 PH6/XWR PH7/XRD NC VDD VSS PA0/A0 PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PB0/PPO00/A8 PB1/PPO01/A9 Pin Assignment in Evaluator Mode (Top View) 100-pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2/PPO02/A10 1 80 PH0/SDA PB3/PPO03/A11 2 79 PK6 PB4/PPO04/A12 3 78 PK5 PB5/PPO05/A13 4 77 PK4/ADTRG PB6/PPO06/A14 5 76 PK3/ADTEN PB7/PPO07/A15 6 75 PK2 PC0/PPO08 7 74 PK1 PC1/PPO09 8 73 PK0 PC2/PPO10 9 72 AVDD PC3/PPO11 10 PC4/PPO12/XCS3 AD10 1 24 VDD A23 25 48 VDD 71 AVREF 11 AD9 2 23 AD11 A22 26 47 E/P 70 AVSS PC5/PPO13/XCS2 12 AD8 3 22 AD12 A21 27 46 ST0 69 PJ7/AN11/KS11 PC6/PPO14/XCS1 13 AD7 4 21 I/T A20 28 45 ST1 68 PJ6/AN10/KS10 PC7/PPO15/XCS0 14 AD6 5 20 MON A19 29 44 ST2 67 PJ5/AN9/KS9 VSS 15 AD5 6 19 ERST A18 30 43 ST3 66 PJ4/AN8/KS8 PD0/D0/KS12 16 AD4 7 18 C1 A17 31 42 WTACK 65 PJ3/AN7/KS7 PD1/D1/KS13 17 AD3 8 17 C2 A16 32 41 JRQH 64 PJ2/AN6/KS6 PD2/D2/KS14 18 AD2 9 16 QS0 AD15 33 40 JRQL 63 PJ1/AN5/KS5 PD3/D3/KS15 19 AD1 10 15 QS1 AD14 34 39 ENMI 62 PJ0/AN4/KS4 PD4/D4/KS16 20 AD0 11 14 QS2 AD13 35 38 MS 61 PI7/AN3/KS3 PD5/D5/KS17 21 Vss 13 Vss 37 Vss 60 PI6/AN2/KS2 PD6/D6/KS18 22 59 PI5/AN1/KS1 PD7/D7/KS19 23 58 PI4/AN0/KS0 PE0/INT0 24 57 Vss PE1/INT1 25 56 PI3/SCK2 PE2/INT2 26 55 PI2/SO2 PE3/INT3 27 54 PI1/SI2 PE4/INT4 28 53 PI0/SCS2 PE5/INT5 29 52 PG7/SCK0 PE6/INT6 30 51 PG6/SO0 12 Vss 36 PG5/SI0 PG4/SCS0 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 VDD EXTAL VSS XTAL RST PF7/T2 PF6/T1 PF5/SCK1 PF3/SI1 PF4/SO1 PF2/SCS1/NMI PF1/EC2 PF0/EC0 PE7/INT7/CINT 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND. 3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. –3– CXP971000 PK5 PK6 PH0/SDA PH1/SCL PH2/RxD PH3/TxD PH4/RMC PH5 PH6/XWR PH7/XRD NC VDD VSS PA0/A0 PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PB0/PPO00/A8 PB1/PPO01/A9 PB2/PPO02/A10 PB3/PPO03/A11 Pin Assignment in Piggyback Mode (Top View) 100-pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB4/PPO04/A12 1 75 PK4 PB5/PPO05/A13 2 74 PK3 PB6/PPO06/A14 3 73 PK2 PB7/PPO07/A15 4 72 PK1 PC0/PPO08 5 71 PK0 PC1/PPO09 6 70 AVD PC2/PPO10 7 69 AVR PC3/PPO11 8 68 AVS PC4/PPO12/XCS3 9 67 PJ7 PC5/PPO13/XCS2 10 66 PJ6 PC6/PPO14/XCS1 11 65 PJ5 64 PJ4 63 PJ3 62 PJ2 61 PJ1 60 PJ0 59 PI7/ 58 PI6/ 57 PI5/ PC7/PPO15/XCS0 12 VSS 13 PD0/D0/KS12 14 PD1/D1/KS13 15 PD2/D2/KS14 A10 1 A9 2 A8 16 VDD 24 A11 23 3 A23 A22 A12 22 25 VDD 48 26 CE 47 A21 27 46 NC A7 4 21 D7 A20 28 45 D15 A6 5 20 D6 A19 29 44 D14 A5 6 19 D5 A18 30 43 D13 A4 7 18 D4 A17 31 42 D12 A3 8 17 D3 A16 32 41 D11 A2 9 16 D2 A15 33 40 D10 A1 10 15 D1 A14 34 39 D9 A0 11 14 D0 A13 35 38 D8 Vss 12 13 Vss Vss 36 37 Vss PD3/D3/KS15 17 PD4/D4/KS16 18 PD5/D5/KS17 19 PD6/D6/KS18 20 56 PI4/ PD7/D7/KS19 21 55 Vss PE0/INT0 22 54 PI3/ PE1/INT1 23 53 PI2/ PE2/INT2 24 52 PI1/ PE3/INT3 25 51 PI0/ PG7/SCK0 PG6/SO0 PG5/SI0 PG4/SCS0 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 VDD EXTAL XTAL VSS RST PF7/T2 PF6/T1 PF5/SCK1 PF4/SO1 PF3/SI1 PF2/SCS1/NMI PF1/EC2 PF0/EC0 PE7/INT7/CINT PE6/INT6 PE5/INT5 PE4/INT4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND. 3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. –4– CXP971000 PK5 PK6 PH0/SDA PH1/SCL PH2/RxD PH3/TxD PH4/RMC PH5 PH6/XWR PH7/XRD NC VDD VSS PA0/A0 PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PB0/PPO00/A8 PB1/PPO01/A9 PB2/PPO02/A10 PB3/PPO03/A11 Pin Assignment in Evaluator Mode (Top View) 100-pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB4/PPO04/A12 1 75 PK4 PB5/PPO05/A13 2 74 PK3 PB6/PPO06/A14 3 73 PK2 PB7/PPO07/A15 4 72 PK1 PC0/PPO08 5 71 PK0 PC1/PPO09 6 70 AVD PC2/PPO10 7 69 AVR PC3/PPO11 8 68 AVS PC4/PPO12/XCS3 9 67 PJ7 PC5/PPO13/XCS2 10 66 PJ6 PC6/PPO14/XCS1 11 PC7/PPO15/XCS0 12 VSS 13 PD0/D0/KS12 14 PD1/D1/KS13 15 PD2/D2/KS14 AD10 1 AD9 2 AD8 16 VDD 24 AD11 23 3 A23 A22 AD12 22 25 VDD 48 26 E/P 47 A21 27 46 ST0 AD7 4 21 I/T A20 28 45 ST1 AD6 5 20 MON A19 29 44 ST2 AD5 6 19 ERST A18 30 43 ST3 AD4 7 18 C1 A17 31 42 WTACK AD3 8 17 C2 A16 32 41 JRQH AD2 9 16 QS0 AD15 33 40 JRQL AD1 10 15 QS1 AD14 34 39 ENMI AD0 11 14 QS2 AD13 35 38 MS Vss 12 13 Vss Vss 36 37 Vss 65 PJ5 64 PJ4 63 PJ3 62 PJ2 61 PJ1 60 PJ0 59 PI7/ 58 PI6/ 57 PI5/ PD3/D3/KS15 17 PD4/D4/KS16 18 PD5/D5/KS17 19 PD6/D6/KS18 20 56 PI4/ PD7/D7/KS19 21 55 Vss PE0/INT0 22 54 PI3/ PE1/INT1 23 53 PI2/ PE2/INT2 24 52 PI1/ PE3/INT3 25 51 PI0/ PG6/SO0 Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND. 3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. –5– PG7/SCK0 PG5/SI0 PG4/SCS0 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 VDD EXTAL XTAL VSS RST PF7/T2 PF6/T1 PF5/SCK1 PF4/SO1 PF3/SI1 PF2/SCS1/NMI PF1/EC2 PF0/EC0 PE7/INT7/CINT PE6/INT6 PE5/INT5 PE4/INT4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP971000 EPROM Read Timing (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V) Item Symbol Pins Address → data Input delay time tACC A0 to A23 D0 to D15 Address → data hold time tIH A0 to A23 D0 to D15 Min. Max. Unit 50 ns 0 ns 0.8VDD A0 to A23 Address data 0.2VDD tACC tIH 0.8VDD D0 to D15 Input data 0.2VDD Product List Type Product name Package ROM capacity Reset pin pull-up resistor Piggy/evaluation chip CXP971000-U01Q CXP971000-U01R 100-pin ceramic PQFP (QFP supported) 100-pin ceramic PQFP (LQFP supported) EPROM 512K bytes Existent –6– CXP971000 Switching of Piggyback Mode and Evaluator Mode Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting to the connector of top of the chip. Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip. Piggyback mode Pin 1 marking 0 For lower bytes 1 For upper bytes LCC-type PROM EPROM adaptor Chip Evaluator mode CPU probe Chip Notes on PK6 Usage FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings: 1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150kΩ), and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load impedance. 2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output prior to software reset execution or connecting pull-up resistor is recommended. RST Normal operation PK6 Flash mode Keep PK6 above 0.7 VDD during this period. Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM incorporated type is used, above countermeasure should be performed. –7– CXP971000 Package Outline Unit: mm 100PIN PQFP(CERAMIC) 24.7 ± 0.5 22.3 ± 0.25 16.3 ± 0.2 0.8 ± 0.1 30 INDEX 0.5 ± 0.25 + 0.05 0.15 – 0.02 8.6 MAX 1 INDEX 0.65 ± 0.05 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE CERAMIC PQFP-100C-L04 LEAD TREATMENT GOLD PLATING AQFP100-C-0000 LEAD MATERIAL 42 ALLOY PACKAGE MASS 4.9g JEDEC CODE –8– 0.3 ± 0.08 100 13.9 50 1.5 ± 0.05 81 3.2 ± 0.2 51 3.57 ± 0.36 18.7 ± 0.5 80 18.0 CXP971000 100PIN PQFP(CERAMIC) 16.0 ± 0.5 51 100 26 25 INDEX + 0.15 0.2 – 0.13 0.8 ± 0.1 + 0.05 0.127 – 0.02 1 INDEX 3.2 ± 0.2 + 0.08 0.18 – 0.03 1.5 ± 0.05 50 8.0 MAX 0.5± 0.05 75 76 3.32 ± 0.33 12.0 ± 0.15 12.4 14.0 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC SONY CODE PQFP-100C-L03 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000 LEAD MATERIAL 42 ALLOY PACKAGE MASS 2.7g JEDEC CODE –9– Sony Corporation