CXP84700 CMOS 8-bit Single Chip Microcomputer Description The CXP84700 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP84716/84720/84724. Piggyback/ evaluator 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which LQFP supported QFP supported covers various types of data. —16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 333ns at 12MHz operation (3.0 to 5.5V) 250ns at 16MHz operation (4.5 to 5.5V) • Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available.) • Incorporated RAM capacity 2144 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.6µs/16MHz) — Serial interface Start-stop sync type (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels 8-bit clock sync type (MSB/LSB first selectable), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter — High precision timing pattern generator PPG: maximum of 11-pins, 16-stages programmable, 2 channels — PWM output 8 bits, 8 channels — FRC capture unit Incorporated 24-bit and 6-stage FIFO • Interruption 19 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP84700. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96Z12-PS CXP84700 PI2/INT2 PI3/INT3 PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 PG0/PWM0 VSS VDD NC PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/PWM4 PG5/PWM5 PG6/PWM6 PG7/PWM7 PF0 PF1 PF2 Pin Assignment in Piggyback Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PF3 1 80 PI1/INT1 PF4 2 79 PI0/INT0 PF5 3 78 PE7/TO 75 PE4 PD1/PPO1 7 74 PE3/NMI PD2/PPO2 8 73 PE2 VDD A13 6 A14 PE5 PD0/PPO0 NC PE6 A15 77 76 A12 4 5 A7 PF6/TxD PF7/RxD PD3/PPO3 9 72 PE1/EC1 PD4/PPO4 10 71 PE0/EC0 PD5/PPO5 11 70 PB7/SO1 69 PB6/SI1 68 PB5/SCK1 67 PB4/CS1 PD6/PPO6 12 PD7/PPO7 13 PC0 14 PC1 15 PC2 16 PC3 17 PC4 18 PC5 19 PC6 20 PC7 21 PH0/PPO8 22 PH1/PPO9 23 PH2/PPO10 24 PH3/PPO11 PH4/PPO12 PH5/PPO13 4 A6 3 2 1 32 31 30 29 5 6 A5 28 A9 27 7 A4 A8 A11 A3 8 26 NC A2 9 25 OE A1 10 24 A10 A0 11 23 CE 66 PB3 65 PB2 64 PB1 63 PB0/CINT 62 SO0 61 SI0 60 SCK0 59 CS0 58 PA7 57 PA6 25 56 PA5 26 55 PA4 27 54 PA3/AN7 PH6/PPO14 28 53 PA2/AN6 PH7/PPO15 29 52 PA1/AN5 30 51 PA0/AN4 22 12 D0 13 D7 D6 21 D5 D4 D3 NC GND D2 D1 14 15 16 17 18 19 20 AN3 AN2 AN1 AN0 AVDD AVss AVREF EXI3 EXI2 Vss XTAL EXTAL RST PJ7/EXI1 PJ6/EXI0 PJ5/PPO21 PJ4/PPO20 PJ3/PPO19 PJ2/PPO18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PJ1/PPO17 PJ0/PPO16 NC Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. –2– CXP84700 PE7/TO PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 PG0/PWM0 Vss VDD NC PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/PWM4 PG5/PWM5 PG6/PWM6 PG7/PWM7 PF0 PF1 PF2 PF3 PF4 Pin Assignment in Piggyback Mode (LQFP package) AA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE6 74 PE5 73 PE4 72 PE3/NMI 5 71 PE2 PD2/PPO2 6 70 PE1/EC1 PD3/PPO3 7 69 PE0/EC0 PD4/PPO4 8 68 PB7/SO1 PD5/PPO5 9 67 PB6/SI1 PD6/PPO6 10 66 PB5/SCK1 PD7/PPO7 11 65 PB4/CS1 PC0 12 64 PB3 PC1 13 63 PB2 PC2 14 62 PB1 PC3 15 PC4 16 PC5 17 PC6 18 PC7 19 PH0/PPO8 20 PH1/PPO9 PF5 1 PF6/TxD 2 PF7/RxD 3 PD0/PPO0 4 PD1/PPO1 A15 1 28 VDD A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 D7 11 18 D6 12 17 D5 13 16 D4 14 15 D3 61 PB0/CINT 60 SO0 59 SI0 58 SCK0 57 CS0 56 PA7 21 55 PA6 PH2/PPO10 22 54 PA5 PH3/PPO11 23 53 PA4 PH4/PPO12 24 52 PA3/AN7 PH5/PPO13 25 51 PA2/AN6 D0 D1 D2 GND Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. –3– PA1/AN5 PA0/AN4 AN3 AN2 AN1 AN0 AVDD AVREF AVss EXI3 EXI2 Vss XTAL EXTAL RST PJ7/EXI1 PJ6/EXI0 PJ5/PPO21 PJ4/PPO20 PJ3/PPO19 PJ2/PPO18 PJ1/PPO17 PJ0/PPO16 PH7/PPO15 PH6/PPO14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP84700 PI2/INT2 PI3/INT3 PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 PG0/PWM0 VSS VDD NC PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/PWM4 PG5/PWM5 PG6/PWM6 PG7/PWM7 PF0 PF1 PF2 Pin Assignment in Evaluator Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PF3 1 80 PI1/INT1 PF4 2 79 PI0/INT0 76 PE5 PD0/PPO0 6 75 PE4 PD1/PPO1 7 74 PE3/NMI 73 PE2 A13 5 A14 PE6 PF7/RxD VDD PE7/TO 77 A15 78 4 A12 3 A7/D7 PF5 PF6/TxD 8 PD3/PPO3 9 72 PE1/EC1 PD4/PPO4 10 71 PE0/EC0 70 PB7/SO1 69 PB6/SI1 68 PB5/SCK1 67 PB4/CS1 66 PB3 65 PB2 64 PB1 63 PB0/CINT PD5/PPO5 11 PD6/PPO6 12 PD7/PPO7 13 PC0 14 PC1 15 PC2 16 PC3 17 PC4 18 PC5 19 PC6 20 PC7 4 A6/D6 3 NC PD2/PPO2 2 1 32 31 30 29 5 6 A5/D5 A4/D4 27 HALT A10 24 10 A0/D0 NC 25 9 A1/D1 A11 26 8 A2/D2 A9 28 7 A3/D3 A8 23 11 E/P NC 12 22 I/T RD 13 21 MON 62 SO0 61 SI0 21 60 SCK0 PH0/PPO8 22 59 CS0 PH1/PPO9 23 58 PA7 PA6 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 PH2/PPO10 24 57 PH3/PPO11 25 56 PA5 PH4/PPO12 26 55 PA4 PH5/PPO13 27 54 PA3/AN7 PH6/PPO14 28 53 PA2/AN6 PH7/PPO15 29 52 PA1/AN5 PJ0/PPO16 30 51 PA0/AN4 AN3 AN2 AN1 AN0 AVDD AVREF EXI3 AVss EXI2 Vss XTAL RST EXTAL PJ7/EXI1 PJ6/EXI0 PJ5/PPO21 PJ4/PPO20 PJ3/PPO19 PJ2/PPO18 PJ1/PPO17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. –4– CXP84700 PE7/TO PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 PG0/PWM0 Vss VDD NC PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/PWM4 PG5/PWM5 PG6/PWM6 PG7/PWM7 PF0 PF1 PF2 PF3 PF4 Pin Assignment in Evaluator Mode (LQFP package) AA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 PE6 2 74 PE5 3 73 PE4 PD0/PPO0 4 72 PE3/NMI PD1/PPO1 5 71 PE2 PD2/PPO2 6 70 PE1/EC1 PD3/PPO3 7 69 PE0/EC0 PD4/PPO4 8 68 PB7/SO1 PD5/PPO5 9 67 PB6/SI1 PD6/PPO6 10 66 PB5/SCK1 PD7/PPO7 11 65 PB4/CS1 PC0 12 64 PB3 PC1 13 63 PB2 PC2 14 62 PB1 PC3 15 61 PB0/CINT PC4 16 60 SO0 PC5 17 59 SI0 PC6 18 58 SCK0 PC7 19 57 CS0 PH0/PPO8 20 56 PA7 PH1/PPO9 21 55 PA6 PH2/PPO10 22 54 PA5 PH3/PPO11 23 53 PA4 PH4/PPO12 24 52 PA3/AN7 PH5/PPO13 25 51 PA2/AN6 A15 1 28 VDD A12 2 27 A14 A7/D7 3 26 A13 A6/D6 4 25 A8 A5/D5 5 24 A9 A4/D4 6 23 A11 A3/D3 7 22 HALT A2/D2 8 21 A10 A1/D1 9 20 E/P A0/D0 10 19 I/T RD 11 18 MON WR 12 17 RST SYNC 13 16 C1 GND 14 15 C2 PA1/AN5 PA0/AN4 AN3 AN2 AN1 AN0 AVDD AVREF AVss EXI3 EXI2 Vss XTAL EXTAL RST PJ7/EXI1 PJ6/EXI0 PJ5/PPO21 PJ4/PPO20 PJ3/PPO19 PJ2/PPO18 PJ1/PPO17 PJ0/PPO16 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PH7/PPO15 PF7/RxD PH6/PPO14 PF5 PF6/TxD Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. –5– CXP84700 EPROM Read Timing (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin Min. Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Max. Unit 100∗1 75∗2 0 ns ns ∗1 At 12MHz operation (VDD = 4.5 to 5.5V) ∗2 At 12MHz operation (VDD = 3.0 to 5.5V), at 16MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Mask product Piggyback/evaluator product CXP84716 CXP84720 CXP84724 CXP84700-U01Q CXP84700-U01R 100-pin plastic QFP/LQFP 100-pin ceramic PQFP Option item Package ROM capacity 16K bytes 20K bytes 24K bytes EPROM 60K bytes 27C512 × 1 Pull-up resistor for reset pin Existent/Non-existent Existent Power-on-reset circuit Existent/Non-existent Existent –6– CXP84700 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe EPROM adaptor Pin 1 marking Note) Evaluation cap should be connected to CPU probe. Pin 1 index CPU probe for LQFP –7– CXP84700 Package Outline Unit: mm PIN NO. 1 INDEX 18.7 100PIN PQFP (CERAMIC) 16.3 ± 0.2 INDEX 100 81 81 80 PIN No. 1 INDEX 1 80 0.65 ± 0.05 1 100 0.3 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 30 0.7 1.0 0.3 6.0 24.7 22.3 ± 0.25 4.5 51 31 1.3 ± 0.3 51 50 9.48 11.66 30 50 31 0.45 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL PQFP-100C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g 10.44 MAX + 0.05 0.15 – 0.02 0.50 ± 0.25 JEDEC CODE 3.57 ± 0.36 CERAMIC SONY CODE 100PIN PQFP (CERAMIC) 16.0 ± 0.4 12.4 14.0 ± 0.2 75 51 76 0.5 ± 0.05 + 0.08 0.18 – 0.03 1.5 3.2 ± 0.2 0.5 ± 0.05 12.0 ± 0.15 + 0.08 0.18 – 0.03 0.8 ± 0.2 26 100 1 INDEX 12.0 ± 0.15 50 25 12.8 ± 0.2 INDEX 6.9 + 0.15 0.2 – 0.13 + 0.05 0.127 – 0.02 3.32 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC SONY CODE PQFP-100C-L02 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-1414-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 2.2g JEDEC CODE –8–