WIRELESS COMMUNICATIONS DIVISION TQ3631 C2 Control Logic DATA SHEET L1 C2 VDD GND GND RF IN 3V PCS Band CDMA LNA IC RF 50 ohm OUT RF Out LNA gnd C3 Control Logic Features Small size: SOT23-8 Single 3V operation Low-current operation Product Description Gain Select The TQ3631 is a 3V, RF LNA IC designed specifically for PCS band CDMA applications. It’s RF performance meets the requirements of products designed to the IS-95 specifications. The TQ3631 is designed to be used with the TQ5631 (CDMA mixer) which provides a complete CDMA receiver for 1900MHz phones. High IP3 performance The LNA incorporates on-chip switches which determine high, low and bypass mode select. When used with the TQ5631 (CDMA RFA/mixer), four gain steps are available for use which provide low current/high IP3 and gain. The RF output port is internally matched to 50 Ω, greatly simplifying the design and minimizing the number of external components. The TQ3631 achieves excellent RF performance with low current consumption, supporting long standby and talk times in portable applications. Coupled with the very small SOT23-8 package, the part is ideally suited for PCS band mobile phones. Few external components Applications IS-95 CDMA PCS Mobile Phones Electrical Specifications1 Parameter Min Typ Max Units Frequency 1960 MHz Gain 13.0 dB Noise Figure 1.5 dB 3rd 10.0 dBm 11.0 mA Input Order Intercept DC supply Current Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, Tc=25C, CDMA High Gain state. For additional information and latest specifications, see our website: www.triquint.com 1 TQ3631 Data Sheet Electrical Characteristics Parameter Conditions Min. Typ/Nom Max. Units RF Frequency PCS band 1810 1960 1990 MHz 12.0 13.0 CDMA Mode-High Gain Gain Noise Figure 1.5 dB 2.2 Input IP3 7.0 Input Return Loss (with external matching) 10 dB Output Return Loss 10 dB Supply Current 10.0 dB 11.0 dBm 13.0 mA CDMA Mode-High Gain-Low Linearity Gain 10.0 Noise Figure 11.5 1.6 dB 2.8 Input IP3 2.0 Input Return Loss (with external matching) 10 dB Output Return Loss 10 dB Supply Current 5.0 dB 4.5 dBm 5.5 mA Bypass Mode Gain -2.5 Noise Figure 2.0 Input IP3 30.0 dB 2.8 dB dBm Input Return Loss (with external matching) 10 dB Output Return Loss 10 dB Supply Current 1.0 Supply Voltage 2.7 Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, TC = 25° C, unless otherwise specified. Note 2: Min/Max limits are at +25°C case temperature, unless otherwise specified. Absolute Maximum Ratings Parameter Value Units DC Power Supply 5.0 V Power Dissipation 500 mW Operating Temperature -40 to 85 C Storage Temperature -60 to 150 C Signal level on inputs/outputs +20 dBm Voltage to any non supply pin +0.3 V 2 -1.5 For additional information and latest specifications, see our website: www.triquint.com 2.8 2.0 3.3 mA V TQ3631 Data Sheet Typical Performance Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=25C, RF=1960MHz 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 1920 CDMA High Gain Mode Idd v Vdd v Temp 13.00 12.00 11.00 Idd (mA) Gain (dB) CDMA High Gain Mode Gain v Freq v Temp -30C +25C +85C 10.00 9.00 -30C +25C +85C 8.00 7.00 6.00 1940 1960 Frequency (MHz) 1980 2.5 2000 Gain (dB) IIP3 (dBm) 9.5 9.0 8.5 -30C 8.0 +25C +85C 7.5 1960 Frequency (MHz) 1980 2000 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 1920 IIP3 (dBm) Noise Figure (dB) -30C +25C +85C 1940 1960 1980 2000 High Gain/Low Linearity Mode IIP3 v Freq v Temp -30C +25C +85C 1940 3.3 Frequency (MHz) CDMA High Gain Mode Noise Figure v Freq v Temp 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 1920 3.1 High Gain/Low Linearity Mode Gain v Freq v Temp 10.0 1940 2.9 Vdd (V) CDMA High Gain Mode IIP3 v Freq v Temp 7.0 1920 2.7 1960 1980 Frequency (MHz) 2000 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 1920 -30C +25C +85C 1940 1960 1980 2000 Frequency (MHz) For additional information and latest specifications, see our website: www.triquint.com 3 TQ3631 Data Sheet BYPASS Mode Noise Figure v Freq v Temp 2.50 3.00 2.00 2.50 Noise Figure (dB) Noise Figure (dB) High Gain/Low Linearity Mode Noise Figure v Freq v Temp 1.50 1.00 -30C +25C +85C 0.50 0.00 1920 1940 1960 1980 Frequency (MHz) 2.00 1.50 1.00 -30C +25C +85C 0.50 0.00 1920 2000 1940 4.50 IIP3 (dBm) Idd (mA) 5.00 4.00 -30C +25C +85C 2.50 2.5 2.7 2.9 Vdd (V) 3.1 3.3 35.0 34.0 33.0 32.0 31.0 30.0 29.0 28.0 27.0 26.0 25.0 1920 -30C +25C +85C 1940 1980 2000 BYPASS Mode Idd v Vdd v Temp 0.0 1.60 -0.5 1.40 -1.0 1.20 -1.5 -2.0 Idd (mA) Gain (dB) 1960 Frequency (MHz) BYPASS Mode Gain v Freq v Temp -30C +25C -2.5 1940 1960 1980 Frequency (MHz) 1.00 0.80 0.60 -30C +25C +85C 0.40 +85C -3.0 1920 0.20 2000 0.00 2.5 2.7 2.9 Vdd (V) 4 2000 BYPASS Mode IIP3 v Freq v Temp 5.50 3.00 1980 Frequency (MHz) High Gain/Low Linearity Mode Idd v Vdd v Temp 3.50 1960 For additional information and latest specifications, see our website: www.triquint.com 3.1 3.3 TQ3631 Data Sheet Application/Test Circuit Vdd R1 Control Logic C2 Vdd GND GND C7 (paddle) L1 LNA input RF in RF out LNA output LNA GND C3 Control Logic C8 Lbrd Bill of Material for TQ3631 LNA Application/Test Circuit Component Reference Designator Part Number Value Size Manufacturer Receiver IC U1 TQ3631 SOT23-8 TriQuint Semiconductor Capacitor C7 2.7pF 0402 Capacitor C8 1.5pF 0402 Resistor R1 3.3Ω 0402 Inductor L1 3.9nH 0402 Inductor Lbrd See application note For additional information and latest specifications, see our website: www.triquint.com Panasonic 5 TQ3631 Data Sheet TQ3631 Product Description Operation The TQ3631 LNA uses a cascode low noise amplifier along with signal path switching. A bias control circuit sets the quiescent current for each mode and ensures peak performance over process and temperature, see Figure 1. In the application, CMOS level signals are applied to pins 1 and 5 and are decoded by an internal logic circuit, this sets the device to the desired mode. See Table 1 for truth table. In the high gain mode, switches S1, S2, and S5 are closed, with switches S3 and S4 open. In the bypass mode, switches S1, S2, and S5 are open, with switches S3 and S4 closed. Six internal switches ensures there are no parasitic feedback paths for the RF signal. In the AMPS mode, control logic switches the LNA into a low current bias condition. Only three external components are. The chip uses an external cap and inductor for the input match to pin 3. The output is internally matched to 50 ohms at pin 6. A Vdd bypass cap is required close to pin 8. External degeneration of the cascode is required between pin 4 and ground. However, a small amount of PC board trace can be used as the inductor. Alternatively, if an extra component can be tolerated, a small value chip inductor could be used. See Figure 2. VDD 1 Bias and Switch Control Logic 8 C7 2 LNA IN GND S6 L1 3 S2 RFIN C8 S3 4 Lbrd LNA OUT 6 S1 5 DC GND Figure 1 TQ3631 Simplified Schematic 6 Typical Gain High Gain 0 0 13(dB) 1 0 0 1 11(dB) 1 1 -2(dB) High Gain Low linearity Bypass Table 1 LNA States and Control Bits LNA Input Network Design Input network design for most LNA’s is a straightforward compromise between noise figure and gain. The TQ3631 is no exception, even though it has 3 different modes. The device was designed so that one only needs to optimize the input match in the high gain mode. As long as the proper grounding and source inductance are used, the other two modes will perform well with the same match. It is probably wise to synthesize the matching network component values for some intermediate range of Gamma values, and then by experimentation, find the one which provides the best compromise between noise figure and gain. The quality of the chip ground will have some effect on the Noise Parameter Analysis RF OUT S4 S5 C3 The values used on our evaluation board may be used as a starting point. 7 GND C2 match, which is why some experimentation will likely be needed. The input match will affect the output match to some degree, so S22 should be monitored. R1 VDD Control Logic C2 MODE Control Logic C3 A noise parameter analysis is shown on the next page for the high gain mode. A “nominal” device was mounted directly on an evaluation board with semi-rigid probes attached to the device input and output pins. A value of Lbrd was chosen so that 13.0dB of gain was attained at conjugate match. The tuner was removed and noise data was taken. For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Gamma Opt analysis for TQ3631 High Gain Mode Freq. (MHz) 1800 1960 2040 Opt Angle 0.453 0.459 0.437 95.8 109.4 116.4 Fmin (dB) 1.476 1.178 1.287 R noise Figure 2 Showing Lbrd and Grounding on Evaluation Board 14.2 9.58 8.17 Gain Control via Pin 4 Inductance The source connection of the LNA cascode is brought out separately through pin 4. That allows the designer to make some range of gain adjustment. The total amount of inductance present at the source of the cascode is equal to the bond wire plus package plus external inductance. One should generally use an external inductance such that gain in the high gain CDMA mode = 13.0dB. Although it is possible to increase the gain of the TQ3631 by using little or no degeneration, input intercept will be degraded. Figure 2 shows how a spiral PC board trace can be used as the external inductance. It is suggested that such a circuit be used for the initial design prototype. Then the optimum inductance can be found by simply solder bridging across the inductor. The final PC board design can then include the proper shorted version of the inductor. Selection of the Vdd Bypass Cap for Optimum Performance The Vdd bypass capacitor has the largest effect on the LNA output match, and is required for proper operation. Because the input match affects the output match to some degree as well, the process of picking the bypass cap value involves some iteration. First, an input match is selected which gives adequate gain and noise figure. Then the bypass capacitor is varied to give the best output match. The demo board achieves 11-12dB of return loss which is adequate for connection directly to the input of a SAW filter. Grounding An optimal ground for the device is important in order to achieve datasheet specified performance. Symptoms of a poor ground include reduced gain and the inability to achieve <2:1 VSWR at the output when the input is matched. It is recommended to use multiple vias to a mid ground plane layer. The vias at pins 2 and 7 to this layer should be as close to the lead pads as possible Additionally, the ground return on the Vdd bypass cap should provide minimal inductance back to chip pins 2 and 7. TQ3631 S-Parameters Following are S-Parameter graphs for the high gain and high mode. Data was taken on a single “nominal” device at 2.8v Vdd. The reference planes were set at the end of the package pins. For additional information and latest specifications, see our website: www.triquint.com 7 TQ3631 Data Sheet TQ3631 High Gain Mode S-Parameters S11 TQ3631 High Gain Mode S-Parameters S12 TQ3631 High Gain Mode S-Parameters S21 TQ3631 High Gain Mode S-Parameters S22 8 For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Package Pinout C2 Control Logic L1 C2 VDD GND GND RF IN GND RF 50 ohm OUT RF Out C3 Control Logic Pin Descriptions Pin Name Pin # Description and Usage C2 1 Control logic 2 GND 2 Ground, paddle RF IN 3 RF input, off-chip matching required DC GND 4 Source of input FET C3 5 Control logic 3 RF OUT 6 RF output, no matching required GND 7 Ground Vdd 8 LNA Vdd, typical 2.8V, C7 capacitor required For additional information and latest specifications, see our website: www.triquint.com 9 TQ3631 Data Sheet Package Type: SOT23-8 Plastic Package Note 1 PIN 1 E E1 b FUSED LEAD Note 2 A c e DESIGNATION A A1 b c D e E E1 L Theta L A1 DESCRIPTION OVERALL HEIGHT STANDOFF LEAD WIDTH LEAD THICKNESS PACKAGE LENGTH LEAD PITCH LEAD TIP SPAN PACKAGE WIDTH FOOT LENGTH FOOT ANGLE DIE METRIC 1.20 +/-.25 mm .100 +/-.05 mm .365 mm TYP .127 mm TYP 2.90 +/-.10 mm .65 mm TYP 2.80 +/-.20 mm 1.60 +/-.10 mm .45 +/-.10 mm 1.5 +/-1.5 DEG θ ENGLISH 0.05 +/-.250 in .004 +/-.002 in .014 in .005 in .114 +/-.004 in .026 in .110 +/-.008 in .063 +/-.004 in .018 +/-.004 in 1.5 +/-1.5 DEG NOTE 3 3 3 3 1,3 3 3 2,3 3 Notes 1. The package length dimension includes allowance for mold mismatch and flashing. 2. The package width dimension includes allowance for mold mismatch and flashing. 3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error. Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Tel: (503) 615-9000 Email: [email protected] Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision A, March, 2000 10 For additional information and latest specifications, see our website: www.triquint.com