0 QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs R DS082 (v1.2) November 5, 2001 0 5 Preliminary Product Specification Features Radiation Hardenned XQR18V04 • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs • Fabricated on Epitaxial Substrate • Latch-Up Immune to >120 LET - Endurance of 2,000 program/erase cycles • Guaranteed TID of 40 kRad(Si) - Program/erase over full military temperature range • Supports SEU Scrubbing • IEEE Std 1149.1 boundary-scan (JTAG) support • Cascadable for storing longer or multiple bitstreams Description • Dual configuration modes Xilinx introduces the QPro™ XQ18V04 and XQR18V04 series of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams. - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mbps at 33 MHz) • Low-power advanced CMOS FLASH process • 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals. • 3.3V or 2.5V output capability • Available in CC44 and VQ44 packages. • Design support using the Xilinx Alliance™ and Foundation™ series software packages. • JTAG command initiation of standard FPGA configuration. • Available to Standard Microcircuit Drawing 5962-01525. - When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 6. For more information contact Defense Supply Center Columbus (DSCC) at http://www.dscc.dla.mil OE/Reset CLK CE TCK TMS TDI Control and JTAG Interface Data Memory Address Data TDO CEO Serial or Parallel Interface 7 D0 DATA (Serial or Parallel [Express/SelectMAP] Mode) D[1:7] Express Mode and SelectMAP Interface CF DS026_01_021000 Figure 1: XQ18V04 Series Block Diagram © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC1700L one-time programmable Serial PROM family. Pinout and Pin Description Table 1: Pin Names and Descriptions (pins not listed are “no connect”) Pin Name Boundary Scan Order Function D0 4 DATA OUT 3 OUTPUT ENABLE 6 DATA OUT 5 OUTPUT ENABLE 2 DATA OUT 1 OUTPUT ENABLE 8 DATA OUT 7 OUTPUT ENABLE 24 DATA OUT 23 OUTPUT ENABLE 10 DATA OUT 9 OUTPUT ENABLE 17 DATA OUT 16 OUTPUT ENABLE 14 DATA OUT 13 OUTPUT ENABLE CLK 0 DATA IN OE/ RESET 20 DATA IN 19 DATA OUT 18 OUTPUT ENABLE 15 DATA IN D1 D2 D3 D4 D5 D6 D7 CE 2 44-pin 44-pin Pin Description VQFP CLCC D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. 40 2 D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Express/SelectMap mode. 29 35 42 4 27 33 9 15 25 31 14 20 19 25 Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. 43 5 When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. 13 19 When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low power standby mode. 15 21 www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Table 1: Pin Names and Descriptions (pins not listed are “no connect”) (Continued) Pin Name Boundary Scan Order Function CF 22 DATA OUT 21 OUTPUT ENABLE 13 DATA OUT 14 OUTPUT ENABLE CEO GND 44-pin 44-pin Pin Description VQFP CLCC Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. 10 16 Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. 21 27 6, 18, 28 & 41 3, 12, 24 & 34 The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. 5 11 GND is the ground connection. TMS MODE SELECT TCK CLOCK This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 7 13 TDI DATA IN This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 3 9 TDO DATA OUT This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 31 37 VCC Positive 3.3V supply voltage for internal logic and input buffers. 17, 35 & 38 23, 41 & 44 VCCO Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers. 8, 16, 26 & 36 14, 22, 32 & 42 DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 3 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Xilinx FPGAs and Compatible PROMs Device Configuration Bits XQ(R)18VO4 PROMs XQV100 781,216 1 XQV(R)300 1,751,808 1 XQV(R)600 3,607,968 1 XQV(R)1000 6,127,744 2 XQV(R)600E 3,961,632 1 XQV(R)1000E 6,587,520 2 XQV(R)2000E 10,159,648 3 In-System Programming In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx JTAG Programmer software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The JTAG Programmer software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming. Capacity Devices Configuration Bits XQ(R)18V04 4,194,304 OE/RESET The ISP programming algorithm requires issuance of a reset that will cause OE to go Low. External Programming Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes. Reliability and Endurance Xilinx in-system programmable products provide a guaranteed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. Each device meets all functional, performance, and data retention specifications within this endurance limit. Design Security The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 2 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 2: Data Security Options 4 Default = Reset Set Read Allowed Program/Erase Allowed Read Inhibited via JTAG Erase Allowed www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs V CC GND (a) (b) DS026_02_011100 Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable IEEE 1149.1 Boundary-Scan (JTAG) Table 3: Boundary Scan Instructions The XQ(R)18V04 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XQ(R)18V04 device. Table 3 lists the required and optional boundary-scan instructions supported in the XQ(R)18V04. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. Boundary-Scan Command Binary Code [7:0] Description Required Instructions BYPASS 11111111 Enables BYPASS SAMPLE/ PRELOAD 00000001 Enables boundary-scan SAMPLE/PRELOAD operation EXTEST 00000000 Enables boundary-scan EXTEST operation Optional Instructions CLAMP 11111010 Enables boundary-scan CLAMP operation HIGHZ 11111100 All outputs in high-impedance state simultaneously IDCODE 11111110 Enables shifting out 32-bit IDCODE USERCODE 11111101 Enables shifting out 32-bit USERCODE XQ(R)18V04 Specific Instructions CONFIG DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 11101110 Initiates FPGA configuration by pulsing CF pin Low 5 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Instruction Register The Instruction Register (IR) for the XQ(R)18V04 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. The ISP Status field, IR(4), contains logic "1" if the device is currently in ISP mode; otherwise, it will contain logic "0". The Security field, IR(3), will contain logic "1" if the device has been programmed with the security option turned on; otherwise, it will contain logic "0". TDI-> IR[7:5] IR[4] IR[3] IR[2] IR[1:0] 000 ISP Status Security 0 01 ->TDO tion by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (50h for XQ(R)18V04 family) a = the ISP PROM product ID (26h for the XQ(R)18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1 Table 4 lists the IDCODE XQ(R)18V00 devices. 0 Notes: Boundary Scan Register The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XQ(R)18V00 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin. Identification Registers The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examina- 6 values for the Table 4: IDCODES Assigned to XQ(R)18V04 Devices 1. IR(1:0) = 01 is specified by IEEE Std. 1149.1 Figure 3: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence register ISP-PROM IDCODE XQ(R)18V04 05026093h The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XQ(R)18V04 device. If the device is blank or was not loaded during programming, the USERCODE register will contain FFFFFFFFh. XQ(R)18V04 TAP Characteristics The XQ(R)18V04 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XQ(R)18V04 TAP are described as follows. TAP Timing Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs TCKMIN TCK TMSS TMSH TMS TDIS TDIH TDI TDOV TDO DS026_04_020300 Figure 4: Test Access Port Timing TAP AC Parameters Table 5 shows the timing parameters for the TAP waveforms shown in Figure 4 Table 5: Test Access Port Timing Parameters Symbol Parameter Min Max Units TCKMIN1 TCK minimum clock period 100 - ns TCKMIN2 TCK minimum clock period, Bypass mode 50 - ns TMSS TMS setup time 10 - ns TMSH TMS hold time 25 - ns TDIS TDI setup time 10 - ns TDIH TDI hold time 25 - ns TDOV TDO valid delay - 25 ns DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 7 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Connecting Configuration PROMs Connecting the FPGA device with the configuration PROM (see Figure 6). • The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) (in Master Serial mode only). • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). • The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. • • The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 20 mA maximum. Express/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. Initiating FPGA Configuration The XQ(R)18V04 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF low for 300-500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The JTAG Programmer software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting. Selecting Configuration Modes The XQ(R)18V04 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XQ(R)18V04 device. This control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx 8 JTAG Programmer software. Serial output is the default programming mode. Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed to accommodate the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor. Cascading Configuration PROMs For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (Figure 5). Multiple XQ(R)18V04 devices can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all XQ(R)18V04 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 6. After configuration is complete, the address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low. www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Vcc Vcco Vcc Vcco Vcc 4.7K Vcc MODE PINS* Vcc DOUT DIN DIN Vcc D0 Vcco J1 TDI TMS TCK TDO 1 2 3 4 D0 Vcc Vcco XC18V00 XC18V00 Cascaded PROM First PROM TDI CLK TDI Vcc Master Serial Slave Serial CCLK CCLK DONE DONE TMS CE TCK CEO TCK CEO OE/RESET OE/RESET CF CF GND Xilinx FPGA ** CE TDO Xilinx FPGA CLK TMS GND MODE PINS* TDO INIT INIT PROGRAM PROGRAM TDI TDI TMS TMS TCK TDO * For Mode pin connections, refer to appropriate FPGA data sheet. ** Virtex, Virtex-E is 300 ohms, all others are 4.7K. TCK TDO DS026_08_021000 Figure 5: JTAG Chain for Configuring Devices in Master Serial Mode DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 9 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs OPTIONAL Daisy-chained FPGAs with different configurations DOUT FPGA OPTIONAL Slave FPGAs with identical configurations Vcco Vcc VCC 4.7K Modes* VCC ** VCC VCCO DATA First CLK PROM CEO CE DIN CCLK DONE INIT DATA Cascaded PROM CLK CE OE/RESET OE/RESET CF CF PROGRAM (Low Resets the Address Pointer) *For Mode pin connections, refer to the appropriate FPGA data sheet. **Virtex, Virtex-E is 300 ohms, all others are 4.7K. Master Serial Mode I/O* I/O* Modes*** WRITE 1K VIRTEX Select MAP NC VCC VCCO VCC VCCO CS External Osc 1K 3.3V VCC BUSY 4.7K XC18Vxx ** CCLK CLK 8 PROGRAM D[0:7] D[0:7] CEO CE DONE OE/RESET INIT CF *CS and WRITE must be pulled down to be used as I/O. One option is shown. **Virtex, Virtex-E is 300 ohms, all others are 4.7K. ***For Mode pin connections, refer to the appropriate FPGA data sheet. Virtex Select MAP Mode To Additional Optional Daisy-chained Devices VCC VCC VCC VCCO VCC 4.7K VCC 4.7K VCCO D[0:7] 8 M0 CS1 M1 DOUT Spartan-XL, XC4000 D[0:7] CEO XC18Vxx CE CF OE/RESET CLK PROGRAM DONE INIT M0 M1 CS1 DOUT Optional Daisy-chained Spartan-XL, XC4000 D[0:7] PROGRAM DONE INIT CCLK CCLK To Additional Optional Daisy-chained Devices External Osc Spartan-XL Express Mode DS026_05_031000 Figure 6: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan-XL Express Mode (dotted lines indicates optional connection) 10 www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs 5V Tolerant I/Os The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) may have power applied in any order. This makes the PROM devices immune to power supply sequencing issues. is held low until the XQ(R)18V04 voltage reaches the operating voltage range. If the power drops below 2.0V, the PROM will reset. OE/RESET polarity is NOT programmable. Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be in a high-impedance state or High. Reset Activation Customer Control Pins On power up, OE/RESET is held low until the XQ(R)18V04 is active (1 ms) and able to supply data after receiving a CCLK pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing configuration to begin. OE/RESET The XQ(R)18V04 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using "Skip User Array" in Xilinx JTAG Programmer Software. Table 6: Truth Table for PROM Control Inputs Control Inputs Outputs OE/RESET CE Internal Address DATA CEO ICC High Low If address < TC(1): increment If address > TC (1): don’t change Active High-Z High Low Active Reduced Low Low Held reset High-Z High Active High High Held reset High-Z High Standby Low High Held reset High-Z High Standby Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0. DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 11 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Absolute Maximum Ratings(1,2) Symbol Description Value Units VCC Supply voltage relative to GND –0.5 to +4.0 V VIN Input voltage with respect to GND –0.5 to +5.5 V VTS Voltage applied to High-Z output –0.5 to +5.5 V TSTG Storage temperature (ambient) –65 to +150 °C Ceramic +150 °C Plastic +125 °C TJ Junction temperature Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCO Parameter Min Max Units Internal voltage supply (TC = –55°C to +125°C) Ceramic 3.0 3.6 V Internal voltage supply (TJ = –55°C to +125°C) Plastic 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCO V Quality and Reliability Characteristics Symbol Description Min Max Units 10 - Years TDR Data retention NPE Program/erase cycles (Endurance) 2,000 - Cycles VESD Electrostatic discharge (ESD) 2,000 - Volts Radiation Tolerances for XQR18V04 Symbol Description Min Max Units TID Total Ionizing Dose - 40 krad(Si) SEL Single Event Latch-Up - 0 cm2 - 0 cm2 (No Latch-Up observed for LET > 120 MeV-mg/cm2) SEU Static Memory Cell Saturation Bit Cross-Section (No Upset observed for LET > 120 MeV-mg/cm2) 12 www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs DC Characteristics Over Operating Conditions Symbol VOH Parameter Test Conditions Min Max Units 2.4 - V 90% VCCO - V High-level output voltage for 3.3V outputs IOH = –4 mA High-level output voltage for 2.5V outputs IOH = –500 µA Low-level output voltage for 3.3V outputs IOL = 8 mA - 0.4 V Low-level output voltage for 2.5V outputs IOL = 500 µA - 0.4 V ICC Supply current, active mode 25 MHz - 50 mA ICCS Supply current, standby mode - 20 mA IILJ JTAG pins TMS, TDI, and TDO VCC = MAX VIN = GND –100 - µA IIL Input leakage current VCC = Max VIN = GND or VCC –10 10 µA IIH Input and output High-Z leakage current VCC = Max VIN = GND or VCC –10 10 µA Input and output capacitance VIN = GND f = 1.0 MHz - 10 pF VOL CIN and COUT DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 13 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V04 . . CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 20 ns TCAC CLK to data delay - 20 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns TDF CE or OE/RESET to data float delay(2) - 25 ns Clock periods 50 - ns TLC CLK Low time(3) 10 - ns THC CLK High time(3) 10 - ns TSCE CE setup time to CLK (to guarantee proper counting)(3) 25 - ms THCE CE High time (to guarantee proper counting) 2 - µs THOE OE/RESET hold time (guarantees counters are reset) 25 - ns TCYC Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 µs, TCE = 2 µs. 14 www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V04 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 25 ns TOCK CLK to CEO delay(3) - 20 ns TOCE CE to CEO delay(3) - 20 ns TOOE OE/RESET to CEO delay(3) - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS082 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 15 R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Ordering Information XQ18V04 CC44 V Device Number Grade (Manufacturing Flow / Temperature Range) Package Type Device Ordering Options Device Type Package Grade XQ18V04 CC44 44-pin Ceramic Chip Carrier Package M Military Ceramic TC = –55°C to +125°C XQR18V04(1) VQ44 44-pin Plastic Thin Quad Flat Package N Military Plastic TJ = –55°C to +125°C V QPro-Plus TC = –55°C to +125°C Notes: 1. Radiation Hardened. 5962 - 01525 Q Y A Generic Standard Microcircuit Drawing (SMD) Lead Finish Package Type Radiation Hardened (1) QML Certified MIL-PRF-38535 Device Type SMD Ordering Options Device Type QML Package Lead Finish 5962-01525 XQ18V04 - 44-pin Ceramic Chip Carrier Package Solder Dip 5962R01525 XQR18V04 - 44-pin Plastic Thin Quad Flat Package Solder Plate Notes: 1. Type R designates Radiation Hardened. Valid Ordering Combinations 16 Mil-Std SMD Rad Hard SMD XQ18V04CC44M - XQR18V04CC44M - XQ18V04VQ44N - XQR18V04CC44V www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Revision History The following table shows the revision history for this document. Date Version 5/1/01 1.0 First publication of this early access specification 7/23/01 1.1 Preliminary publication supporting Full Mil Temp range and corrected write cycles 11/05/01 1.2 Added Class V to ordering combinations for Rad Hard version. Updated format. DS082 (v1.2) November 5, 2001 Preliminary Product Specification Revision www.xilinx.com 1-800-255-7778 17 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.