EM78P156N
OTP ROM
EM78P156N
8-BIT MICRO-CONTROLLER
Version 1.2
EM78P156N
OTP ROM
Specification Revision History
Version
Content
1.0
Initial version
1.1
Change Power on reset content
07/01/2003
1.2
Add the Device Characteristic at section 6.3
07/29/2004
Application Note
AN-001 EM78P156N v.s. EM78P156E on the DC Characteristics
This specification is subject to change without prior notice.
2
07.29.2004 (V1.2)
EM78P156N
OTP ROM
1. GENERAL DESCRIPTION
EM78P156N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS
technology.. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides three PROTECTION bits to prevent user’s code in the OTP memory from being
intruded. 8 OPTION bits are also available to meet user’s requirements.
With its OTP-ROM feature, the EM78P156N is able to offer a convenient way of developing and verifying
user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development
code.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
2. FEATURES
• Operating voltage range : 2.5V~5.5V
• Operating temperature range: -40°C~85°C
• Operating frequency rang (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.
* ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.
• Low power consumption:
* Less then 2 mA at 5V/4MHz
* Typically 20 µA at 3V/32KHz
* Typically 1 µA during sleep mode
• 1K × 13 bits on chip ROM
• One security register to prevent intrusion of OTP memory codes
• One configuration register to accommodate user’s requirements
• 48× 8 bits on chip registers (SRAM, general purpose register)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Three available interruptions
* TCC overflow interrupt
* Input-port status changed interrupt (wake up from sleep mode)
* External interrupt
• Programmable free running watchdog timer
• 8 programmable pull-high pins
• 7 programmable pull-down pins
• 8 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 18 pin DIP 300mil
: EM78P156NP
* 18 pin SOP 300mil
: EM78P156NM
* 20 pin SSOP 209mil
: EM78P156NAS
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
* 20 pin SSOP 209mil
: EM78P156NKM
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
3. PIN ASSIGNMENTS
P52
P51
18
1
NC
1
20
NC
P52
1
20
P51
P52
2
19
P51
P53
2
19
P50
P53
3
18
P50
TCC
3
18
OSCI
TCC
4
17
OSCI
/RESET
4
/RESET
5
16
OSCO
Vss
5
15
VDD
Vss
6
P50
TCC
3
16
OSCI
/RESET
4
15
OSCO
Vss
5
14
VDD
Vss
6
P60/INT
6
13
P67
P60/INT
7
14
P67
P60/INT
7
P61
7
12
P66
P61
8
13
P66
P61
8
P62
8
11
P65
P62
9
12
P65
P62
9
12
P65
P63
9
10
P64
P63
10
11
P64
P63
10
11
P64
EM78P156NKM
17
EM78P156NAS
2
EM78P156NP
EM78P156NM
P53
17
OSCO
16
VDD
15
VDD
14
P67
13
P66
Fig. 1 Pin Assignment
Table 1 EM78P156NP and EM78P156NM Pin Description
Symbol Pin No.
VDD
14
Type
-
OSCI
16
I
OSCO
15
I/O
TCC
3
I
/RESET
4
I
P50~P53
17,18,
1, 2
I/O
P60~P67
6~13
I/O
6
5
I
-
/INT
VSS
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
* P60~P67 are bi-directional I/O pins.
* These can be pulled-high or can be open-drain by software programming.
* P60~P63 can also be pulled-down by software.
* External interrupt pin triggered by falling edge.
* Ground.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Table 2 EM78P156NAS Pin Description
Symbol Pin No.
VDD
15
Type
-
OSCI
17
I
OSCO
16
I/O
TCC
4
I
/RESET
5
I
P50~P53
18, 19,
2, 3
I/O
P60~P67
7~14
I/O
7
6
I
-
/INT
VSS
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
* P60~P67 are bi-directional I/O pins.
* These can be pulled-high or can be open-drain by software programming.
* P60~P63 can also be pulled-down by software.
* External interrupt pin triggered by falling edge.
* Ground.
Table 3 EM78P156NKM Pin Description
Symbol Pin No.
VDD
15,16
Type
-
OSCI
18
I
OSCO
17
I/O
TCC
3
I
/RESET
4
I
P50~P53
19, 20,
1, 2
I/O
P60~P67
7~14
I/O
7
5, 6
I
-
/INT
VSS
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
* P60~P67 are bi-directional I/O pins.
* These can be pulled-high or can be open-drain by software programming.
* P60~P63 can also be pulled-down by software.
* External interrupt pin triggered by falling edge.
* Ground.
This specification is subject to change without prior notice.
7
07.29.2004 (V1.2)
EM78P156N
OTP ROM
4. FUNCTION DESCRIPTION
OSCO
/RESET
OSCI
WDT timer
TCC
/INT
Oscillator/Timing
Control
R2
ROM
Prescaler
Stack
IOCA
R4
ALU
Instruction
Register
Interrupt
Controller
RAM
R3
R1(TCC)
Instruction
Decoder
ACC
DATA & CONTROL BUS
IOC6
R6
P60//INT
P61
P62
P63
P64
P65
P66
P67
I/O
PORT 6
IOC5
R5
I/O
PORT 5
P50
P51
P52
P53
Fig. 2 Function Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin,
or by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB(CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
• The contents of the prescaler counter will be cleared only when TCC register is written with a
value.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bits wide. The structure is depicted
in Fig.3.
• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows
PC to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits
of the PC are cleared.
• "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g., "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the
ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first
256 locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
Reset Vector
Interrupt Vector
PC (A9 ~ A0)
000H
008H
User Memory
Space
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Address
R PAGE registers
IOC PAGE registers
00
R0
(IAR)
Reserve
01
R1
(TCC)
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(Port5)
IOC5
(I/O Port Control Register)
06
R6
(Port6)
IOC6
(I/O Port Control Register)
CONT (Control Register)
07
Reserve
Reserve
08
Reserve
Reserve
09
Reserve
Reserve
0A
Reserve
IOCA
(Prescaler Control Register)
0B
Reserve
IOCB
(Pull-down Register)
0C
Reserve
IOCC
(Open-drain Control)
0D
Reserve
IOCD
(Pull-high Control Register)
0E
Reserve
IOCE
(WDT Control Register)
IOCF
(Interrupt Mask Register)
0F
RF
(Interrupt Status)
10
︰
General Registers
3F
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
4. R3 (Status Register)
7
6
5
4
3
2
1
0
GP2
GP1
GP0
T
P
Z
DC
C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
• Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT
time-out.
• Bit5 ~7 (GP0 ~ 2) General-purpose read/write bits.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode.
• Bits 6~7 are not used (read only).
• The Bits 6~7 set to “1” at all time.
• Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4 content will select
as R0.
• See the configuration of the data memory in Fig. 4.
6. R5 ~ R6 (Port 5 ~ Port 6)
• R5 and R6 are I/O registers.
• Only the lower 4 bits of R5 are available.
7. RF (Interrupt Status Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXIF
ICIF
TCIF
“1” means interrupt request, and “0” means no interrupt occurs.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by
software.
• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 3 ~ 7 Not used.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
• RF can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
• Note that the result of reading RF is the "logic AND" of RF and IOCF.
8. R10 ~ R3F
• All of these are 8-bit general-purpose registers.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It cannot be addressed.
2. CONT (Control Register)
7
-
6
/INT
5
TS
4
TE
3
PAB
2
PSR2
1
PSR1
0
PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 7 Not used.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
• CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• Only the lower 4 bits of IOC5 can be defined.
• IOC5 and IOC6 registers are both readable and writable.
4. IOCA (Prescaler Counter Register)
• IOCA register is readable.
• The value of IOCA is equal to the contents of Prescaler counter.
• Down counter.
5. IOCB (Pull-down Control Register)
7
6
5
4
3
2
1
0
/PD7
/PD6
/PD5
/PD4
-
/PD2
/PD1
/PD0
• Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin.
0: Enable internal pull-down
1: Disable internal pull-down
• Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin.
• Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin.
• Bit 3
Not used.
• Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin.
• Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin.
• Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin.
• Bit 7 (/PD7) Control bit is used to enable the pull-down of P63 pin.
• IOCB Register is both readable and writable.
6. IOCC (Open-drain Control Register)
7
6
5
4
3
2
1
0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
• Bit 0 (OD0) Control bit is used to enable the open-drain of P60 pin.
0: Disable open-drain output
1: Enable open-drain output
• Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin.
• Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin.
• Bit 3 (OD3) Control bit is used to enable the open-drain of P63 pin.
• Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
• Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin.
• Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin.
• Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin.
• IOCC Register is both readable and writable.
7. IOCD (Pull-high Control Register)
7
6
5
4
3
2
1
0
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
• Bit 0 (/PH0) Control bit is used to enable the pull-high of P60 pin.
0: Enable internal pull-high
1: Disable internal pull-high
• Bit 1 (/PH1) Control bit is used to enable the pull-high of P61 pin.
• Bit 2 (/PH2) Control bit is used to enable the pull-high of P62 pin.
• Bit 3 (/PH3) Control bit is used to enable the pull-high of P63 pin.
• Bit 4 (/PH4) Control bit is used to enable the pull-high of P64 pin.
• Bit 5 (/PH5) Control bit is used to enable the pull-high of P65 pin.
• Bit 6 (/PH6) Control bit is used to enable the pull-high of P66 pin.
• Bit 7 (/PH7) Control bit is used to enable the pull-high of P67 pin.
• IOCD Register is both readable and writable.
8. IOCE (WDT Control Register)
7
6
5
4
3
2
1
0
WDTE
EIS
-
ROC
-
-
-
-
• Bit 7 (WDTE) Control bit used to enable Watchdog timer.
0: Disable WDT.
1: Enable WDT.
WDTE is both readable and writable.
• Bit 6 (EIS) Control bit is used to define the function of P60 (/INT) pin.
0: P60, bi-directional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to
"1".
When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be
read by way of reading Port 6 (R6). Refer to Fig. 7(a).
EIS is both readable and writable.
• Bit 4 (ROC) ROC is used for the R-option.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the
controller. Clearing the ROC will disable the R-option function. If the R-option function is selected,
user must connect the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex). If the
Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8.
• Bits 0~3,5 Not used.
9. IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXIE
ICIE
TCIE
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bit 1 (ICIE) ICIF interrupt enable bit.
0: disable ICIF interrupt
1: enable ICIF interrupt
• Bit 2 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bits 3~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to
Fig. 10.
• IOCF register is both readable and writable.
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the
instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the “WDTC” or “SLEP” instructions. Fig. 5 depicts the circuit diagram of TCC/WDT.
• R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input
(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at
every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4 application
is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is
increased by 1 at every falling edge or rising edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when
the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a
WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
Data Bus
CLK(=Fosc/2 or Fosc/4)
0
TCC
Pin
1
1
M
U
X
M
U
X
0
SYNC
2 cycles
TE
TS
TCC (R1)
TCC overflow interrupt
PAB
0
WDT
1
WTE
(in IOCE)
M
U
X
8-bit Counter
PAB
8-to-1 MUX
M
U
X
IOCA
PAB
PSR0~PSR2
0
Initial
value
1
MUX
PAB
WDT time-out
Fig. 5 Block Diagram of TCC and WDT
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high
internally by software. In addition, Port 6 can also have open-drain output by software. Input status
change interrupt (or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by
software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6).
P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. When the
1
<Note>: Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in
enable state, P50~P51 must be programmed as input pins. Under R-option mode, the current/power
consumption by Rex should be taken into the consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for
Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b), and Figure 8.
PCRD
P
R
Q
_
Q
PORT
C
L
Q
P
R
_
Q
C
L
D
PC W R
CLK
IO D
D
PD W R
CLK
PDRD
0
1
M
U
X
NOTE: Pull-down is not shown in the figure.
Fig. 6 The Circuit of I/O Port and I/O Control Register for Port 5
PC R D
Q
_
Q
P
R D
C L K
C
L
PC W R
Q
_
Q
P
R D
C L K
C
L
PD W R
P 6 0 /I N T
PO R T
B it 6 o f I O C E
P
R
C L K
C
L
D
0
Q
1
_
Q
IO D
M
U
X
PD R D
P
R
C L K
C
L
D
T 10
Q
_
Q
IN T
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60 (/INT)
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
PCRD
P61~P67
PORT
0
1
Q
_
Q
P
R D
CLK
C
L
PCWR
Q
_
Q
P
R D
CLK
C
L
PDWR
IOD
M
U
X
TIN
PDRD
P
R
CLK
C
L
D
Q
_
Q
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67
IOCE.1
D
P
R
Q
Interrupt
CLK
_
C Q
L
RE.1
ENI Instruction
P
D R Q
T10
T11
CLK
_
C
L Q
P
Q R
D
CLK
_
Q C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 input status changed Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status Change
(a) Before SLEEP
1. Disable WDT1 (using very carefully)
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable interrupt (Set IOCF.1)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(II) Port 6 Input Status Change Interrupt
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI"
3. Enable interrupt (Set IOCF.1)
4. IF Port 6 change (interrupt)
→ Interrupt vector (008H)
PCRD
VCC
ROC
Q
P
R
Q
C
L
Q
P
R
Q
C
L
Weakly
Pull-up
PORT
D
CLK
PCWR
IOD
D
PDWR
PDRD
0
M
U
X
1
Rex*
*The Rex is 430K ohm external resistor
Fig. 8 The Circuit of I/O Port with R-option(P50,P51)
1
NOTE: Software disables WDT (watchdog timer) but hardware must be enabled before applying
Port 6 Change Wake-Up function. (CODE Option Register and Bit 11 (ENWDTB-) set to
“1”).
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
4.5 RESET and Wake-up
1. RESET
A RESET is initiated by one of the following events(1) Power on reset.
(2) /RESET pin input "low", or
(3) WDT time-out (if enabled).
The device is kept in a RESET condition for a period of approx. 18ms1 (one oscillator start-up timer period)
after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig.9.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "0".
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• When power is switched on, the upper 3 bits of R3 are cleared.
• The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
• The bits of the IOCA register are set to all "1".
• The bits of the IOCB register are set to all "1".
• The IOCC register is cleared.
• The bits of the IOCD register are set to all "1".
• Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
• Bits 0~2 of RF and bits 0~2 of IOCF register are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode,
WDT (if enabled) is cleared but keeps on running. The controller can be awakened by(1) External reset input on /RESET pin,
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled).
The first two cases will cause the EM78P156N to reset. The T and P flags of R3 can be used to determine the
source of the reset (wake-up). The last case is considered the continuation of program execution and the
global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt
1
NOTE: Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
This specification is subject to change without prior notice.
20
07.29.2004 (V1.2)
EM78P156N
OTP ROM
vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address
008H after wake-up. If DISI is executed before SLEP, the operation will restart from the succeeding instruction
right next to SLEP after wake-up.
Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be disabled. by
software. However, the WDT bit in the option register remains enabled. Hence, the
EM78P156N can be awakened only by Case 1 or 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence,
the EM78P156N can be awakened only by Case 1 or 2. Refer to the section on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P156N (Case [a] above), the following
instructions must be executed before SLEP:
MOV A, @xx000110b
; Select internal TCC clock
CONTW
CLR R1
; Clear TCC and prescaler
MOV A, @xxxx1110b
; Select WDT prescaler
CONTW
WDTC
; Clear WDT and prescaler
MOV A, @0xxxxxxxb
; Disable WDT
IOW RE
MOV R6, R6
; Read Port 6
MOV A, @00000x1xb
; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI)
; Enable (or disable) global interrupt
SLEP
; Sleep
NOP
One problem user should be aware of, is that after waking up from the sleep mode, WDT would enable
automatically. The WDT operation (being enabled or disabled) should be handled appropriately by software
after waking up from the sleep mode.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Table 5 The Summary of the Initialized Values for Registers
Address
N/A
N/A
N/A
0x00
0x01
0x02
Name
IOC5
IOC6
CONT
R0(IAR)
R1(TCC)
R2(PC)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
X
X
X
X
C53
C52
C51
C50
Power-On
U
U
U
U
1
1
1
1
/RESET and WDT
U
U
U
U
1
1
1
1
Wake-Up from Pin Change
U
U
U
U
P
P
P
P
Bit Name
C67
C66
C65
C64
C63
C62
C61
C60
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
/INT
TS
TE
PAB
Power-On
1
0
1
1
1
1
1
1
/RESET and WDT
1
0
1
1
1
1
1
1
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin Change **0/P
0x03
0x04
0x05
0x06
R3(SR)
R4(RSR)
P5
P6
PSR2 PSR1 PSR0
**0/P
**0/P
**0/P
**1/P
**0/P
**0/P
**0/P
Bit Name
GP2
GP1
GP0
T
P
Z
DC
C
Power-On
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
t
t
P
P
P
Wake-Up from Pin Change
P
P
P
t
t
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
1
1
U
U
U
U
U
U
/RESET and WDT
1
1
P
P
P
P
P
P
Wake-Up from Pin Change
1
1
P
P
P
P
P
P
Bit Name
X
X
X
X
P53
P52
P51
P50
Power-On
0
0
0
0
U
U
U
U
/RESET and WDT
0
0
0
0
P
P
P
P
Wake-Up from Pin Change
0
0
0
0
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-On
U
U
U
U
U
U
U
U
This specification is subject to change without prior notice.
22
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Address
0x0F
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
RF(ISR)
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
0x10~0x2F R10~R2F
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
X
X
X
X
X
EXIF
ICIF
TCIF
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
U
U
U
U
U
0
0
0
Wake-Up from Pin Change
U
U
U
U
U
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
/PD7
/PD6
/PD5
/PD4
X
/PD2
/PD1
/PD0
Power-On
1
1
1
1
U
1
1
1
/RESET and WDT
1
1
1
1
U
1
1
1
Wake-Up from Pin Change
P
P
P
P
U
P
P
P
Bit Name
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
WDTE
EIS
X
ROC
X
X
X
X
Power-On
1
0
U
0
U
U
U
U
/RESET and WDT
1
0
U
0
U
U
U
U
Wake-Up from Pin Change
1
P
U
P
U
U
U
U
Bit Name
X
X
X
X
X
EXIE
ICIE
TCIE
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
U
U
U
U
U
0
0
0
Wake-Up from Pin Change
U
U
U
U
U
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
** To jump address 0x08, or to execute the instruction which is next to the “SLEP” instruction.
X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check Table 4
2. The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
This specification is subject to change without prior notice.
23
07.29.2004 (V1.2)
EM78P156N
OTP ROM
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P, listed in Table 4 are used to check how the processor wakes up. Table 5 shows the
events that may affect the status of T and P.
Table 6 The Values of RST, T and P after RESET
Reset Type
T
P
1
*P
1
0
0
1
1
*P
0
*P
0
0
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP mode
WDT during Operating mode
WDT wake-up during SLEEP mode
Wake-Up on pin change during SLEEP mode
*P: Previous status before reset
Table 7 The Status of T and P Being Affected by Events.
Event
SLEP instruction
1
0
Wake-Up on pin change during SLEEP mode
1
0
*P: Previous value before reset
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Fig. 9 Block Diagram of Controller Reset
This specification is subject to change without prior notice.
24
07.29.2004 (V1.2)
EM78P156N
OTP ROM
4.6 Interrupt
The EM78P156N has three falling-edge interrupts listed below:
(1) TCC overflow interrupt
(2) Port 6 Input Status Change Interrupt
(3) External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is
necessary. Each pin of Port 6 will have this feature if its status changed. Any pin configured as output or
P60 pin configured as /INT is excluded from this function. The Port 6 Input Status Changed Interrupt can
wake up the EM78P156N from the sleep mode if Port 6 is enabled prior to going into the sleep mode by
executing SLEP. When the chip wakes-up, the controller will continue to execute the succeeding
address if the global interrupt is disabled or branch to the interrupt vector 008H if the global interrupt is
enabled.
RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an
interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from
address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by
polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask
bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to
Fig. 10). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution
of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from
address 001H.
This specification is subject to change without prior notice.
25
07.29.2004 (V1.2)
EM78P156N
OTP ROM
VCC
P
R
D
/IRQn
CLK
C
L
Q
IRQn
INT
_
Q
IRQm
RFRD
RF
ENI/DISI
IOCF
Q
P
R
_
Q
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 10 Interrupt Input Circuit
4.7 Oscillator
1. Oscillator Modes
The EM78P156N can be operated in three different oscillator modes, such as External RC oscillator mode
(ERC), High XTAL oscillator mode (HXT), and Low XTAL oscillator mode (LXT). User can select one of them
by programming OSC and HLF in the CODE option register. Table 6 depicts how these three modes are
defined.
The up-most limited operation frequency of crystal/resonator on the different VDDs is listed in Table 7.
Table 8 Oscillator Modes Defined by OSC and HLP
Mode
ERC(External RC oscillator mode)
HXT(High XTAL oscillator mode)
LXT(Low XTAL oscillator mode)
OSC
HLF
HLP
0
1
1
*X
1
0
*X
*X
0
<Note> 1. X, Don’t care
2.The transient point of system frequency between HXT and LXY is around 400 KHz.
This specification is subject to change without prior notice.
26
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Table 9 The Summary of Maximum Operating Speeds
Conditions
VDD
Fxt max.(MHz)
3.0
8.0
5.0
20.0
Two cycles with two clocks
2. Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P156N can be driven by an external clock signal through the OSCI pin as shown in Fig. 11 below.
OSCI
Ext. Clock
OSCO
EM78P156N
Fig. 11 Circuit for External Clock Input
In the most applications, pin OSCI and pin OSCO can connected with a crystal or ceramic resonator to
generate oscillation. Fig. 12 depicts such circuit. The same thing applies whether it is in the HXT mode or in the
LXT mode. Table 8 provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be
necessary for AT strip cut crystal or low frequency mode.
C1
OSCI
EM78P156N
XTAL
OSCO
RS
C2
Fig. 12 Circuit for Crystal/Resonator
This specification is subject to change without prior notice.
27
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Ceramic Resonators
HXT
LXT
Crystal Oscillator
HXT
Frequency
455 kHz
2.0 MHz
4.0 MHz
32.768kHz
100KHz
200KHz
455KHz
1.0MHz
2.0MHz
4.0MHz
C1(pF)
100~150
20~40
10~30
25
25
25
20~40
15~30
15
15
C2(pF)
100~150
20~40
10~30
15
25
25
20~150
15~30
15
15
<Note> 1. The value of capacitors (C1, C2) is for reference.
3. External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 15) offers a lot
of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the
supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process
variation.
In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that
the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is
easily affected by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext
values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot discharge the current of
the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature,
the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system
frequency.
This specification is subject to change without prior notice.
28
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Vcc
Rext
OSCI
Cext
EM78P156N
Fig. 13 Circuit for External RC Oscillator Mode
Table 11 RC Oscillator Frequencies
Cext
Rext
20 pF
3.3k
5.1k
10k
100k
3.92 MHz
2.67 MHz
1.39MHz
149 KHz
3.65 MHz
2.60 MHz
1.40 MHz
156 KHz
100 pF
3.3k
5.1k
10k
100k
1.39 MHz
940 KHz
480 KHz
52 KHz
1.33 MHz
920 KHz
475 KHz
50 KHz
300 pF
3.3k
5.1k
10k
100k
595 KHz
400 KHz
200 KHz
21 KHz
560 KHz
390 KHz
200 KHz
20 KHz
Average Fosc 5V,25°C Average Fosc 3V,25°C
<Note> 1. Measured on DIP packages.
2. For design reference only.
3. The frequency drift is about ±30%
4.8 CODE Option Register
The EM78P156N has a CODE option word that is not a part of the normal program memory. The option
bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
This specification is subject to change without prior notice.
29
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Word 0
Bit12~Bit0
Word 1
Bit12~Bit0
1. Code Option Register (Word 0)
WORD 0
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
CLKS
ENWDTB
-
HLF
OSC HLP
PR2
PR1
PR0
• Bit 12 、11 、10 、9:Not used.
Reserved.
The bit set to “1” all the time.
• Bit 8 (CLKS): Instruction period option bit.
0: two oscillator periods.
1: four oscillator periods.
Refer to the section on Instruction Set.
• Bit 7(ENWDTB): Watchdog timer enable bit.
0: Enable
1: Disable
• Bit 6: Not used.
Reserved.
The bit set to “1” all the time.
• Bit 5 (HLF): XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit4 (OSC) is “1”. When OSC is”0”, HLF must be “0”.
<Note>: The transient point of system frequency between HXT and LXY is around 400 KHz.
• Bit 4 (OSC):Oscillator type selection.
0:RC type
1:XTAL type (XTAL1 and XTAL2)
• Bit 3 (HLP): Power selection.
0: Low power
1: High power
• Bit 2~0 (PR2~PR0): Protect Bit
PR2~PR0 are protect bits, protect type as following
PR2
0
0
0
PR1
0
0
1
PR0
0
1
0
Protect
Enable
Enable
Enable
This specification is subject to change without prior notice.
30
07.29.2004 (V1.2)
EM78P156N
OTP ROM
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Enable
Enable
Enable
Enable
Disable
2. Customer ID Register (Word 1)
Bit 12~Bit 0
XXXXXXXXXXXXX
• Bit 12~0: Customer’s ID code
4.9 Power On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its
steady state.
EM78156N POR voltage range is 1.2V~1.8V. Under customer application, when power is OFF, Vdd
must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way,
the EM78156E will reset and work normally. The extra external reset circuit will work well if Vdd can rise
at very fast speed (50 ms or less). However, under most cases where critical applications are involved,
extra devices are required to assist in solving the power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The pulse width (time
constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit is
used when the power supply has slow rise time. Because the current leakage from the /RESET pin is
about ±5µA, it is recommended that R should not be greater than 40 K. In this way, the /RESET pin
voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or
ESD (electrostatic discharge) from flowing to pin /RESET.
This specification is subject to change without prior notice.
31
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Vdd
R
/RESET
D
EM78P156N
Rin
C
Fig. 14 External Power-Up Reset Circuit
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage
may trips below Vdd minimum, but not to zero. This condition may cause a poor power on reset. Fig.18 and Fig.
19 show how to build a residue-voltage protection circuit.
Vdd
Vdd
33K
EM78P156N
Q1
10K
/RESET
40K
1N4684
Fig. 15 Circuit 1 for the Residue Voltage Protection
This specification is subject to change without prior notice.
32
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Vdd
Vdd
R1
EM78P156N
Q1
/RESET
40K
R2
Fig. 16 Circuit 2 for the Residue Voltage Protection
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands.
Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2
oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by
instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try
modifying the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ",
"DJZA") commands which were tested to be true, are executed within two instruction cycles.
The instructions that are written to the program counter also take two instruction cycles.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator clocks
if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal clock
source to TCC should be CLK=Fosc/4, instead of Fosc/ 2 as indicated in Fig. 5.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
(2) The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including operational
registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator
that selects the value for the bit which is located in the register "R", and affects operation. "k" represents an 8
or 10-bit constant or literal value.
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
STATUS AFFECTED
None
C
None
T,P
T,P
None <Note1>
None
None
None
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable
Interrupt
CONT → A
IOCR → A
A→R
0→A
0→R
R-A → A
0 0000 0001 0011
0013
RETI
0
0
0
0
0
0
0014
001r
00rr
0080
00rr
01rr
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z,C,DC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
0000
0000
0000
0000
0000
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0001
0001
01rr
1000
11rr
00rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
0100
rrrr
rrrr
0000
rrrr
rrrr
This specification is subject to change without prior notice.
34
None
None
None <Note1>
None
Z
Z
Z,C,DC
C
C
C
07.29.2004 (V1.2)
EM78P156N
OTP ROM
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 00kk kkkk kkkk
1kkk
CALL k
1
1
1
1
1
kkkk
kkkk
kkkk
kkkk
kkkk
1kkk
18kk
19kk
1Akk
1Bkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
1 1100 kkkk kkkk
1Ckk
RETL k
1 1101 kkkk kkkk
1Dkk
SUB A,k
1 1110 0000 0001
1E01
INT
1 1111 kkkk kkkk
1Fkk
ADD A,k
0111
0111
0111
100b
101b
110b
111b
01kk
1000
1001
1010
1011
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
kkkk
kkkk
kkkk
kkkk
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A,
[Top of Stack] → PC
k-A → A
PC+1 → [SP],
001H → PC
k+A → A
C
None
None
None
None
None <Note2>
None <Note3>
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
<Note 1> This instruction is applicable to IOC5~IOC6, IOCB~IOCF only.
<Note 2> This instruction is not recommended for RF operation.
<Note 3> This instruction cannot operate under RF.
This specification is subject to change without prior notice.
35
07.29.2004 (V1.2)
EM78P156N
OTP ROM
4.13 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
This specification is subject to change without prior notice.
36
07.29.2004 (V1.2)
EM78P156N
OTP ROM
5. ABSOLUTE MAXIMUNM RATINGS
EM78P156N
Items
Rating
Temperature under bias
-40°C to 85°C
Storage temperature
-65°C to 150°C
Working voltage
2.5 to 5.5V
Working frequency
DC to 20MHz*
Input voltage
Vss-0.3V to Vdd+0.5V
Output voltage
Vss-0.3V to Vdd+0.5V
*These parameters are characterized but not tested.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
6. ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
ERC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHX1
VILX1
VIH2
VIL2
VIHT2
VILT2
VIHX2
VILX2
Parameter
XTAL: VDD to 3V
XTAL: VDD to 5V
ERC: VDD to 5V
Input Leakage Current for input pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage (VDD=5V)
Input Low Threshold Voltage (VDD=5V)
Clock Input High Voltage (VDD=5V)
Clock Input Low Voltage (VDD=5V)
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage (VDD=3V)
Input Low Threshold Voltage (VDD=3V)
Clock Input High Voltage (VDD=3V)
Clock Input Low Voltage (VDD=3V)
Condition
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
VIN = VDD, VSS
Ports 5, 6
Ports 5, 6
/RESET, TCC(Schmitt trigger)
/RESET, TCC(Schmitt trigger)
OSCI
OSCI
Ports 5, 6
Ports 5, 6
/RESET, TCC(Schmitt trigger)
/RESET, TCC(Schmitt trigger)
OSCI
OSCI
VOH1
Output High Voltage (Ports 5)
IOH = -12.0 mA
2.4
V
VOH1
Output High Voltage (Ports 6)
(Schmitt trigger)
IOH = -12.0 mA
2.4
V
Output Low Voltage(Port5)
IOL = 12.0 mA
0.4
V
IOL = 12.0 mA
0.4
V
-70
50
-240
120
µA
µA
1
2
µA
15
µA
20
30
µA
25
35
µA
2.0
mA
4.0
mA
FXT
VOL1
IPH
IPD
Output Low Voltage (Ports 6)
(Schmitt trigger)
Pull-high current
Pull-down current
ISB1
Power down current
ISB2
Power down current
VOL1
ICC1
ICC2
ICC3
ICC4
Operating supply current
(VDD=3V)
at two cycles/four clocks
Operating supply current
(VDD=3V)
at two cycles/four clocks
Operating supply current
(VDD=5.0V)
at two cycles/two clocks
Operating supply current
(VDD=5.0V)
at two cycles/four clocks
Pull-high active, input pin at VSS
Pull-down active, input pin at VDD
All input and I/O pins at VDD,
output pin floating, WDT disabled
All input and I/O pins at VDD,
output pin floating, WDT enabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output
pin floating, WDT disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output
pin floating, WDT enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
Min
Typ.
DC
DC
F±30% 940
Max
8.0
20.0
F±30%
±1
2.0
0.8
2.0
0.8
3.5
1.5
1.5
0.4
1.5
0.4
2.1
0.9
-50
25
15
Unit
MHz
MHz
KHz
µA
V
V
V
V
V
V
V
V
V
V
V
V
* These parameters are characterizes but not tested.
This specification is subject to change without prior notice.
38
07.29.2004 (V1.2)
EM78P156N
OTP ROM
6.2 AC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Dclk
Tins
Ttcc
Tdrh
Trst
Twdt
Tset
Thold
Tdelay
Parameter
Input CLK duty cycle
Instruction cycle time
(CLKS="0")
TCC input period
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
Conditions
Crystal type
RC type
Ta = 25°C
Ta = 25°C
Cload=20pF
Min
45
100
500
(Tins+20)/N*
11.8
2000
11.8
Typ
50
Max
55
DC
DC
16.8
21.8
16.8
0
20
50
21.8
Unit
%
ns
ns
ns
ms
ns
ms
ns
ns
ns
* N= selected prescaler ratio.
* These parameters are characterizes but not tested.
This specification is subject to change without prior notice.
39
07.29.2004 (V1.2)
EM78P156N
OTP ROM
6.3 Device Characteristic
The graphs provided in the following pages were derived based on a limited number of samples and are
shown here for reference only. The device characteristic illustrated herein are not guaranteed for it accuracy.
In some graphs, the data maybe out of the specified warranted operating range.
Vih/Vil (Input pins with schmitt inverter)
2.5
Vih max (-40℃ to 85℃)
Vih typ 25℃
Vih min (-40℃ to 85℃)
Vih/Vil (Volt)
2
1.5
1
Vil max (-40℃ to 85℃)
Vil typ 25℃
Vil min (-40℃ to 85℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 17 Vih, Vil of Port6 vs. VDD
This specification is subject to change without prior notice.
40
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Vth (Input thershold voltage) of I/O pins
2
Vth (Volt)
1.5
Max(-40℃ to 85℃)
Typ 25℃
1
Min(-40℃ to 85℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 18 Vth (Threshold voltage) of Port5 vs. VDD
This specification is subject to change without prior notice.
41
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Voh/Ioh (3V)
0
0
-5
-2
Min 85℃
-10
Min 85℃
-4
Ioh (mA)
Ioh (mA)
Voh/Ioh (5V)
Typ 25℃
Typ 25℃
-6
-15
Min -40℃
Min -40℃
-20
-8
-25
-10
1.5
2
2.5
3
3.5
4
4.5
5
Voh (Volt)
Fig. 19 Port5 and Port6 Voh vs. Ioh, VDD=5V
0
0.5
1
1.5
2
2.5
3
Voh (Volt)
Fig. 20 Port5 and Port6 Voh vs. Ioh, VDD=3V
EM78P156N
OTP ROM
Vol/Iol (5V)
Vo l/Io l (3 V)
100
45
Max -40℃
Max -40℃
90
40
80
35
Typ 25℃
70
Typ 25℃
30
Iol (mA)
Iol (mA)
60
Min 85℃
50
25
Min 85℃
20
40
15
30
10
20
5
10
0
0
0
0.5
1
1.5
2
2.5
0
3
Vol (Volt)
1
1.5
2
2.5
3
Vol (Volt)
Fig. 21 Port5, Port6 Vol vs. Iol, VDD = 5V
This specification is subject to change without prior notice.
0.5
Fig. 22 Port5, Port6 Vol vs. Iol, VDD = 3V
43
07.29.2004 (V1.2)
EM78P156N
OTP ROM
WDT Time out
45
40
35
Max 85℃
WDT period(mS)
30
Max 70℃
25
Typ 25℃
20
Min 0℃
15
Min -40℃
10
5
0
2
3
4
5
VDD (Volt)
Fig. 23 WDT time out period vs. VDD,
perscaler set to 1:1
6
EM78P156N
OTP ROM
Cext = 100pF, Typical RC Frequency vs. VDD
1.6
R = 3.3K
1.4
Frequency (M Hz)
1.2
R = 5.1K
1
0.8
0.6
R = 10K
0.4
0.2
R = 100K
0
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 24 Typical RC OSC Frequency vs. VDD
(Cext= 100pF, Temperature at 25℃)
VDD = 5V
VDD = 3V
Fig. 25 Typical RC OSC Frequency vs. VDD (R and C are ideal components)
This specification is subject to change without prior notice.
45
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows:
ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable
ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enable
ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enable
ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enable
Typical ICC1 and ICC2 vs. Temperature
15
Current (uA)
12
Typ ICC2
9
Typ ICC1
6
3
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 26 Typical operating current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
21
Current (uA)
18
15
Max ICC2
12
Max ICC1
9
6
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 27 Maximum operating current (ICC1 and ICC2) vs. Temperature
This specification is subject to change without prior notice.
46
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Typical ICC3 and ICC4 vs. Temperature
4
Current (mA)
3.5
Typ ICC4
3
2.5
2
Typ ICC3
1.5
1
0.5
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 28 Typical operating current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Max ICC4
Current (mA)
4
3.5
3
2.5
Max ICC3
2
1.5
1
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 29 Maximum operating current (ICC3 and ICC4) vs. Temperature
This specification is subject to change without prior notice.
47
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as follows:
ISB1: VDD=5V, WDT disable
ISB2: VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
12
Current (uA)
10
Typ ISB2
8
6
4
Typ ISB1
2
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 30 Typical standby current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
12
Max ISB2
Current (uA)
10
8
6
4
Max ISB1
2
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 31 Maximum standby current (ISB1 and ISB2) vs. Temperature
This specification is subject to change without prior notice.
48
07.29.2004 (V1.2)
EM78P156N
OTP ROM
Fig. 32 Operating voltage in temperature range from 0℃ to 70℃
Fig. 33 Operating voltage in temperature range from -40℃ to 85℃
This specification is subject to change without prior notice.
49
07.29.2004 (V1.2)
EM78P156N
OTP ROM
EM78P156N-J HXT V-I
2.5
2.25
2
I(mA)
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 34 Operating current range (based on high Freq. @ =25℃) vs. Voltage
EM78P156N-J LXT V-I
35
30
I(uA)
25
20
15
10
5
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 35 Operating current range (based on low Freq. @ =25℃) vs. Voltage
This specification is subject to change without prior notice.
50
07.29.2004 (V1.2)
EM78P156N
OTP ROM
EM78P156N-G HXT V-I
2.5
2.25
2
1.75
I(mA)
1.5
1.25
1
0.75
0.5
0.25
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 36 Operating current range (based on high Freq. @ =25℃) vs. Voltage
EM78P156N-G LXT V-I
40
35
30
I(uA)
25
20
15
10
5
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 37 Operating current range (based on high Freq. @ =25℃) vs. Voltage
This specification is subject to change without prior notice.
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EM78P156N
OTP ROM
APPENDIX
Package Types:
OTP MCU
EM78P156NP
EM78P156NM
Package Type
DIP
SOP
Pin Count
18
18
Package Size
300 mil
300 mil
EM78156NAS
SSOP
20
209 mil
EM78156NKM
SSOP
20
209 mil
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Package Information
18-Lead Plastic Dual in line (PDIP) — 300 mil
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
18-Lead Plastic Small Outline (SOP) — 300 mil
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
20-Lead Plastic Small Outline (SSOP) — 209 mil
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
Quality Assurance And Reliability
Test category
Test conditions
Solderability
Solder temperature=245±5℃，for 5 seconds up to the stopper
using a rosin-type flux
Pre-condition
Step1: TCT ，65℃(15mins)~150℃(15mins)，10 cycles
Remarks
For SMD IC(such as
SOP、QFP、SOJ…etc)
Step2: bake 125℃，TD(durance)=24 hrs
Step3:soak 30°C /60%，TD(durance)=192hrs
Step4:IR flow 3cycles
(Pkg thickness≧2.5mm or Pkg volume≧350mm3 ----225±5℃)
(Pkg thickness≦2.5mm or Pkg volume≦350mm3 ----240±5
℃)
Temperature cycle test -65℃(15mins)~150℃(15mins) , 200 cycles
Pressure cooker test
TA =121℃,RH=100%,pressure=2atm, TD(durance)= 96 Hrs
High temperature /high
TA=85℃ , RH=85%，TD(durance)=168 ,500 Hrs
humidity test
High-temperature
storage life
TA=150℃, TD(durance)=500,1000Hrs
High-temperature
operating life
TA=125 ℃ , VCC=Max. operating voltage, TD(durance)
=168,500,1000Hrs
Latch-up
TA=25℃, VCC=Max. operating voltage, 150mA/20V
ESD(HBM)
TA=25℃, ≧∣±3KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
ESD(MM)
TA=25℃, ≧∣±300V∣
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
VDD-VSS(+),VDD_VSS
(-)mode
This specification is subject to change without prior notice.
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EM78P156N
OTP ROM
Vdd
/Rese
Tvr
Tvd
Internal
POR
Power
Tpor
on
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Tpor
Power on reset time
Vdd = 5V, -40℃ to 85℃
10.5
16.8
22
ms
Tvd
Vdd Voltage drop time
Vdd = 5V, -40℃ to 85℃
-
-
1*
us
Tvr
Vdd Voltage rise time
Vdd = 5V, -40℃ to 85℃
-
-
1**
us
* Tvd is the period of Vdd voltage less than POR voltage.
** Tvr is the period of Vdd voltage higher than 5.5 volts.
Address Trap Detect
An address trap detect is one of the fail-safe function that detects CPU malfunction caused by noise or the like.
If the CPU attempts to fetch an instruction from a part of RAM, an internal recovery circuit will auto started. Until
CPU got the correct function, it will execute the following program.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)
EM78P156N
OTP ROM
ELAN (HEADQUARTER) MICROELECTRONICS CORP., LTD.
Address : No. 12, Innovation 1st. Rd. Science-Based Industrial Park, Hsinchu City, Taiwan.
Telephone: 886-3-5639977
Facsimile : 886-3-5639966
ELAN (H.K.) MICROELECTRONICS CORP., LTD.
Address : Rm. 1005B, 10/F, Empire Centre, 68 Mody Road, Tsimshatsui, Kowloon, Hong Kong.
Telephone: 852-27233376
Facsimile : 852-27237780
E-mail : [email protected]
ELAN MICROELECTRONICS SHENZHEN, LTD.
Address : SSMEC Bldg. 3F , Gaoxin S. Ave. 1st , South Area , Shenzhen High-tech Industrial Park., Shenzhen
Telephone: 86-755-26010565
Facsimile : 86-755-26010500
ELAN MICROELECTRONICS SHANGHAI, LTD.
Address : #23 Building No.115 Lane 572 BiBo Road. Zhangjiang, Hi-tech Park, Shanghai
Telephone: 86-21-50803866
Facsimile : 86-21-50804600
Elan Information Technology Group.
Address: 1821 Saratoga Avenue, suite 250, Saratoga, CA 95070, USA
Telephone: 1-408-366-8225
Facsimile : 1-408-366-8220
Elan Microelectronics Corp. (Europe)
Address: Dubendorfstrasse 4, 8051 Zurich, Switzerland
Telephone: 41-43-2994060
Facsimile : 41-43-2994079
Email : [email protected]
Web-Site : www.elan-europe.com
Copyright © 2004 ELAN Microelectronics Corp. All rights reserved.
ELAN owns the intellectual property rights, concepts, ideas, inventions, know-how (whether patentable
or not) related to the Information and Technology (herein after referred as " Information and
Technology") mentioned above, and all its related industrial property rights throughout the world, as now
may exist or to be created in the future. ELAN represents no warranty for the use of the specifications
described, either expressed or implied, including, but not limited, to the implied warranties of
merchantability and fitness for particular purposes. The entire risk as to the quality and performance of
the application is with the user. In no even shall ELAN be liable for any loss or damage to revenues,
profits or goodwill or other special, incidental, indirect and consequential damages of any kind, resulting
from the performance or failure to perform, including without limitation any interruption of business,
whatever resulting from breach of contract or breach of warranty, even if ELAN has been advised of the
possibility of such damages.
The specifications of the Product and its applied technology will be updated or changed time by time. All
the information and explanations of the Products in this website is only for your reference. The actual
specifications and applied technology will be based on each confirmed order.
ELAN reserves the right to modify the information without prior notification. The most up-to-day
information is available on the website http://www.emc.com.tw.
This specification is subject to change without prior notice.
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07.29.2004 (V1.2)