TI TLC976C

TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
D
D
D
D
Correlated Double Sampling (CDS), AGC
and High Speed 10-Bit ADC in a Single
Package
5-V Analog Power Supply and 3.3-V Digital
Power Supply
Power Down Mode
56-Pin TSSOP (DGG) Package with
Multichip Module Assembly for Isolation
CDS/AGC
D
D
D
D
AGC Gain Range of 5 dB to 39 dB
Black Level Clamp Circuit
Direct Connection to ADC Input
Voltage Reference for ADC
Analog-to-Digital Converter
D
D
D
D
D
10-Bit Resolution
Maximum Conversion Rate . . . 20 MSPS
(MIN)
Differential Nonlinearity . . . 0.75 LSB (TYP)
Analog Input Voltage Range of 2 Vp-p
3.3 V CMOS Digital Interface
Applications
D
D
D
D
PC Camera
Digital Camera
Camcorder
CCD Scanner
DGG PACKAGE
(TOP VIEW)
SHV
GND1
BLK-PULSE
OFFSET
VCC3
DRIVE-OUT
GND3
CDS-STBY
VRB-OUT
VRT-OUT
A-SUB
D-SUB
DVSS
D0
D1
D2
D3
D4
DVSS
DVDD
D5
D6
D7
D8
D9
RESET
DVSS
AVDD
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
SHR
VCC1
CLP2
DATA-IN
PIN
AGCGAIN
OBCLP
AGCCLP
SH-PULSE
GND2
VCC2
A-SUB
DVDD
AVSS
AVSS
VIN
D-SUB
AVSS
VRB-IN
VRB-IN
VRT-IN
VRT-IN
AVSS
AVDD
AVDD
AD-STBY
OE
CLK
description
The TLC976 is a multichip module (MCM) subsystem designed for interfacing Charge-Coupled Device (CCD)
in camcorder and digital camera systems. The TLC976 includes correlated double sampler (CDS), automatic
gain control (AGC), black level clamp circuit, 10 bit, 20 MSPS analog-to-digital converter (ADC), and internal
reference voltage generator for ADC.
The CDS/AGC can be connected directly to the ADC input or a separate signal can be connected directly to
the ADC input. A power-down mode is provided.
Assembled using the MCM process, the TLC976 provides isolation between the noisy digital domain and the
noise sensitive analog signals. The CDS/PGA, black level clamps are on one die and the ADC is on a separate
die. The separate dies significantly reduce the substrate noise to the analog section.
The TLC976 comes in a 56-pin TSSOP package with 0,50 mm pin pitch. This is about 25% smaller than using
two separate 32-pin quad flat packs (QFP).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
functional block diagram
SHR
SHV
AGCGAIN
AGCCLP OBCLP
AGCCLP
SH-PULSE
PIN
SH
SH
LPF
SH
AGC
BLK-PULSE
BLK
SH
DATA-IN
CLP1
VRB
VRB-OUT
VRT
VRT-OUT
CLP2
CLP2
CDS-STBY
OFFSET
DRV
DRIVE-OUT
Auto
Calibration
Circuit
D9
D8
D7
Upper
Data
Latch
D3
D2
Upper
Sampling
Comparators
Upper
Data
Latch
S&H
VIN
+
D6
D5
D4
RESET
DAC
–
Lower
Data
Latch
Lower
Data
Latch
D1
D0
Lower
Sampling
Comparators
VRT-IN
Reference
Voltage
VRB-IN
Clock
Generator
CLK
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
AD-STBY
OE
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AD-STBY
31
I
ADC standby mode
L level in operation
AGCCLP
49
I
AGC clamp capacitor (connect 0.1 µF to GND)
51
I
AGC gain control
AGCGAIN
A-SUB
11, 45
AVDD
28, 32, 33
ADC analog power supply
AVSS
34, 39, 42,
43
Analog GND for ADC
H level in standby mode
Analog GND
BLK-PULSE
3
I
DRIVE-OUT terminal is clamped to 1.66 V internally when BLK-PULSE = L.
CDS-STBY
8
I
CDS/AGC standby mode control
L level in operation
H level in standby mode
CLK
29
I
CLK input for ADC
CLP2
D0–D9
DATA-IN
DRIVE-OUT
54
I
CCD signal clamp control input
14–18,
21–25
O
Digital data output, D0 (pin 14): LSB, D9 (pin 25): MSB
53
I
CCD signal input
6
O
CDS/AGC output
D-SUB
12, 40
Analog GND
DVDD
20, 44
ADC digital power supply
DVSS
13, 19, 27
GND1
2
GND2
47
Digital GND for ADC
I
CDS/AGC analog GND
CDS/AGC analog GND
GND3
7
OBCLP
50
I
Control input for clamping optical black level after AGC
OE
30
I
ADC output enable
L level in operation
OFFSET
4
GND for CDS output circuit
I
H level in Hi-Z
CDS/AGC output offset control:
DC voltage at OFFSET pin
0V
0.5 V
3V
DRIVE-OUT offset
– 450 mV
– 280 mV
550 mV
PIN
52
I
CCD signal input
RESET
26
I
Reset for calibration circuit. Restart of startup calibration.
SHV
1
I
CCD signal level sample clock input
SH-PULSE
48
I
Sample and hold pulse input
SHR
56
I
CCD reset level sample clock input
VCC1
55
CDS/AGC analog power supply
VCC2
46
CDS/AGC analog power supply
VCC3
5
VIN
41
I
ADC analog signal input
VRB-OUT
VRB-IN
VRT-OUT
VRT-IN
CDS/AGC analog power supply
9
O
ADC bottom reference voltage output (1.5 V typ)
37, 38
I
Connect to VRB-OUT
10
O
ADC top reference voltage output (3.5 V typ)
35, 36
I
Connect to VRT-OUT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Analog supply voltage, VCC1, VCC2, VCC3, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 V to 7 V
Digital supply voltage, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 V to 7 V
Analog input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.4 V to AVCC1, 2,3 + 0.5 V
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 mW
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 10.75 mW/°C.
recommended operating conditions
MIN
Analog supply voltage, VCC1, VCC2, VCC3, AVDD
ADC digital output supply voltage, DVDD
Difference, AGND to DGND
NOM
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
100
mV
–100
High-level input voltage
2
V
Low-level input voltage
0.8
ADC analog input voltage full scale range
ADC CLK pulse width
2
High level
25
Low level
25
Operating temperature
V
V
ns
0
70
°C
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted)
total device
PARAMETER
TEST CONDITIONS
AGCGAIN = 0 V,
STBY = 0 V
CDS/AGC supply current
ADC supply current
4
Digital supply
Analog supply
VRT = VRB = Open,
NTSC ramp input
MIN
TYP
MAX
30
38
3
6
32
35
UNIT
mA
mA
CDS/AGC standby current
CDS-STBY = High
5.6
11
mA
ADC standby current
AD-STBY = HIGH,
CDS STBY = HIGH,
(VIN = VRT-IN = VRB-IN = Hi-Z)
0.5
1
mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted) (continued)
CDS input/AGC
PARAMETER
TEST CONDITIONS
MIN
Input signal clamp voltage
Input current for SHR,
SHR SHV,
SHV CLP2
AGC gain
TYP
MAX
2.7
High input
VIN = 3 V
Low input
VIN = 0 V
Minimum
AGCGAIN = 0 V
Maximum
AGCGAIN = 3 V
34
UNIT
V
1
A
–1
µA
5
7
37
39
dB
High-level input current, OBCLP, BLK pulse
1
µA
Low-level input current, OBCLP, BLK pulse
–1
µA
CDS input clock frequency
20
MHz
driver output
PARAMETER
TEST CONDITIONS
Output offset voltage
High
OFFSET = 3 V
Low
OFFSET = 0 V
Internal black level
MIN
TYP
MAX
UNIT
0.55
0.65
V
– 0.35
– 0.45
1.36
1.66
Nominal signal voltage at DRIVE-OUT
V
1.96
2
V
Vp-p
reference voltage
PARAMETER
VRT output voltage
VRB output voltage
TEST CONDITIONS
300 Ω,
Ω AVDD = VCC1–
VCC1 3 = 4.75
4 75 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
3.47
3.50
3.53
V
1.45
1.50
1.55
V
5
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25°C (unless
otherwise noted) (continued)
A/D converter
PARAMETER
TEST CONDITIONS
Integral non-linearity
Fs = 20 MSPS,
MIN
VIN = 1.8 V – 3.8 V
Differential non-linearity
TYP
MAX
UNIT
±1.5
±2.5
LSB
±0.75
±1.25
LSB
Analog input capacitance
10
pF
Reference voltage output current
6.5
mA
300
Ω
Zero scale offset error
20
mV
Full scale offset error
20
mV
Reference voltage output impedance
(VRT IN – VRB IN)
High-level input current
DVDD = MAX,
Low-level input current
DVDD = MAX,
VIH = DVDD
VIL = 0 V
High-level output current
OE = GND,
VOH = DVDD – 0.5 V
DVDD = MIN,
Low-level output current
OE = GND,
VOL = 0.4 V
DVDD = MIN,
High-level output voltage
DVDD = 3 V – 5.25 V,
IOH = 2 mA
Low-level output voltage
DVDD = 3 V – 5.25 V,
High-level output leakage current
OE = DVDD,
VOH = DVDD
IOL = 1 mA
DVDD = MAX,
Low-level output leakage current
OE = DVDD,
VOL = 0 V
µA
10
µA
3
mA
5
mA
VDD–
0.7V
V
DVDD = MIN,
DVDD–DGND
Automatic starting calibration voltage
10
0.8
V
1
µA
1
µA
2.5
VRT–VRB
V
1
A/D converter operating characteristics
PARAMETER
Sampling rate
TEST CONDITIONS
VIN = 1.8 V – 3.8 V,
Fin = 1 kHz ramp
MIN
Analog input bandwidth (– 3 dB)
Data output, propagation delay
Differential gain
Differential phase
6
MAX
UNIT
20
MSPS
10
CL = 20 pF
3 MSPS
NTSC 40 IRE mod ramp
ramp, FS = 14
14.3
Sampling delay time
Signal to noise ratio
TYP
0.5
Fin = 1 MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MHz
ns
1%
0.3
Degree
5
ns
55
dB
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
TYPICAL CHARACTERISTICS
AGCGAIN
vs
VOLTAGE
45
40
AGCGAIN – dB
35
30
25
20
15
10
5
0
0
0.3 0.6 0.9
1.2 1.5 1.8
2.1 2.4
2.7
3
AGCGAIN – V
Figure 1. AGC Characteristics
OUTPUT OFFSET VOLTAGE
vs
OFFSET CONTROL VOLTAGE
0.6
0.5
DRIVE OUT Offset Voltage
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1
1.5
2
2.5
Control Voltage at OFFSET Pin (V)
3
Figure 2. OFFSET IN Terminal Input/Output Characteristics
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
TYPICAL OPERATION
Optical Black
Pixel Period
Dummy Black/Blanking Period
Signal Period
CCD Reset Feedthrough
CCD Reset Level
CCD Signal Level
CCD Input
SHR Input
SHV Input
2 µs
(typ)
CLP2 Input
(Internal)
AGC Output
Optical Black Level
1.66 V
Black Level
SH-Pulse
(Input)
OBCLP Input
1.66 V
(Internal) BLK
10 µs
(typ)
BLK-PULSE
(Input)
1.66 V
DRIVE-OUT
(Output)
Figure 3. CCD Input Mode Timing Diagram
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
APPLICATION INFORMATION
AVDD
0.1 µF
1
2
GND1
VCC1
3
4
5
6
0.1 µF
7
8
52
VCC3
51
50
GND3
49
9
12
13
14
AGND
48
GND2
A-SUB
VCC2
A-SUB
D-SUB
DVSS
DVDD
AVSS
AVSS
15
16
17
D-SUB
18
19
20
0.1 µF
21
AVSS
DVSS
0.1 µF
46
45
44
43
42
41
40
39
38
36
35
23
AVSS
24
AVDD
AVDD
25
26
28
47
37
DVDD
22
27
54
53
10
11
56
55
34
33
0.1 µF
32
31
30
DVSS
29
AVDD
DGND
DVDD
NOTE A: A-SUB and D-SUB should be connected to Analog GND.
Figure 4. Typical Connection Diagram
Table 1. Standby, Output Enable
PIN
PIN NAME
8
CDS-STBY
31
AD-STBY
30
OE
FUNCTION
OPERATION
STAND-BY OR DISABLE
Standby mode for CDS/AGC
L
H
Standby mode for AD converter
L
H
AD output
L
H
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• DALLAS, TEXAS 75265
9
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
APPLICATION INFORMATION
0.1 µF
AGCCLP
SHR
CCD-IN
SHV
AGCGAIN
OBCLP
AGCCLP
1 µF
SH-PULSE
PIN
SH
SH
LPF
SH
AGC
DATA-IN
BLK-PULSE
BLK
SH
1 µF
VRB-OUT
CLP1
VRB
VRT
CLP2
VRT-OUT
CLP2
CDS-STBY
DRV
OFFSET-IN
DRIVE-OUT
Auto
Calibration
Circuit
D9
D8
Upper
Data
Latch
D7
Upper
Data
Latch
RESET
Upper
Sampling
Comparators
S&H
VIN
D6
DAC
D5
D4
D3
D2
+
(see Note A)
–
Lower
Data
Latch
Lower
Data
Latch
Lower
Sampling
Comparators
VRT-IN
D1
Reference
Voltage
D0
Clock
Generator
CLK
NOTE A: The 0.1 µF capacitors are necessary when you need to protect the noise.
Figure 5. Typical Application
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VRB-IN
AD-STBY
OE
(see
Note A)
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
CDS/AGC signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled
and held during both the reset reference interval and the video signal interval. By subtracting two resulting
voltage levels, the CDS removes low frequency noise from the output of the CCD sensor. Two sample/hold
control pulses (SHR and SHV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLC976. The AC coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLP2 input. The bias at the input to the TLC976 is set
to 2.7 V at VCC = 4.75 V. Normally, the CLP2 is applied at the sensor’s line rate.
The signal is sent to AGC after the CDS function is complete. The AGC gain can be adjusted from 5 dB to 39
dB by applying variable dc voltage from 0 V to 3 V at the AGCGAIN terminal.
A low-pass filter is installed at the AGC output to improve signal-to-noise ratio. After its output settles, it is
sampled and held by the SH-PULSE input for digitization. The SH-PULSE should synchronize with the ADC
clock.
The basic black level reference is established by clamping the AGC output to 1.66 V internally by the OBCLP
input during the optical black pixel period. A capacitor of 0.1 µF should be connected to the AGCCLP pin.
To prevent the black level from falling below the basic black level (1.66 V) during the blanking period, the AGC
output level is kept at 1.66 V by the BLK PULSE input. It is recommended that the BLK PULSE be kept low during
the entire blanking period.
The DRV block drives the ADC and adjusts the signal offset at the DRIVE OUT output. The offset can be
adjusted from –450 mV to 550 mV by applying control voltage on the OFFSET pin.
The VRT (3.5 V) and VRB (1.5 V) outputs provide voltage references for the ADC. They should be connected
to the VRT-IN and VRB-IN input pins externally.
analog-to-digital converter (ADC)
The A/DC in the TLC976 performs high-speed analog-to-digital conversion with 10-bit resolution using
semi-flash technique. The latency of the data output valid is 2.5 clocks.
Table 2. ADC Output Code
INPUT VOLTAGE
STEPS
VRT
•
•
•
•
•
•
•
•
•
•
VRB
0
•
•
•
•
511
512
•
•
•
•
1023
POST OFFICE BOX 655303
DIGITAL OUTPUT CODE
MSB
LSB
1111111111
•
•
•
•
1000000000
0111111111
•
•
•
•
0000000000
• DALLAS, TEXAS 75265
11
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
twh
twl
CLOCK
N+2
INPUT SIGNAL
DATA OUTPUT
N
N+3
N–3
N–2
N–1
tpd
Figure 6. ADC Operation Sequence
12
N+4
N+1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
N
N+1
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
ADC internal calibration
start-up calibration at power up
After power is turned on, the start-up calibration starts under the following conditions:
1. The voltage between VRT and VRB is over 1 V when the voltage between AVDD and AVSS is over 2.5 V.
2. The voltage between DVDD and DVSS is over 2.5 V.
3. The RESET terminal (pin 26) is high.
4. The AD-STBY terminal (pin 31) is low.
The calibration sequence starts after condition 2 is met (see Figure 7). The following equation calculates the
time required for the start-up calibration after the above conditions are met.
Start-up calibration time = main clock pulse period × 16 × 16384
For example, if the main clock frequency is 15 MHz, the time required for startup calibration is 17.5 ms.
Reset = HIGH, AD-STBY = LOW
5V
AVDD
VRT
DVDD
2.5 V
1V
VRB
CALIBRATION START
Figure 7. Start-Up Calibration
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
start-up calibration using RESET terminal
If start-up characteristics are not stable, the start-up calibration can be performed using the AD-STBY terminal
(pin 31) or the RESET terminal (pin 26). Start-up calibration can be initiated properly by connecting RC
components to the RESET pin as shown in Figure 8. The RC components delay the start-up until the supply
voltage stablizes.
AVDD
M
AVDD
VRT
R
RESET
RESET
26
C
VRB
AVSS
(t)
Figure 8. Start-Up Calibration Using RESET Terminal
14
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TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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15
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLC976CDGG
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
TLC976CDGGR
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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