PIXART PAC407BCA

PAC407BCA/PAC407BCW
CMOS Image Sensor IC
PAC407 CMOS VGA DIGITAL IMAGE SENSOR
General Description:
The PAC407 is a highly integrated CMOS active-pixel image sensor that has a VGA resolution (644H x 484V or
640H x 480V). The PAC407 outputs 8-bit data with wide range of formats include RGB Raw Data, RGB565 and
YCbCr422 through an 8-bit parallel data bus. It is available in 32-pin LCC and 22-pin CSP.
To have an excellent image quality, the PAC407 supports all require image processing functions, includes
Automatic Exposure Control, Automatic White Balance, Gamma Correction, Color Saturation Correction, Edge
Enhancement, Lens Shading Compensation and Defect Compensation. These functions are all programmable via
I 2 CTM serial control bus.
Features:
ƒ VGA, QVGA, QQVGA (Sub-sampling) and
Window Of Interest (WOI) outputs with 8-bit
parallel data mode, the formats include:
ƒ <25mA(~15 fps) power dissipation
ƒ I 2 CTM Serial Interface
ƒ Pin-to-pin compatible to OV7648
o Raw Data
(Except for the polarity of RESET pin)
o RGB565
Key Specification:
o YCbCr422
ƒ VGA resolution, ~1/4” Lens
Supply Voltage
2.8V to 3.3V
o 644 x 484 pixels (Raw Data)
ƒ Bayer-RGB color filter array
Array diagonal
ƒ Continuous variable frame time(1/2sec~1/30sec)
ƒ On-chip 10-bit pipelined A/D converter
ƒ On-chip programmable gain amplifier
o 4-bit color gain amplifier (x1~x2)
640x480(YUV) or 644x484(Raw)
Resolution
o 640 x 480 pixels (YUV/RGB)
4.5mm (~1/4”Optic)
5.6µmx5.6µm
Pixel Size
~30 fps
Frame rate
Up to 26 MHz
System clock
o 4-bit global gain amplifier (x1~x2)
ƒ Automatic image control functions:
o AEC: Automatic Exposure Control
Sensitivity
o AWB: Automatic White Balance
ƒ Image quality control:
o Color Saturation
BCA
BCW
o Smooth filter for skin
Exposure Time
ƒ X Flip Function for mirrored image
~ 4us to 0.1412s
Progressive
Scan Mode
> 45 dB
S/N Ratio
ƒ Defect Compensation
ƒ Lens Shading Compensation
1.4 V/Lux-Sec
1.2 V/Lux-Sec
RGB Bayer Pattern
Color filter
o Gamma Correction
o Sharpness (Edge Enhancement)
26 MHz
Max. pixel rate (YUV)
Package
BCA
BCW
32-pin LCC
22-pin CSP
Note1: Only 2 decouple-capacitors needed.
Note2: Excellent sensitivity.
ƒ Digital Zoom (x2, x4)
Version 1.7, 13 Sep
2004
E-mail: [email protected]
PixArt Imaging Inc.
1
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
1. Pin Assignment
1.1. PAC407BCW pin assignment
PXD5
PXD7
15
13
11
9
7
PXD6
VSSD
SYSCLK
PXCK
VSYNC
14
12
10
8
6
PXD4
16
RESET# VDDMA/MD HSYNC
PAC407 BCW
-- Top View --
VCC
5
PXD3
PXD1
SCL
VDDA
VREF
17
19
21
2
4
PXD2
PXD0
SDA
VSSA
CSB
18
20
22
1
3
Figure 1.1. PAC407BCW pin assignment
Pin No.
Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSSA
VDDA
PWDN
VREF
VCC
VSYNC
HSYNC
PXCK
VDDMA/MD
SYSCLK
RESET#
VSSD
PXD7
PXD6
PXD5
PXD4
PXD3
PXD2
PXD1
PXD0
SCL
SDA
GND
PWR
IN
IN
PWR
OUT
OUT
OUT
PWR
IN
IN
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
I/O
Analog ground.
Connected with a 0.1uF capacitor
Power Down (chip power down when high).
Internal voltage reference.
N.C.
Vertical synchronization signal.
Horizontal synchronization signal.
Pixel clock output.
Main Power (include IO pad power), 2.8V to 3.3V.
Master clock input.
Resets all registers to their default values (chip reset when low).
Digital ground.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
I 2 CTM clock.
I 2 CTM data. Internal pull high resister is 10KΩ.
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2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
PX5
VSSD
PX7
SCLK
RESET#
PXCK
VDDMD
VSYNC
1.2. PAC407BCA
12
11
10
9
8
7
6
5
VHRST
13
4
HSYNC
VLRST
14
3
VPN
PX6
15
VCC
PX4
2
VPP
16
PAC407 BCA
1
VDDMA
17
-- Top View --
32
VRT
VREF
21
22
23
24
25
26
27
28
VRB
PWDN
VSSA
29
VCM
NC
SDA
VDDA
20
SCL
30
PX0
NC
19
PX1
18
PX2
PX3
31
Figure 1.2. PAC407BCA pin assignment
Pin No.
Name
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDMA
VPP
VPN
HSYNC
VSYNC
VDDMD
PXCK
RESET#
SCLK
PX7
VSSD
PX5
VHRST
VLRST
PX6
VCC
PX4
PX3
NC
NC
PX2
PX1
PX0
SCL
PWR
BYPASS
BYPASS
OUT
OUT
PWR
OUT
IN
IN
OUT
GND
OUT
BYPASS
BYPASS
OUT
PWR
OUT
OUT
OUT
OUT
OUT
IN
Version 1.7, 13 Sep
2004
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Description
Main analog power, 2.8V to 3.3V.
Analog test output P
Analog test output N
Horizontal synchronization signal.
Vertical synchronization signal.
Main digital power (include IO pad power), 2.8V to 3.3V.
Pixel clock output.
Resets all registers to their default values (chip reset when low).
Master clock input.
Digital data out.
Digital ground.
Digital data out.
Test pin
Test pin
Digital data out.
N.C.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
Digital data out.
I 2 CTM clock.
PixArt Imaging Inc.
3
PAC407BCA/PAC407BCW
25
26
27
28
29
30
31
32
SDA
VCM
VSSA
VRB
PWDN
VDDA
VREF
VRT
I/O
BYPASS
GND
BYPASS
IN
PWR
IN
BYPASS
CMOS Image Sensor IC
I 2 CTM data. Internal pull high resister is 10KΩ.
Voltage common mode
Analog ground.
Voltage reference bottom
Power Down (chip power down if high).
Connected with a 0.1uF capacitor
Internal voltage reference.
Voltage reference top
Note: The pin-out difference between PAC407BCA and PAS302BCA are pin1 and pin32.
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2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
2. Block Diagram
VGA
Image
Core
Timing
Generator
AFE
Serial
Interface
Sensor Interface
Data Flow
Pipelined
Image
Flow
Processor
AE
AWB
Register
Bank
Output Formatter
Control Flow
YUV data
Figure 2.1. PAC407 block diagram
The PAC407 is a 1/4” CMOS imaging sensor with 644x488 physical pixels. The active region of sensor
array is 644x484. The sensor array is cover with Bayer pattern color filters and micro-lens. The first pixel
location <0,0> is programmable in 2 direction (X and Y) and the default value is at the left-down side of
sensor array.
After a programmable exposure time, the signals of image are sampled first with CDS (Correlated Double
Sampling) block to improve S/N ratio and reduce fixed pattern noise (FPN).
Three analog gain stages are implemented before signals are transferred to 10-Bit ADC. The front gain
stage (FG) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The
programmable color gain stage (CG) is used to balance the luminance response difference between B, G
and R color. The global gain stage (GG) is programmed to adapt the gain to the image luminance.
After three gain stages, the signals will be digitized by the on-chip 10-Bit ADC. After the image data have
been digitized, further adjustment to the signal can be applied before the data is output to next stage.
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2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
3. Function Description
„
Defect Compensation
The Defect Compensation block can detect the possible defect pixel and replace it with average output of
like-colored pixels from near side of defect pixel. This function can be programmed to enable/disable by
user.
„
Hardware Windowing
Users are allowed to define window size and window location in PAC407. The location of window can be
anywhere in the sensor array. Window location and size are determined by different register settings.
„
Sub-Sampling
PAC407 can be programmed to output image in QVGA, QQVGA and CIF size. In QVGA sub-sampling
mode, both vertical and horizontal pixels are sub-sampling at 1/2, while in QQVGA sub-sampling mode,
both vertical and horizontal pixels are sub-sampling at 1/4.
„
Digital Zoom
By programming Hardware Windowing registers and Sub-sampling registers, PAC407supports 2X and
4X digital zoom.
„
Automatic White Balance
In digital image applications, color balance is typically achieved by automatic white balance (AWB).
PAC407 can adjust its color spectrum sensitivity to the scene such that the resulting image on the average
has an equal amount of all color components. The AWB mechanism can be set and adjusted by registers.
„
Color Saturation
If one color is more saturated than others, it will dominate the image. If the colors aren't saturated enough,
the image might appear lifeless. Hence, PAC407 can enable color saturation function by setting registers
to provide a more vivid image for user.
„
Lens Shading Compensation
In order to compensate the effect of the attenuation due to poorly optic component, PAC407 has a series
of registers to eliminate the shading effect.
„
Gamma Correction
To realize a more brilliant image quality, PAC407 includes gamma correction function. Gamma correction
performs on the luminance element of the image and allows compensating for non-linear dependence of
the display device output against driving signal (ex. monitor brightness against CRT voltage). Gamma
correction curve is shown as below, and some dedicated registers can adjust it.
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2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
Y9
Output Luminance
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
X
Y0
4 8 16 32
48
128
64
192
255
Input Luminance
Figure 4.1 Gamma Correction curve
„
Power Down Mode
Because PAC407 is divided by two portions: Sensor and ASIC (ISP), software power down procedure
should be performed on both portions. The PAC407 supports 2 power-down modes:
ƒ Software power down
Setting register “ISP_EnH”=0 in ASIC and register “Sw_PwrDn”=1 in Sensor.
ƒ Hardware power down
Pull PWDN pin to high to power down the chip. The chip will go into standby state.
„
Reset Mode
The PAC407 can be reseted by setting registers or by pulling low RESET# pin. PAC407 supports 2 reset
modes:
ƒ Software reset
Setting register “Sw_Reset”=1 in Sensor and register “Software_Reset”=1 in ASIC to reset all the
I 2 CTM registers.
ƒ Hardware reset
Pulling RESET# pin to low to reset the entire chip.
Version 1.7, 13 Sep
2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
4. Output Format
4.1. Sensor Output Format
644 - Column
G
G
G
B
R
....
G
R
G
R
G
....
B
G
B
G
484 - Row
B
R
644 X 484
pixels
G
R
G
R
....
G
R
G
R
B
G
B
G
....
B
G
B
G
Figure 4.1 RAW data output
640 - Column
....
RGB RGB RGB RGB
565 565 565 565
RGB RGB RGB RGB
565 565 565 565
....
RGB RGB RGB RGB
565 565 565 565
480 - Row
RGB RGB RGB RGB
565 565 565 565
640 X 480
pixels
RGB RGB RGB RGB
565 565 565 565
....
RGB RGB RGB RGB
565 565 565 565
RGB RGB RGB RGB
565 565 565 565
....
RGB RGB RGB RGB
565 565 565 565
Figure 4.2 RGB565 output
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
640 - Column
....
YCb YCr YCb YCr
YCb YCr YCb YCr
....
YCb YCr YCb YCr
480 - Row
YCb YCr YCb YCr
640 X 480
pixels
YCb YCr YCb YCr
....
YCb YCr YCb YCr
YCb YCr YCb YCr
....
YCb YCr YCb YCr
Figure 4.3 YCbCr422 Output
4.2. Output Timing
V/HSYNC
PX[7:0]
G R G R
B G B G
B G B G
G R G R
PXCK
Figure 4.4 Inter-Line Timing
VSYNC
HSYNC
PX[7:0]
Last Row
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Last Row
Row 0
Figure 4.5 Inter-Frame Timing
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
PXCK
HSYNC
Invalid
Data
PX[7:0]
B
G
B
G
Figure 4.6 RAW Data Output Timing
PXCK
HSYNC
Invalid
Data
PX[7:0]
Y1H
Y1L
First Byte
PX[7]
PX[6]
PX[5]
PX[4]
PX[3]
PX[2]
PX[1]
PX[0]
Y2H
Y2L
Second Byte
R4
R3
R2
R1
R0
G5
G4
G3
PX[7]
PX[6]
PX[5]
PX[4]
PX[3]
PX[2]
PX[1]
PX[0]
G2
G1
G0
B4
B3
B2
B1
B0
Figure 4.7 RGB565 Output Timing
PXCK
HSYNC
Invalid
Data
PX[7:0]
Y
Cb
Y
Cr
Figure 4.8 YCbCr422 Output Timing
Since the output stream of YCbCr422 or RGB565 format is two times then sensor raw data output, we
should double the pixel clock rate while data format is in YCbCr422 or RGB565 mode.
The minimum of Np=1 in sensor timing generator that means the pixel clock rate is the same as system
clock rate. Noticed that Np=1 can only be used in sensor raw data mode. When PAC407 is operated in
YCbCr422 or RGB565 mode, the minimum of Np should be 2. Besides, when Np is odd number, the duty
cycle of PXCK will not be 50%.
Note: The detail timing description for raw data output format could be found in PAS302 spec.
Version 1.7, 13 Sep
2004
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
5. I 2CTM Bus
PAC407 supports I 2 CTM bus transfer protocol and acts as slave device. The 7 bits unique slave address
is 1000000 and the bus supports receiving / transmitting speed up to 400kHz.
5.1. I 2CTM Bus Overview
There are only two lines SDA (serial data) and SCL (serial clock) carry information between the
devices which are connected by I 2 CTM bus. Normally both SDA and SCL lines are open collector
structure and pulled high by external pull-up resistors.
Only the master can initiate a transfer (start), generate clock signals, and terminate a transfer (stop).
Start Condition :
A high to low transition of the SDA line while SCL is high defines a start condition.
Stop Condition :
A low to high transition of the SDA line while SCL is high defines a stop condition.
Valid Data:
The data on the SDA line must be stable during the high period of the SCL clock. Within each byte,
MSB is always transferred first. Read/write control bit is the LSB of the first byte.
Both the master and slave can transmit and receive data from the bus.
Acknowledge :
The receiving device should pull down the SDA line during high period of the SCL clock line when a
byte was transferred completely by transmitter. When in the case of that a master received data from a
slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master
read cycle.
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 5-1: Start and Stop Conditions
SDA
DATA
STABLE
DATA
CHANGE
ALLOWED
SCL
Figure 5-2: Valid Data
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
5.2. Data Transfer Format
5.2.1. Master transmits data to slave (write cycle)
S: Start
A: Acknowledge by slave
P: Stop
RW: The LSB of 1ST byte to decide whether current cycle is read or write cycle.
If RW=1 that means read cycle, if RW=0 that means write cycle.
SUBADDRESS: The address values of PAC407 internal control
(Please refer to PAC407 register description)
„
„
„
„
„
1ST BYTE
S
2ND BYTE
SLAVE ID (7 BIT)
MSB
RW
A
SUBADDRESS (8 BIT)
registers
n BYTEs + A
A
DATA
A
DATA
A
P
LSB=0
1ST BYTE
S
SLAVE ID (7 BIT)
MSB
2ND BYTE
RW
A
n BYTEs + A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
LSB=0
During the write cycle, the master generates start condition and then places the 1st byte data that
combined slave address (7 bits) with a read/write control bit on SDA line. After slave(PAC407) issues
acknowledgment, the master places 2nd byte (sub-address) data on SDA line. And then following the
slave’s( PAC407) acknowledgment, the master places the 8 bits data on SDA line and transmit to PAC407
control register (address was assigned by 2nd byte). After PAC407 issue acknowledgment, the master can
generate a stop condition to end this write cycle. In the condition of multi-byte write, the PAC407
sub-address will be increased automatically after each DATA byte has been transferred. The Data and A
cycles are repeated until last byte write. Every control registers value inside PAC407 can be programming
via this way. (Please refer to Figure 5.3.)
5.2.2. Slave transmits data to master (read cycle)
The sub-address was assigned by previous write cycle
The sub-address is automatically increased after each byte read
Am : Acknowledged by master
Note there is no acknowledgment from master after last byte read
„
„
„
„
1ST BYTE
S
SLAVE ADDRESS
(7 BITS)
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2ND BYTE
RW
A
DATA (8 BIT)
PixArt Imaging Inc.
n BYTE
Am
DATA
Am
DATA
1
P
NO ACK IN LAST
BYTE
12
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
During read cycle, the master generates start condition and then place the 1st byte data that combine slave
address (7 bits) with a read/write control bit to SDA line. After slave issue acknowledgment, 8 bits DATA
was placed on SDA line by PAC407. The 8 bit data was read from PAC407 internal control register that
address was assigned by previous write cycle. Following the master acknowledgment, the PAC407 place
the next 8 bits data (address is increased automatically) on SDA line and then transfer to master serially.
The DATA and Am cycles are repeated until the last byte read. After last byte read, Am is no longer
generated by master but instead of keeping SDA line as high. The slave (PAC407) must releases SDA line
back to master to generate STOP condition. (Please refer to Figure 5.3.)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
P
S
Address
Start
Condition
R/W
ACK
from
Receiver
ACK
from
Receiver
Data
ACK
from
Receiver
Data
Stop
Condition
Figure 5.3 Data Transfer Format
5.3. I 2CTM Bus Timing
SDA
tf
tHD;STA
tf
tLOW
tr
tBUF
tr
tSP
tSU;DAT
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Figure 5.4 I 2 CTM Bus Timing
5.4. I 2CTM Bus Timing Specification
STANDARD-MODE
PARAMETER
SYMBOL
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
Low period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time. For I 2 CTM bus device
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
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2004
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UNIT
MIN.
MAX.
fscl
10
400
kHz
tHD:STA
4.0
-
µs
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
4.7
0.75
4.7
0
250
30
30
4.0
4.7
3.45
N.D. (note)
N.D. (note)
-
µs
µs
µs
µs
ns
ns
ns
µs
µs
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13
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
Capacitive load for each bus line
Noise margin at LOW level for each connected
device (including hysteresis)
Noise margin at HIGH level for each connected
device (including hysteresis)
Note: It depends on the "high" period time of SCL.
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2004
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Cb
1
15
pF
VnL
0.1 VDD
-
V
VnH
0.2 VDD
-
V
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PAC407BCA/PAC407BCW
CMOS Image Sensor IC
6. Electrical Characteristics
„
Absolute Maximum Ratings
-40℃ ~ +125℃
Ambient Storage Temperature
Supply Voltages ( with respect to Ground )
VCC
3V
VDDA
3V
VDDMA
4V
VDDMD
4V
-0.3V to VDDMD + 1V
All Input / Output Voltages (with respect to Ground)
Lead Temperature, Surface-mount process
+230℃
ESD Rating, Human Body model
2000V
„
DC Electrical Characteristics (Ta =0℃ ~ 70℃ )
Symbol
Parameter
Min.
Typ.
Max.
Unit
Type: PWR
VDDA
DC Supply voltage – Analog Power
2.4
2.5
2.6
V
VCC
DC Supply voltage – Digital Power
2.4
2.5
2.6
V
2.8
-
3.3
V
VDDMA/MD DC Supply voltage – Main Analog/Digital
IDD
IPWDN
Operating
Current
Power Down
Current
VDDMA/MD = 3.3V
15 fps
-
24.4
-
mA
VDDMA/MD = 3.3V
15 fps
-
35
-
µA
Type: IN & I/O Reset and SYSCLK
VIH
Input voltage HIGH
VIL
Input voltage LOW
CIN
Input capacitor
0.7 x
VDDMD
V
0.3 x
VDDMD
10
Type: OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ,2.5volts
0.9 x
VOH
Output voltage HIGH
VDDMD
0.1 x
VOL
Output voltage LOW
VDDMD
„
V
pF
V
V
AC Operating Condition
Symbol
Parameter
Min.
SYSCLK Master clock frequency
PXCK
Pixel clock output frequency (when YUV out)
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2004
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Typ.
Max.
Unit
26
MHz
26
MHz
15
PAC407BCA/PAC407BCW
„
CMOS Image Sensor IC
Sensor Characteristics
Parameter
Sensitivity
Signal to Noise Ratio
Range
Version 1.7, 13 Sep
BCW
1.4
1.2
Unit
dB
dB
Operation
60
-10 ~ 70
Stable Image
0 ~ 50
2004
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Note
V/Lux-Sec
> 45
Dynamic Range
Temperature
Typ.
BCA
℃
16
11
RESET#
13
14
PX9
PX8
12
10
VDDM
9
PX6
PX7
VSSD
RESET#
SY SCLK
PAS407BCW
SCL
SDA
VSSA
VDDA
21
22
1
2
3
0.1U
U1
PWDN
15
PX7
SY SCLK
PXCLK
8
16
PX6
PX5
17
PX5
PX4
18
PX4
PX3
VDDM
HSYNC
7
PXCLK
VSYNC
HSYNC
6
VSYNC
19
PX3
PX2
VREF
4
VREF
5
VCC
PX1
2004
PX0
E-mail: [email protected]
20
Version 1.7, 13 Sep
PX2
C2
SCL
SDA
PWDN
C1
PWDN
2
4
6
8
10
12
14
16
18
20
22
SENSOR BOARD INTERFACE
1
3
5
7
9
11
13
15
17
19
21
JP1
PXCLK
HSY NC
SCL
RESET#
PX7
PX5
PX3
VDDM
PX1
Notes:
VDDM is 2.8V to 3.3V sensor power.
C1 should close to sensor VDDA and AGND.
C2 should close to sensor VREF and AGND.
0.1U
VSY NC
SY SCLK
SDA
PX0
PX6
PX4
PX2
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
7. Reference Circuit Schematic
7.1. PAC407BCW
PixArt Imaging Inc.
17
18
PX3
20
19
17
16
15
PX4
PX6
14
NC2
NC1
PX3
PX4
VCC
PX6
VLRST
PXCLK
PAS407BCA
21
PX2
VHRST
VSSD
22
PX1
13
PX7
12
PX5
23
PX2
SYSCLK
24
PX0
11
VSSD
RESET#
SCL
SCL
PX0
PX1
PX9
10
PX7
9
SYSCLK
8
RESET#
7
PXCLK
26
SDA
25
SDA
PixArt Imaging Inc.
VDDMD
27
2004
VSSA
E-mail: [email protected]
VCM
6
VDDMD
VSSA
VSYNC
5
VSYNC
VRB
Version 1.7, 13 Sep
28
PWDN
VDDA
VREF
VRT
VDDMA
VPP
VPN
HSY NC
29
30
31
32
1
2
3
4
U4
PWDN
VREF
VDDMA
HSY NC
C1
0.1U
C2
0.1U
VSY NC
SY SCLK
SDA
VDDMA
PWDN
PX0
PX6
PX4
PX2
2
4
6
8
10
12
14
16
18
20
22
PXCLK
HSY NC
SCL
RESET#
PX7
PX5
PX3
VDDMD
PX1
Notes:
VDDMD is 2.8V to 3.3V sensor digital power.
VDDMA is 2.8V to 3.3V sensor analog power.
C1 should close to sensor VDDA and AGND.
C2 should close to sensor VREF and AGND.
SENSOR BOARD INTERFACE
1
3
5
7
9
11
13
15
17
19
21
JP1
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
7.2. PAC407BCA
18
PAC407BCA/PAC407BCW
8.
CMOS Image Sensor IC
Package Specification
8.1. PAC407BCW
Dimensions
Package Body Dimension X
Package Body Dimension Y
Package Height
Ball Height
Package Body Thickness
Thickness of Glass surface to wafer
Ball Diameter
Total Pin Count
Pin Count X axis
Pin Count Y axis
Pin Pitch X axis
Pin Pitch Y axis
Edge to Pin Center Distance along X
Edge to Pin Center Distance along Y
Edge to Optical Center Distance along X
Edge to Optical Center Distance along Y
Version 1.7, 13 Sep
2004
E-mail: [email protected]
Symbol
A
B
C
C1
C2
C3
D
N
N1
N1
J1
J2
S1
S2
E
F
Nominal
4340
4755
800
160
640
415
300
22
5
5
800
800
570
777.5
2254.16
1832.84
PixArt Imaging Inc.
Min.
4315
4730
740
130
605
395
270
540
747.5
2229.16
1807.84
Max.
4365
4780
860
190
675
435
330
600
807.5
2279.16
1857.84
Unit
µm
µm
µm
µm
µm
µm
µm
Ball
µm
µm
µm
µm
µm
µm
µm
µm
19
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
8.2. PAC407BCA
Unit:mm
Version 1.7, 13 Sep
2004
E-mail: [email protected]
PixArt Imaging Inc.
20
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
9. Recommended Lens and Holder
9.1. Genius Lens（2P1G）
Version 1.7, 13 Sep
2004
E-mail: [email protected]
PixArt Imaging Inc.
21
PAC407BCA/PAC407BCW
Version 1.7, 13 Sep
2004
E-mail: [email protected]
CMOS Image Sensor IC
PixArt Imaging Inc.
22
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
9.2. Asia-optical Lens（2P）
Version 1.7, 13 Sep
2004
E-mail: [email protected]
PixArt Imaging Inc.
23
PAC407BCA/PAC407BCW
CMOS Image Sensor IC
9.3. MaxEmil Lens（3P）
Version 1.7, 13 Sep
2004
E-mail: [email protected]
PixArt Imaging Inc.
24