240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb version A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply • Fully differential clock operations (CK & CK) • • All inputs and outputs are compatible with SSTL_1.8 interface Programmable Burst Length 4 / 8 with both sequential and interleave mode • Auto refresh and self refresh supported • 8 Bank architecture • 8192 refresh cycles / 64ms • Posted CAS • Serial presence detect with EEPROM • Programmable CAS Latency 3, 4, 5, 6 • DDR2 SDRAM Package: 60 ball(x4/x8) • OCD (Off-Chip Driver Impedance Adjustment) • 133.35 x 30.00 mm form factor • ODT (On-Die Termination) • RoHS compliant • ORDERING INFORMATION Part Name HMP31GP7AFR4C - Y5/S5/S6 Density Organization # of DRAMs # of ranks Parity Support 8GB 1G X 72 36 2 O This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2009 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800) Unit Speed@CL3 400 - 400 Mbps Speed@CL4 533 533 533 Mbps Speed@CL5 667 667 800 Mbps Speed@CL6 - 800 - Mbps CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 tCK ADDRESS TABLE Density Organization 8GB 1G x 72 Rev. 0.1 / Jan. 2009 Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 2 512Mb x 4 36 15(A0~A14)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms 2 1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description Symbol Type Polarity Pin Description CK0 IN Positive Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 IN Negative Edge Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CKE[1:0] IN Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. S[1:0] IN Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 ODT[1:0] IN Active High On-Die Termination signals. RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Vref Supply Reference voltage for SSTL18 inputs VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA[2:0] IN - Selects which DDR2 SDRAM internal bank of Eight is activated. During a Bank Activate command cycle, Address input defines the row address(RA0~RA13) A[9:0],A10/AP A[13:11] IN - DQ[63:0], CB[7:0] IN - DM[8:0] IN Active High VDD,VSS Supply During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke auto precharge operation at the end of the burst read or write cycle. If AP is high., auto precharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL IN - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. RESET IN The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Par_In IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even) Err_Out OUT VDDSPD TEST Rev. 0.1 / Jan. 2009 Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs) 3 1240pin Registered DDR2 SDRAM DIMMs PIN DESCRIPTION Pin Pin Description Pin Pin Description CK0 Clock Input, positive line ODT[1:0] CK0 Clock input, negative line VDDQ DQs Power Supply DQ0~DQ63 Data Input/Output CKE0~CKE1 Clock Enable Input On Die Termination Inputs RAS Row Address Strobe CB0~CB7 Data check bits Input/Output CAS Column Address Strobe DQS(0~8) Data strobes WE Write Enable DQS(0~8) Data strobes, negative line DM(0~8),DQS(9~17) Data Makes/Data strobes DQS(9~17) Data strobes, negative line S0,S1 A0~A9,A11~A13 A10/AP BA0, BA1, BA2 Chip Select Input Address input Address input/Autoprecharge RFU SDRAM Bank Address NC Reserved for Future Use No Connect SCL Serial Presence Detect(SPD) Clock Input TEST Memory bus test tool (Not Connected and Not Usable on DIMMs) SDA SPD Data Input/Output VDD Core Power SA0~SA2 E2PROM Address Inputs VDDQ Par_In Parity bit for the Address and Control bus Err_Out Parity error found on the Addre RESET Reset Enable CB0~CB7 VSS VREF VDDSPD I/O Power Supply Ground Reference Power Supply Power Supply for SPD Data Strobe Inputs/Outputs PIN LOCATION pin #1 Pin #121 Rev. 0.1 / Jan. 2009 Front Side Back Side Pin #64 Pin #184 Pin #65 Pin #185 Pin #120 pin #240 4 1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS 2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13 3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 DQS13 4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS 5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38 6 DQS0 46 DQS8 86 DQ34 126 DQS9 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS 8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44 9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14 DQS14 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS 14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46 DQ47 15 DQS1 55 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52 18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU 22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15 24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15 25 DQ17 105 DQS6 145 VSS 225 VSS Key Key 26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54 27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0 227 DQ55 28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS 29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60 30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61 31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 231 VSS 32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16 33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 233 NC,DQS16 34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS 35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62 DQ63 36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS 38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD 39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0 40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1 80 DQ32 200 DQ37 NC= No Connect, RFU= Reserved for Future Use. Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs) Rev. 0.1 / Jan. 2009 5 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 8GB(1Gbx72): HMP31GP7AFR4C VSS RS0 RS1 DQS0 DQS0 DQS9 DQS9 DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D0 D18 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D1 D19 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D2 D20 DQS3 DQS3 DQ12 DQ13 DQ14 DQ15 DQS11 DQS11 DQ20 DQ21 DQ22 DQ23 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D9 D27 Serial PD SCL SDA WP A0 A1 A2 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D10 SA0 SA1 SA2 D28 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D11 D29 VDDSPD SPD VDD/VDDQ D0–D35 VREF D0–D35 VSS D0–D35 DQS12 DQS12 DQ24 DQ25 DQ26 DQ27 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D3 D21 DQS8 DQS8 DQ28 DQ29 DQ30 DQ30 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D12 D30 DQS17 DQS17 CB0 CB1 CB2 CB3 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D8 D26 CB4 CB5 CB6 CB7 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D17 D35 Signals for Address and Command Parity Function Register Par_In RS0 RS1 DQS4 DQS4 PARIN PTYERR 0Ω Register 100KΩ DQS13 DQS13 DQ32 DQ33 DQ34 DQ35 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D4 D22 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D5 D23 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D6 D24 DQS7 DQS7 DQ36 DQ37 DQ38 DQ39 DQS14 DQS14 DQ44 DQ45 DQ46 DQ47 DQS15 DQS15 DQ52 DQ53 DQ54 DQ55 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D13 D31 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D14 D32 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D15 PARIN PTYERR Err_Out o ohm resistor on Err_Out is not populated for non-parity card. The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Out refer to the section: “Register Options for Unused Address input” D33 DQS16 DQS16 DQ56 DQ57 DQ58 DQ59 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 S0* D7 D25 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D16 D34 RS0 -> CS: SDRAMs D0-D17 S1* BA0-BA2*** A0-A15*** RAS 1:2 R E G I S T CAS WE CKE0 CKE1 ODT0 ODT1 RESET** DQ4 DQ5 DQ6 DQ7 DQS10 DQS10 E R RST PCK7** PCK7** RS1 -> CS: SDRAMs D18-D35 RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35 RA0-RA15 -> A0-A15: SDRAMs D0-D35 RRAS -> RAS: SDRAMs D0-D35 CK0 CK0 RESET P L L OE PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35 PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35 PCK7 -> CK: Register PCK7 -> CK: Register RCAS -> CAS: SDRAMs D0-D35 RWE -> WE: SDRAMs D0-D35 RCKE0 -> CKE0-1: SDRAMs D0-D17 RCKE1 -> CKE0-1: SDRAMs D18-D35 RODT0 -> ODT1: SDRAMs D0-D17 RODT1 -> ODT1: SDRAMs D18-D35 Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 22 Ohms ± 5%. 3. RS0 and RS1 alternate between the bottom and surface sides of the DIMM. *S0 connects to DCS and S1 command to CRS on a pair of Register, S2 connects to DCS and S0 connect to CRS on another pair of Register. ** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to one pair of four Registers. *** A14-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here. Rev. 0.1 / Jan. 2009 6 1240pin Registered DDR2 SDRAM DIMMs ABSOLUTE MAXIMUM DC RATINGS Parameter Symbol Value Unit Note Voltage on VDD pin relative to Vss VDD - 1.0 ~ 2.3 V 1 Voltage on VDDQ pin relative to Vss VDDQ - 0.5 ~ 2.3 V 1 Voltage on VDDL pin relative to Vss VDDL - 0.5 ~ 2.3 V 1 Voltage on any pin relative to Vss VIN, VOUT - 0.5 ~ 2.3 V 1 Operating Conditions and Environmental Parameters Parameter Symbol Rating Units Notes DIMM Operating temperature(ambient) TOPR 0 ~ +55 o C Storage Temperature TSTG -50 ~ +100 o C 1 Storage Humidity(without condensation) HSTG 5 to 95 % 1 DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal 2 DRAM Component Case Temperature Range TCASE 0 ~+95 oC 3 Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con ditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. DC OPERATING CONDITIONS Symbol Parameter (SSTL_1.8) Rating Min. Typ. Max. Units Notes VDD Supply Voltage 1.7 1.8 1.9 V 1 VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1,2 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,2 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4 VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 5 1.7 - 3.6 V VDDSPD EEPROM Supply Voltage Note: 1. Min. Type. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. Rev. 0.1 / Jan. 2009 7 1240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V Note INPUT AC LOGIC LEVEL Parameter DDR2 667/800 Symbol Min Unit Max ac Input logic HIGH VIH(AC) VREF + 0.200 - V ac Input logic LOW VIL(AC) - VREF - 0.200 V Notes AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.5 * VDDQ V 1 VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 Note: 1. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the range from VREF min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Start of Falling Edge Input Timing Start of Rising Edge Input Timing VSWING(MAX) ∆TR ∆TF Falling Slew = VREF - VIL(ac) max ∆TF Rising Slew = VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS VIH(ac) min - VREF ∆TR < Figure: AC Input Test Signal Waveform > Rev. 0.1 / Jan. 2009 8 1240pin Registered DDR2 SDRAM DIMMs Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Note 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 Note: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Note: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. DIFFERENTIAL AC OUTPUT PARAMETERS Symbol VOX (ac) Parameter ac differential crosspoint voltage Min. Max. Units Note 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 0.1 / Jan. 2009 9 1240pin Registered DDR2 SDRAM DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Units Notes 0.5 * VDDQ V 1 Note: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current SSTl_18 Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 Note: 1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 0.1 / Jan. 2009 10 1240pin Registered DDR2 SDRAM DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C) 8GB: HMP31GP7AFR4C Pin CK0, /CK0 CKE, ODT /CS Address, /RAS, /CAS, /WE DQ, DM, DQS, /DQS Rev. 0.1 / Jan. 2009 Symbol Min Max Unit CCK CI1 CI2 CI3 CIO TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD pF pF pF pF pF 11 1240pin Registered DDR2 SDRAM DIMMs IDD SPECIFICATIONS (TCASE: 0 to 95oC) 8GB, 1G x 72 Registered DIMM: HMP31GP7AFR4C Symbol Y5 (DDR2 667@CL5) S6 (DDR2 800@CL6) Unit IDD0 3170 3350 mA IDD1 3350 3530 mA IDD2P 1082 1082 mA IDD2Q 2270 2450 mA IDD2N 2450 2630 mA IDD3P(F) 1910 1910 mA IDD3P(S) 1298 1298 mA IDD3N 3170 3530 mA IDD4W 5150 5960 mA IDD4R 4880 5600 mA IDD5B 5310 5580 mA IDD6 990 990 mA IDD7 6590 7130 mA Note 1 Note: 1. IDD6 current values are guaranteed up to Tcase of 85°Cmax. Rev. 0.1 / Jan. 2009 12 1240pin Registered DDR2 SDRAM DIMMs IDD Measurement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranteed up to Tcase of 85℃ max. mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin ≤ VILAC (max) HIGH is defined as Vin ≥ VIHAC (min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes Rev. 0.1 / Jan. 2009 13 1240pin Registered DDR2 SDRAM DIMMs Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-800 (S5) DDR2-667 (Y5) Bin(CL-tRCD-tRP) 5-5-5 5-5-5 Parameter min min CAS Latency 5 5 ns tRCD 12.5 15 ns tRP 12.5 15 ns tRC 57.5 60 ns tRAS 45 45 ns Rev. 0.1 / Jan. 2009 Unit 14 1240pin Registered DDR2 SDRAM DIMMs AC Timing Parameters by Speed Grade (DDR2-667 & DDR2-800) Parameter Symbol DDR2-667 DDR2-800 min max min max Unit Note DQ output access time from CK/CK tAC -450 +450 -400 +400 DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) - min(tCL, tCH) - ps Clock cycle time, CL=x tCK 3000 8000 2500 DQ and DM input setup time (differential strobe) tDS 100 - 50 - ps 1 DQ and DM input hold time (differential strobe) tDH 175 - 125 - ps 1 Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK ps ps tIPW 0.6 - 0.6 - tCK tDIPW 0.35 - 0.35 - tCK - tHZ - tAC max tAC max ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 - 200 ps DQ hold skew factor tQHS - 340 - 300 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write preamble tWPRE 0.35 - 0.35 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 - 127.5 - ns Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns tIS 200 - 175 - ps Address and control input setup time Address and control input hold time tIH 275 - 250 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Activate to precharge command tRAS 45 70000 45 70000 ns Active to active command period for 1KB page size products tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Active Window for 1KB page size products tFAW 37.5 - 35 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 7.5 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 Rev. 0.1 / Jan. 2009 2 7.5 tCK ns 15 1240pin Registered DDR2 SDRAM DIMMs Parameter Symbol DDR2-667 min DDR2-800 max min max Exit self refresh to a non-read command tXSNR tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK tXARD 2 2 tCK tXARDS 7 - AL 8 - AL tCK tCKE 3 3 tCK Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay tRFC + 10 Unit ns tAOND 2 2 2 2 tCK tAON tAC(min) tAC(max) +0.7 tAC(min) tAC(max) +0.7 ns tAONPD tAC(min)+2 2tCK+ tAC(max)+1 tAC(min) +2 2tCK+ tAC(max)+1 ns tAOFD 2.5 2.5 2.5 2.5 tCK ns tAOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max) +0.6 ODT turn-off (Power-Down mode) tAOFPD tAC(min) +2 2.5tCK+ tAC(max)+1 tAC(min) +2 2.5tCK+ tAC(max)+1 ODT to power down entry latency tANPD 3 ODT power down exit latency tAXPD 8 OCD drive mode output delay tOIT 0 ODT turn-off Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval tDelay 3 0 tCK 12 tIS+tCK +tIH tIS+tCK+tIH ns tCK 8 12 Note ns ns tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 Note: 1. For details and notes, please refer to the relevant HYNIX component datasheet H5PS2G[4,8]3AFR. 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 0.1 / Jan. 2009 16 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 1Gx72 (2 ranks) - HMP31GP7AFR4C Front 2X 3.00MIN PLL Register 4X FULL R 4X 4.0 ± 0.1 17.80 30.00 10.00 2X Ø 2.50 ± 0.10 2X 2.3 ± 0.1 5.175 2X R1.00 63.0 DETAIL-A DETAIL-B 5.0 55.0 128.95 133.35 Register Back Detail of Contacts A Detail of Contacts B Side 0.8 ± 0.05 3.80 1.0 2.50 3.0 ± 0.15 0.35 0.05 2.50 ± 0.20 4.00max 1.50 ± 0.10 0.3 ~ 1.0 5.00 1.27 ± 0.10 Note) All dimensions are typical unless otherwise stated. Rev. 0.1 / Jan. 2009 Millimeters Inches 17 1240pin Registered DDR2 SDRAM DIMMs REVISION HISTORY Revision History Date 0.1 Initial data sheet released Jan. 2009 Rev. 0.1 / Jan. 2009 18