HPL5331 3A Bus Termination Regulator Features General Description (Cont.) • On-chip thermal shutdown provides protection against any combination of overload that would create excessive junction temperature. The output voltage of HPL5331 track the voltage at VREF pin. A resistor divider connected to VIN, GND and VREF pins is used to provide a half voltage of VIN to VREF pin. In addition, an external ceramic capacitor and an opendrain transistor connected to VREF pin provides softstart and shutdown control respectively. Pulling and holding the VREF to GND shuts off the output. The output of HPL5331 will be high impedance after being shut down by VREF or thermal shutdown function. Provide Bi-direction Current - Sourcing or Sinking Current up to 3A High Output Accuracy - ±20mV over Load, VOUT Offset and Temperature • Adjustable Output Voltage by External Resistors • Current-Limit Protection • On-Chip Thermal Shutdown • Shutdown for Standby or Suspend Mode • Simple SOP-8, SOP-8-P with thermal pad, Pin Configuration TO-252- 5 and TO-263-5 Packages Applications VIN 1 8 VCNTL GND 2 7 VCNTL VREF • DDR I/II SDRAM Termination • SSTL-2/3 Termination Voltage • Applications Requiring the Regulator with VOUT 3 6 VCNTL 4 5 VCNTL TAB is VCNTL SOP-8 (Top View) 5 • VOUT 4 Fast Transient Response VREF 3 • VCNTL 2 1.25V/0.9V Output for DDR I/II Applications GND 1 • VIN TO-252-5 (Top View) Bi-direction 3A Current Capability General Description The HPL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for VIN 1 8 NC GND 2 7 NC VREF 3 6 VCNTL VOUT 4 5 NC TAB is VCNTL SOP-8-P (Top View) DDR-SDRAM termination. The HPL5331 integrates two power transistors to source or sink current up to 5 4 3 2 1 VOUT VREF VCNTL GND VIN TO-263-5 (Top View) NC = No internal connection = Thermal Pad (connected to GND plane for better heat dissipation) 3A. It also incorporate current-limit, thermal shutdown and shutdown control functions into a single chip. Current-limit circuit limits the short-circuit current. Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 1 www.hipacsemi.com HPL5331 Ordering and Marking Information Package Code K : SOP-8 KA : SOP-8-P U5 : TO-252-5 G5 : TO-263-5 Temp. Range C : 0 to 70 o C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device HPL5331 Lead Free Code Handling Code Temp. Range Package Code HPL5331KC-TR : HPL5331KAC-TR : HPL5331 XXXXX XXXXX - Date Code HPL5331U5C-TR : HPL5331G5C-TR : HPL5331 XXXXX XXXXX - Date Code Pin Description PIN NAME I/O VIN I GND O VCNTL I VREF I VOUT O DESCRIPTION Main power input pin. Connect this pin to a voltage source and an input capacitor. The HPL5331 sources current to VOUT pin by controlling the upper NPN pass transistor, providing a current path from VIN pin. Power and signal ground. Connect this pin to system ground plane with shortest traces. The HPL5331 sinks current from VOUT pin by controlling the lower NPN pass transistor, providing a current path to GND pin. This pin is also the ground path for internal control circuitry. C NTL Power input pin for internal control circuitry. VConnect this pin to a voltage source, providing a bias for the internal control circuitry. A bypass capacitor is usually connected near this pin. Reference voltage input and active-low shutdown control pin. Apply a voltage to this pin as a reference voltage for the HPL5331. Connect this pin to a resistor divider, between VIN and GND, and a capacitor for soft-start and filtering noise C u rre n t to shut purposes. Applying and holding this pin low by an open-drain transistor Lim it down the output. Output pin of the regulator. Connect this pin to load. Output capacitors connected this pin improves stability and transient response. The output voltage tracks the reference voltage and is capable of sourcing or sinking current up to 3A. Block Diagram V RE F V C NTL V o lt ag e R e g ulat io n V IN Th erm a l L im it C u rre nt L im it V OUT S h u td ow n G ND Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 2 www.hipacsemi.com HPL5331 Absolute Maximum Ratings Symbol V CNTL Parameter VCNTL Supply Voltage, VCNTL to GND V IN VIN Supply Voltage, VIN to GND PD Power Dissipation TJ T STG Rating Unit -0.2 ~ 7 V -0.2 ~ 3.9 V Internally Limited Junction Temperature Storage Temperature T SDR Soldering Temperature, 10 Seconds V ESD Minimum ESD Rating (Human Body Mode) W 150 o C -65 ~ 150 o C 300 o C ±3 kV Thermal Characteristics Symbol Rating Unit 160 80 80 50 °C/W Range Unit VCNTL Supply Voltage 3.1 ~ 6V V V IN VIN Supply Voltage 1.6 ~ 3.5 V V REF VREF Input Voltage 0.8 ~ 1.75 V IOUT VOUT Output Current (Note1, 2) θJA Parameter Thermal Resistance in Free Air SOP-8 SOP-8-P TO-252-5 TO-263-5 Recommended Operating Conditions Symbol V CNTL TJ Parameter -3 ~ +3 Junction Temperature 0 ~ 125 A o C Note1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to GND. Note2 : The max. IOUT varies with the TJ. Please refer to the typical characteristics. Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 3 www.hipacsemi.com HPL5331 Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN and TJ= 0 to 125°C, unless otherwise specified. Typical values refer to TJ =25°C. Symbol Parameter HPL5331 Test Conditions Min Typ Max Unit Output Voltage V OUT VOUT Output Voltage System Accuracy V OS VOUT Offset Voltage (V OUT –V REF) Load Regulation I OUT=0A Over temperature, VOUT offset, and load regulation I OUT=+10mA -20 -14 I OUT=-10mA 20 -9 2 I OUT=+10mA to +3A V V REF -6 I OUT = -10mA to -3A 8 -3 7 12 mV mV mV Protection I LIM T SD Current Limit Sourcing Current (V IN =2.5V) Sinking Current (V IN =2.5V) Sourcing Current (V IN =1.8V) Sinking Current (V IN =1.8V) T J =25°C T J =125°C T J =25°C T J =125°C T J =25°C T J =125°C T J =25°C T J =125°C +3.3 -3.3 +2.9 -2.9 Thermal Shutdown Rising T J Temperature Thermal Shutdown Hysteresis +3.6 +3.1 -3.6 -3.1 +3.2 +2.6 -3.2 -2.6 A 150 o C 40 o C Input Current ICNTL IVREF VCNTL Supply Current I OUT =0A I OUT =±3A (Normal Operation), V CNTL =5V V REF=GND (Shutdown) 2 4.5 6 50 110 mA 150 500 nA 20 40 µA 2.6 V REF=1.25V/0.9V (Normal Operation) VREF Bias Current (The current flows out of VREF) V REF=GND (Shutdown) Shutdown Control Shutdown Threshold Voltage Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 0.2 4 0.35 0.65 V www.hipacsemi.com HPL5331 Typical Application Circuit 1. VOUT=1.25V/0.9V Application VC N TL +3 .3 V VIN +2 .5 V/1 .8 V VIN R1 1k VC N TL VR EF C IN 4 70 uF GN D VO U T VR EF Shu td o w n Q1 R2 1k C C N TL 4 7u F C SS 0 .1u F VOU T +1 .2 5 V/0.9 V -3 ~+3 A C OU T 4 70 uF GN D GN D COUT : 470µF, ESR=25mΩ R1, R2 : 1kΩ, 1% Q1 : HPM2300 AC Note : Since R1 and R2 are very small, the voltage offset caused by the bias current of VREF can be ignore. 2. VOUT=1.4V Application VCNT L +5V VIN +2.8V VIN R1 1k C IN 470 µ F VR EF VOUT +1.4V/ -3~+3 A GN D VOU T VRE F R2 1k CSS 0.1 µ F C CNT L 47 µ F C O UT 470 µ F GND GND Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 VC N TL 5 www.hipacsemi.com HPL5331 Typical Characteristics Sourcing Current-Limit vs Junction Temperature Sinking Current-Limit vs Junction Temperature 5.0 -2.0 VCNTL=5V,VIN=2.5V VCNTL=3.3V,VIN=2.5V Current-Limit, ILIM (A) Current-Limit, ILIM (A) 4.5 4.0 3.5 3.0 VCNTL=5V,VIN=1.8V VCNTL=3.3V,VIN=1.8V 2.5 2.0 VCNTL=3.3V,VIN=1.8V -3.0 -3.5 VCNTL=3.3V,VIN=2.5V -4.0 VCNTL=5V,VIN=2.5V -4.5 -5.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 Junction Temperature (°C) Junction Temperature (°C) VREF Bias Current vs Junction Temperature VREF Shutdown Threshold vs Junction Temperature 125 0.6 0.40 VREF=1.25V/0.9V VREF Shutdown Threshold (V) VREF Bias Current, IVREF (µA) VCNTL=5V,VIN=1.8V -2.5 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -50 0.5 VCNTL=5V 0.4 0.3 VCNTL=3.3V 0.2 0.1 -25 0 25 50 75 100 125 -50 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 -25 6 www.hipacsemi.com HPL5331 Typical Characteristics (Cont.) VOUT Offset Voltage vs Junction Temperature Quiescent VCNTL Current vs Junction Temperature 7.0 Quiescent VCNTL Current (mA) VOUT Offset Voltage, VOS (mV) 6 VREF=1.25V/0.9V 4 2 0 IOUT=-10mA -2 -4 -6 -8 -10 -12 IOUT=+10mA -14 -16 IOUT=0A 6.5 6.0 VCNTL=5V 5.5 5.0 4.5 4.0 VCNTL=3.3V 3.5 3.0 2.5 2.0 -50 -25 0 25 50 75 100 125 -50 Junction Temperature (°C) -25 0 25 50 75 100 125 Junction Temperature (°C) VREF Bias Current vs VREF Supply Voltage VREF Bias Current, IVREF (µA) 22 20 TJ=25°C 18 16 14 12 10 8 6 4 2 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VREF Supply Votage, VREF (V) Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 7 www.hipacsemi.com HPL5331 Operating Waveforms 1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +10mA -> +3A IOUT = +10mA -> +3A -> +10mA IOUT = +3A -> +10mA Load Regulation = -2.8mV VOUT VOUT IOUT +3A IOUT IOUT +10mA Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div VOUT Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div 2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = -10mA -> -3A IOUT = -10mA -> -3A -> -10mA IOUT = -3A -> -10mA Load Regulation = +6.2mV VOUT VOUT VOUT IOUT IOUT -10mA IOUT -3A Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 8 Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div www.hipacsemi.com HPL5331 Operating Waveforms (Cont.) 3. Load Transient Response : IOUT = +3A -> -3A -> +3A - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +3A -> -3A IOUT = -3A -> +3A IOUT = +3A -> -3A -> +3A VOUT VOUT VOUT IOUT IOUT +3A IOUT Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div -3A Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 20µS/Div Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div 4. Short-Circuit Test - VIN = 2.5V, VCNTL = 3.3V VOUT is Shorted to GND VOUT is Shorted to VIN (2.5V) IOUT VOUT IOUT VOUT IOUT VOUT Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div 9 www.hipacsemi.com HPL5331 Application Information Shutdown and Soft-Start The VREF pin is a dual-function input pin, acting as reference input and shutdown control input. Applying and holding a voltage below 0.35V(typ.) to VREF pin shuts down the output of the regulator. An NPN transistor or N-channel MOSFET is used to pull down the VREF while applying a “high” signal to turn on the transistor. When shutdown function is active, the two pass transistors are turned off and the impedance of the VOUT is about 10MΩ (typ.), sourcing or sinking no current. When release the VREF pin, the current through the resistor divider charges the softstart capacitor to initiate a soft-start cycle. The output voltage tracks the rising VREF. The soft start process limits the input surge current. General The HPL5331 is a linear regulator and is capable of sourcing or sinking current up to 3A. The HPL5331 has fast transient response, accurate output voltage (small voltage offset, load regulation), active-low shutdown control and fault protections (current-limit, thermal shutdown). The HPL5331 is available in several packages to meet different of power dissipation in requirement various applications. Output Voltage Regulation The output voltage at VOUT pin tracks the reference voltage applied at VREF pin. Two internal NPN pass transistors controlled by separate high bandwidth error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. The base currents of the pass transistors are provided by VCNTL pin. An internal kelvin sensing scheme use at the VOUT pin for perfect load regulation at various load current. To prevent the two pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error amplifiers. This results in higher output voltage while the regulator sinks light or heavy load current. Since the HPL5331 exhibits very fast load transient response, lesser amount of capacitors can be use. In addition, capacitors with high ESR can also be use. Thermal Shutdown An thermal shutdown circuit limits the junction temperature of the HPL5331. When the junction temperature exceeds TJ= +150oC, a thermal sensor turns off both pass transistors, allowing the device to cool down. The regulator starts to regulate again after the junction temperature reduces by 40oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal limit designed with a 40oC hysteresis lowers the average TJ during continuous thermal overload conditions, extend life time of HPL5331. Current Limit The HPL5331 monitors sourcing and sinking current, and limits the maximum output current to prevent damages during overload or short-circuit, To increase the input voltage of VIN or VCNTL will get higher current-limit points. Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 10 www.hipacsemi.com HPL5331 Application Information Power Inputs Input power sequence are not required for VIN and VCNTL. However, do not apply a voltage to VOUT when there is not voltage VCNTL. This is due to the internal parasitic diodes between VOUT to VIN and VOUT to VCNTL which will be forward bias. The HPL5331 can source few current or sinks current up to 3A for load when the input Voltage at VIN is not present. put capacitor should have an ESR less than 1Ω. 25 ESR (mΩ) 20 Stable Region 15 10 5 0 10 Reference Voltage A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. Normally the bias current of the VREF pin flows out of the IC and is about 150nA(typ.), creating voltage offset at the resistor divider and affecting the output voltage accuracy. The recommended resistor is <5kΩ to maintain the accuracy of the output voltage. An external bypass capacitor is also connected to VREF. The capacitor and the resistor divider form a lowpass filter to reduce the inherent reference noise from VIN. A ceramic capacitor can be use and is selected to be greater than 0.1µF. Connected the capacitor as close to VREF as possible for optimal effect. More capacitance and large resistor divider will increase the soft-start interval. Do not place any additional loading on this reference input pin. 1000 Ultra-low-ESR capacitors, such as ceramic chip capacitors, may promote under-damped transient response, but proper ceramic chip capacitors placed near loads can be used as decoupling capacitors. A low-ESR solid tantalum and aluminum electrolytic capacitor (ESR<1Ω) works extremely well and provides good transient response and stability over temperature. The output capacitors are also used to reduce the slew rate of load current and help the HPL5331 to minimize variations of the output voltage, improving transient response. For this purpose, the low-ESR capacitors are recommended and depend on the stepping and slew rate of load current. Input Capacitor The input capacitors of VCNTL and VIN pins are not required for stability but for supplying surge currents during large load transients, This will prevent the input rail from drooping and improve the performance of the HPL5331. Because of parasitic inductors from voltage sources or other bulk capacitors to the VCNTL and VIN pins will limit the slew rate of the surge currents during large load transients, resulting in voltage drop at VIN and VCNTL pins. Output Capacitor The HPL5331 requires a proper output capacitor to maintain stability over full temperature and current ranges, and improve transient response. The output capacitor selection is dependent upon the ESR (equivalent series resistance) and capacitance of the output capacitor over full temperature range. The following chart shows the stable region of the output capacitor for HPL5331. The stable region is above the curve, indicating minimum required ESR and capacitance to maintain stability. However, the out Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 100 Capacitance(µF) 11 www.hipacsemi.com HPL5331 plane reduces the resistance θCA . The relationship between power dissipation and temperatures is the following equation : PD = (TJ - TA) / ≤ θJA where, PD : Power dissipation TJ : Junction Temperature TA : Ambient Temperature θJA : Junction-to-Ambient Thermal Resistance A capacitor of 1µF (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended to connect near VCNTL pin. For VIN pin, an aluminum electrolytic capacitor (>50µF) is recommended. It is not necessary to use low-ESR capacitors. Layout and Thermal Consideration The input capacitors for VIN and VCNTL pins are normally placed near each pin for good performances. Ceramic decoupling capacitors at output must be placed as close to the load to reduce the parasitic inductors of traces. It is also recommended that the HPL5331 and output capacitors are placed near the load for good load regulation and load transient response. The negative pins of the input and output capacitors and the GND pin of the HPL5331 should connect to analog ground plane of the load. See figure 1. The SOP-8-P utilizes a bottom thermal pad to minimize the thermal resistance of the package, making the package suitable for high current applications. The thermal pad is soldered to the top ground pad and is connected to the internal or bottom ground plane by several vias. The printed circuit board (PCB) forms a heat sink and dissipates most of the heat into ambient air. The vias are recommended to have proper size to retain solder, helping heat conduction. Thermal resistance consists of two main elements, θJC (junction-to-case thermal resistance) and θCA (caseto-ambient thermal resistance). θJC is specified from the IC junction to the bottom of the thermal pad directly below the die. θCA is the resistance from the bottom of thermal pad to the ambient air and it includes θCS (case-to-sink thermal resistance) and θSA (sink-to-ambient thermal resistance). The specified path for heat flow is the lowest resistance path and it dissipates majority of the heat to the ambient air. Typically, θCA is the dominant thermal resistance. Therefore, enlarging the internal or bottom ground Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 102 mil 118 mil SOP-8-P D ie T herm al pad T op g ro u n d pad A m b ie n t Air V ias Internal P rinted g ro un d circuit p la n e b o a rd Figure 1 Package Top and side view Figure 2 shows a board layout using the SOP-8-P package. The demo board is made of FR-4 material and is a two-layer PCB. The size and thickness are 65mm* 65mm and 1.6mm. An area of 140mil*105mil on the top layer is use as a thermal pad for the HPL5331 and this is connected to the bottom layer by vias. The bottom layer using 2 oz. copper acts as the ground plane for the system. The PCB and all components on the board form a heat sink. The θJA of the HPL5331 (SOP-8-P) mounted on this demo board is about 37oC/ W in free air. Assuming the TA=25oC and the maximum TJ=150oC (typical thermal limit temperature), the maximum power dissipation is calculated as : 12 www.hipacsemi.com HPL5331 PD (max) = (150 - 25) / 37 = 3.38W If the TJ is designed to be below 125oC, the calculated power dissipation should be less than : PD = (125 - 25) / 37 = 2.70W HPL5331 HPL5331 Figure 2(c) Bottom layer Figure 2(a) TopOver layer HPL5331 Figure 2(b) Top layer Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 13 www.hipacsemi.com HPL5331 Packaging Information E e1 0.015X45 SOP-8 pin ( Reference JEDEC Registration MS-012) H e2 D A1 1 L 0.004max. Dim A Mi ll im et er s In ch e s Min . 1. 3 5 Ma x . 1. 7 5 Min . 0. 0 53 Ma x. 0. 0 69 A1 0. 1 0 0. 2 5 0. 0 04 0. 0 10 D 4. 8 0 5. 0 0 0. 1 89 0. 1 97 E 3. 8 0 4. 0 0 0. 1 50 0. 1 57 H 5. 8 0 6. 2 0 0. 2 28 0. 2 44 A L 0. 4 0 1. 2 7 0. 0 16 0. 0 50 e1 0. 3 3 0. 5 1 0. 0 13 0. 0 20 e2 1. 2 7B S C 0. 50B S C φ 1 8° 8° Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 14 www.hipacsemi.com HPL5331 Packaging Information E1 E 0.015X45 SOP-8-P pin ( Reference JEDEC Registration MS-012) H D1 e1 e2 D A1 A 1 L 0.004max. Dim A M illim et er s Inc h es M in . M ax. M in. M ax. 1.3 5 1. 75 0. 0 53 0.0 69 A1 0.1 0 0. 25 0. 0 04 0.0 10 D 4.8 0 5. 00 0. 1 89 0.1 97 3. 0 0R EF D1 E 3.8 0 E1 0. 118 RE F 4. 00 0. 1 50 2. 6 0R EF 0.1 57 0. 1 02 R EF H 5.8 0 6. 20 0. 2 28 0.2 44 L 0.4 0 1. 27 0. 0 16 0.0 50 e1 0.3 3 0. 51 0. 0 13 0.0 20 e2 1.2 7BS C 0. 50B SC φ 1 8° 8° Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 15 www.hipacsemi.com HPL5331 Packaging Information TO-252-5 E1 A H B L D M C D1 J D im A B C D D1 E1 P S H J K L M P K S M illim e te rs M in . 6 .4 0 5 .2 0 6 .8 0 2 .2 0 In c h e s M ax. 6 .8 0 5 .5 0 7 .2 0 2 .8 0 M in . 0 .2 5 0 .2 0 0 .2 6 0 .0 8 5 .2 R E F 5 .3 R E F 1 .2 7 R E F 0 .5 0 2 .2 0 0 .4 5 0 .4 5 0 .9 0 5 .4 0 Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 M ax. 0 .2 6 0 .2 1 0 .2 7 0 .11 0 .2 0 5 R E F 0 .2 0 9 R E F 0 .0 5 R E F 0 .8 0 2 .4 0 0 .5 5 0 .6 0 1 .5 0 5 .8 0 16 0 .0 2 0 .0 8 0 .0 1 0 .0 1 8 0 .0 3 0 .2 1 0 .0 3 0 .0 9 0 .0 2 0 .0 2 4 0 .0 6 0 .2 2 www.hipacsemi.com HPL5331 Packaging Information TO-263-5 A D L E v B c1 A1 L1 L2 b c e e1 M i llim et e r s Dim M ax . M in. M a x. 4.06 4. 8 3 0. 1 60 0. 1 90 0.50 0. 9 9 0. 0 20 0. 0 39 1.52 1. 8 3 0. 0 60 0. 0 72 c 0. 4 57 0. 7 3 6 0. 0 18 0. 0 29 c1 1.14 1. 4 0 0. 0 45 0. 0 55 D 8.25 9. 6 6 0. 3 25 0. 3 80 E 9.65 10 . 2 9 0. 3 80 0. 4 05 L 14 . 60 15 . 8 8 0. 5 75 0. 6 25 2. 8 0 0. 0 90 0. 11 0 A b b1 L1 M in . Inc he s 2.28 L2 Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 1. 4 0 17 0. 0 55 www.hipacsemi.com HPL5331 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Tem perature Ram p-up TL tL Tsm ax Tsm in Ram p-down ts Preheat 25 t 25 °C to Peak Tim e Classificatin Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Large Body Small Body Average ramp-up rate 3°C/second max. (TL to TP) Preheat - Temperature Min (Tsmin) 100°C - Temperature Mix (Tsmax) 150°C - Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL - Temperature(TL) 183°C - Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C Time within 5°C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6°C/second max. 6 minutes max. Time 25°C to Peak Temperature Pb-Free Assembly Large Body Small Body 3°C/second max. 150°C 200°C 60-180 seconds 3°C/second max 217°C 60-150 seconds 245 +0/-5°C 250 +0/-5°C 10-30 seconds 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 18 www.hipacsemi.com HPL5331 Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Carrier Tape t D P Po E P1 Bo F W Ko Ao D1 T2 J C A B T1 Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 19 www.hipacsemi.com HPL5331 Carrier Tape Application SOP- 8 SOP-8-P A B 330 ± 1 F 5.5± 1 Application TO-252 Application TO-263 J T1 T2 W P E 62 +1.5 C 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 D D1 Po P1 Ao Bo Ko t 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013 T2 1.55 +0.1 1.55+ 0.25 A B C J 13 ± 0. 5 2 ± 0.5 2.5± 0.5 W 16+ 0.3 - 0.1 E 100 ± 2 T1 16.4 + 0.3 -0.2 P 330 ±3 8 ± 0.1 1.75± 0.1 F D D1 Po P1 Ao Bo Ko t 7.5 ± 0.1 1.5 +0.1 1.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 6.8 ± 0.1 10.4± 0.1 2.5± 0.1 0.3±0.05 A B C J T1 T2 P E 380±3 80 ± 2 13 ± 0. 5 2 ± 0.5 24 ± 4 2± 0.3 W 24 + 0.3 - 0.1 16 ± 0.1 1.75± 0.1 F D D1 Po P1 Ao Bo Ko t 11.5 ± 0.1 1.5 +0.1 1.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 10.8 ± 0.1 16.1± 0.1 5.2± 0.1 0.35±0.013 (mm) Cover Tape Dimensions Application SOP- 8 / SOP-8-P TO- 252 TO- 263 Carrier Width 12 16 24 Cover Tape Width 9.3 13.3 21.3 Devices Per Reel 2500 2500 1000 CONTACT HIPAC Semiconductor, Inc. 2540 North First Street, Suite 308 San Jose, CA 95131-1016 U.S.A. Tel: 1-408-943-0808 Fax: 1-408-943-0878 E-Mail: [email protected] Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 20 www.hipacsemi.com