APL5330 Dual Input 2A Low Dropout Regulator Features General Description • • The APL5330 integrates a power transistor to provide Fast Transient Response regulated voltage with maximum output current of 2A. High Output Accuracy It also incorporates current-limit, thermal shutdown and - ±20mV over Load, Output Voltage Offset and shutdown control functions into a single chip. Temperature • The current-limit circuit limits the maximum output Adjustable Output Voltage by External current in overload or short-circuit conditions. Resistors • • • • • The on-chip thermal shutdown provides protection Current-Limit Protection against any combination of overload that would create On-Chip Thermal Shutdown excessive junction temperature. The output voltage of Shutdown for Standby or Suspend Mode the APL5330 tracks the reference voltage on VREF Simple SOP-8 and SOP-8 with Thermal Pad pin. A resistor divider connected to VREF pin is Packages usually used to provide reference voltage to the IC. In addition, an external ceramic capacitor and an open-drain Lead Free Available (RoHS Compliant) transistor connected to VREF pin provides soft-start and shutdown control. Applying and holding a voltage below Applications • • 0.35V (typ.) to VREF shuts off the output. VGA Card Power Chip Set Power Pin Configuration VIN 1 8 VCNTL VIN 1 8 NC GND 2 7 VCNTL GND 2 7 NC VREF 3 6 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL VOUT 4 5 NC SOP-8 (Top View) SOP-8-P (Top View) NC = No internal connection = Thermal Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 1 www.anpec.com.tw APL5330 Ordering and Marking Information Package Code K : SOP-8 KA : SOP-8-P Operating Ambient Temp. Range E : -20 to 70 °C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APL5330 Lead Free Code Handling Code Temp. Range Package Code APL5330KE-TR : APL5330KAE-TR : APL5330 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Pin Description PIN NAME I/O VIN I GND O VCNTL I VREF I VOUT O DESCRIPTION Main power input pin. Connect this pin to a voltage source and an input capacitor. The APL5330 provides current from VIN pin to VOUT pin by controlling the NPN pass transistor. Signal ground. Power input pin for internal control circuitry. Connect this pin to a voltage source to provide a bias for the internal control circuitry. A bypass capacitor is usually connected near this pin. Reference voltage input and active-low shutdown control pin. Connect this pin to a resistor divider and a capacitor for soft-start and filtering noise purposes. Pulling and holding the voltage on this pin low by an open-drain transistor shuts down the output. Output pin of the regulator. Connect this pin to load. Output capacitors connected to this pin improves stability and transient response. The output voltage tracks the reference voltage, and the output pin provides the maximum current up to 2A. Block Diagram VIN VCNTL VREF Voltage Regulation Thermal Limit Current Limit VOUT Shutdown GND Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 2 www.anpec.com.tw APL5330 Absolute Maximum Ratings Symbol VCNTL Parameter VCNTL Supply Voltage, VCNTL to GND VIN VIN Supply Voltage, VIN to GND PD Power Dissipation TJ TSTG Rating -0.2 ~ 7 Unit V -0.2 ~ 3.9 V Internally Limited Junction Temperature Storage Temperature W 150 o C -65 ~ 150 o C o C TSDR Soldering Temperature, 10 Seconds 300 VESD Minimum ESD Rating (Human Body Mode) ±3 kV Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Thermal Resistance in Free Air SOP-8 SOP-8-P Junction-to-Case Thermal Resistance SOP-8 SOP-8-P Value Unit 75 55 o C/W 28 20 o C/W Note : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB. Recommended Operating Conditions Symbol VCNTL VIN Parameter VCNTL Supply Voltage (Note 1) VREF Input Voltage VOUT VOUT Output Voltage (Note 3) VOUT Output Current (Note 4) TJ Unit V 1.2 ~ 3.5 V 0.8 ~ 3 V VREF ± 0.02 V VIN Supply Voltage (Note 2) VREF IOUT Range 3.1 ~ 6 2 -20 ~ 125 Junction Temperature A o C Notes : 1. Please refer to the VCNTL-to-Vin Dropout Voltage in the “Typical Characteristics” section for the minimun supply voltage on VCNTL. 2. Please supply enough voltage to VIN for providing desired maximum output current. Please refer to the VIN. Dropout Voltage vs Output Current in the Typical Characteristics. 3. The VOUT is regulated to the VREF with additional voltage offset and load regulation except over-load conditions. 4. The maximum IOUT varies with the TJ and the voltages of VIN-VOUT and VOUT. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 3 www.anpec.com.tw APL5330 Electrical Characteristics Refer to the typical application circuit. These specifications apply over VCNTL = 3.3V, VIN = 2V, VREF = 1.2V and TA = -20 to 70°C, unless otherwise specified. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APL5330 Min Typ Max Unit OUTPUT VOLTAGE VOUT VOUT Output Voltage Load Regulation IOUT = 0A Over temperature, VOUT offset, and load regulation IOUT = 10mA to 2A VIN Dropout Voltage IOUT = 2A System Accuracy V VREF -20 -8 20 mV mV -3 0.7 0.47 V PROTECTION ILIM TSD TJ = 25°C TJ = 125°C Current Limit 2.4 Thermal Shutdown Rising TJ Temperature Thermal Shutdown Hysteresis 2.7 2.6 A 170 o 30 o C C INPUT CURRENT IOUT = 0A ICNTL IVREF 2 4 IOUT = 2A (Normal Operation) 25 50 VREF = GND (Shutdown) 0.3 Normal operation VREF Bias Current (The current flows out of VREF) VREF = GND (Shutdown) 150 500 300 5000 0.35 0.65 VCNTL Supply Current 0.5 mA nA SHUTDOWN CONTROL Shutdown Voltage Threshold 0.2 V Typical Application Circuit VCNTL +3.3V VIN +2V VIN R1 3.5k VREF Shutdown R2 2k CSS 0.1uF VCNTL CIN 47uF CCNTL 1uF GND COUT 330uF GND VOUT = VREFIN ⋅ Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 VOUT 1.2V/2A VREF GND VOUT 4 R2 (V) R1 + R2 www.anpec.com.tw APL5330 Typical Characteristics Current-Limit Quiescent VCNTL Current vs. Junction Temperature vs. Junction Temperature 2500 Quiescent VCNTL Current, ICNTL (µA) 3.5 VIN = 2V VOUT=1.2V Current-Limit, ILIM (A) 3 2.5 VCNTL = 5V VCNTL = 3.3V 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 1500 VCNTL = 5V VCNTL = 3.3V 1000 500 0 -50 -25 0 25 50 75 100 Junction Temperature (°C) VREF Threshold Voltage VREF Bias Current vs. Junction Temperature vs. VREF Supply Voltage 125 VREF Bias Current, IVREF (nA) 500 VCNTL = 5V VREF Threshold Voltage (V) 2000 Junction Temperature (°C) 0.6 0.5 0.4 0.3 VCNTL = 3.3V 0.2 0.1 450 400 350 VCNTL= 3.3V 300 VCNTL= 5V 250 200 150 100 50 0 0 -50 IOUT= 0A -25 0 25 50 75 100 0 125 1 1.5 2 2.5 3 VREF Supply Voltage (V) Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 0.5 5 www.anpec.com.tw APL5330 Typical Characteristics (Cont.) VIN Dropout Voltage VIN Dropout Voltage vs. Output Current vs. Output Current 0.6 0.6 VCNTL = 3.3V 0.4 VREF = 1.2V 0.5 VIN Dropout Voltage (V) 0.5 VIN Dropout Voltage (V) VCNTL = 5V TJ = 125oC VREF = 1.2V TJ = 75oC 0.3 TJ = 25oC 0.2 TJ = -25oC 0.1 TJ = 125oC 0.4 TJ = 75oC 0.3 TJ = -25oC TJ = 25oC 0.2 0.1 0 0 0 0.5 1 1.5 0 2 P.6 右上角的圖 0.5 1 1.5 Output Current (A) Output Current (A) VCNTL Input Current VCNTL-to-VOUT Dropout Voltage vs. VIN - VOUT Voltage at IOUT=1A vs. VCNTL Input Current Minimum VCNTL - VOUT Voltage (V) VCNTL Input Current, ICNTL (mA) 140 IOUT = 1A 120 100 TJ = 125oC TJ = 75oC 80 60 TJ = 25oC TJ = -25oC 40 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 3.8 IOUT = 1A 3.4 3 2.6 TJ = 25oC TJ = -25oC 2.2 TJ = 125oC 1.8 1.4 TJ = 75oC 1 0 20 40 60 80 100 120 VCNTL Input Current, ICNTL (mA) VIN - VOUT Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 2 6 www.anpec.com.tw APL5330 Typical Characteristics (Cont.) VCNTL Input Current VCNTL-to-VOUT Dropout Voltage vs. VIN - VOUT Voltage at IOUT=1.5A vs. VCNTL Input Current Minimum VCNTL - VOUT Voltage (V) VCNTL Input Current, ICNTL (mA) 140 IOUT = 1.5A 120 100 TJ = 125oC TJ = 75oC 80 60 TJ = 25oC 40 TJ = -25oC 20 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 TJ = 25oC 2.6 TJ = -25oC 2.2 TJ = 125oC 1.8 1.4 TJ = 75oC 1 20 40 60 80 100 VCNTL Input Current, ICNTL (mA) VCNTL Input Current VCNTL-to-VOUT Dropout Voltage vs. VIN - VOUT Voltage at IOUT=2A vs. VCNTL Input Current Minimum VCNTL - VOUT Voltage (V) VCNTL Input Current, ICNTL (mA) 3 VIN - VOUT Voltage (V) IOUT = 2A 120 TJ = 25oC 100 TJ = 75oC 80 TJ = 125oC 60 40 TJ = -25oC 0 0.4 IOUT = 1.5A 3.4 0 140 20 3.8 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 3.8 IOUT = 2A 3.4 3 2.6 TJ = 25oC TJ = -25oC 2.2 1.8 TJ = 125oC 1.4 TJ = 75oC 1 0 20 40 60 80 100 120 VCNTL Input Current, ICNTL (mA) VIN - VOUT Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 120 7 www.anpec.com.tw APL5330 Operating Waveforms 1. Load Transient Response : IOUT = 10mA -> 2A -> 10mA - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V - VREF is 1.2V supplied by a regulator - COUT = 330µF, ESR = 14mΩ - IOUT slew rate = 2A/µs Load Regulation = -2.8mV V OUT V OUT V OUT IOUT IOUT 10mA 2 Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 1µs/Div 1 1 1 IOUT 2A 2 2 Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 10µs/Div Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 1µs/Div 2. Short-Circuit Test - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V VOUT is Shorted to GND VOUT is Shorted to GND V OUT V OUT 1 1 IOUT IOUT 2 2 Ch1 : VOUT, 1V/Div, DC Ch2 : IOUT, 2A/Div Time : 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 Ch1 : VOUT, 1V/Div, DC Ch2 : IOUT, 2A/Div Time : 50ms/Div 8 www.anpec.com.tw APL5330 Operating Waveforms (Cont.) 3. Power on/off - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V V IN V IN 1 1 V OUT V OUT 2 2 IOUT IOUT 3 3 Ch1 : VIN, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 1ms/Div Ch1 : VIN, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 10ms/Div 4. Enable/Shutdown - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V VREF VREF 1 V OUT V OUT 2 2 IOUT IOUT 3 3 Ch1 : VREF, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 2ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 1 Ch1 : VREF, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 2ms/Div 9 www.anpec.com.tw APL5330 Application Information General The output voltage tracks the VREF voltage rises. The soft start function limits the input current. The APL5330 is a linear regulator and is capable of providing output current up to 2A. The APL5330 is Thermal Shutdown designed with the fast transient response, accurate A thermal shutdown circuit limits the junction temperature output voltage, active-low shutdown control and fault of the APL5330. When the junction temperature protections (current-limit, thermal shutdown). The exceeds TJ= +170oC, a thermal sensor turns off the APL5330 is available in two packages to meet wide range bypass transistor, allowing the device to cool down. of power dissipation requirements in various applications. The regulator starts to regulate again after the junction temperature reduces by 30oC, resulting in a Output Voltage Regulation pulsed output during continuous thermal overload The output voltage on VOUT pin tracks the reference conditions. The thermal limit designed with a 30oC voltage on VREF pin. A bypass NPN transistor controlled hysteresis lowers the average TJ during continuous by a high bandwidth error amplifier regulates the thermal overload conditions to extend life time of the output voltage by providing output current from VIN APL5330. pin to the output. The base current of the pass transistor is provided by the VCNTL pin. An internal kelvin Power Inputs sensing scheme is used at the VOUT pin for perfect Input power sequencing is not necessary for VIN and load regulation. Since the APL5330 exhibits very fast VCNTL voltage supplies. However, do not apply a load transient response, lesser amount of capacitors voltage to VOUT when there is no VCNTL voltage. This can be used. is because the internal parasitic diodes connected from Current Limit VOUT to VIN or VCNTL is forward bias. The APL5330 can supply few current to load when the input voltage on The APL5330 monitors the output current, and limits VIN is not present. the maximum output current to prevent damages during overload or short-circuit conditions. To increase Reference Voltage the input voltage on VIN or VCNTL will get higher The reference voltage is applied to the VREF pin current-limit points. connected with a resistor divider. Normally the bias Shutdown and Soft-Start current of the VREF pin flows out of the IC and is about 150nA (typ.), creating a voltage offset to the The VREF pin is a dual-function input pin, acting as resistor divider and affecting the output voltage reference input and shutdown control input. Applying accuracy. The recommended resistors are <5kΩ to and holding a voltage below 0.35V(typ.) to VREF pin maintain the accurate output voltage. An external shuts down the output of the regulator. An NPN bypass capacitor is also connected to VREF. The transistor or N-channel MOSFET is normaly used to pull down the VREF voltage while applying a “high” signal to turn on the transistor. When release the VREF capacitor (>0.1µF) and the resistor divider form a low-pass filter to reduce the inherent reference noise. Connect the capacitor as close to VREF as possible pin, the current through the resistor divider charges for optimal effect. More capacitance and large resistor the soft-start capacitor to initiate a soft-start process. divider will increase the soft-start interval. Do not place any additional loading on this reference input pin. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 10 www.anpec.com.tw APL5330 Application Information (Cont.) Output Capacitor For VCNTL pin, a capacitor of 1µF (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) The APL5330 requires a proper output capacitor to is recommended. For VIN pin, an aluminum electrolytic maintain stability and improve transient response. capacitor (>47µF) is recommended. It is not necessary The APL5330 can work stably with wide range of to use low-ESR capacitors. capacitance and ESR (equivalent series resistance). Layout and Thermal Consideration A low-ESR solid tantalum, aluminum electrolytic or ceramic output capacitor works extremely well and The input capacitors for VIN and VCNTL pins are normally provides good transient response and stability over placed near each pin for good performances. Ceramic temperature. decoupling capacitors of output must be placed as close to the load to reduce the parasitic inductance of The output capacitors also reduce the slew rate of load traces. It is also recommended to place the APL5330 current and help the APL5330 to minimize variations and output capacitors near the load for good load of the output voltage. For this purpose, the low-ESR regulation and load transient response. Please connect capacitors which depend on the step size and slew the negative pins of the input and output capacitors rate of load current are recommended. and the GND pin of the APL5330 to the power ground 25 plane of the load. ESR (m Ω) 20 See figure 1. The SOP-8-P utilizes a bottom thermal pad to minimize the thermal resistance of the package 15 and make the package suitable for high current Stable Region applications. The thermal pad is soldered to the top 10 ground pad connected to the internal or bottom ground plane by several vias. The printed circuit board (PCB) 5 forms a heat sink and dissipates most of the heat into ambient air. It is recommended that the vias have 0 10 100 proper size to retain solder and help heat conduction. 1000 Capacitance (uF) Thermal resistance consists of two main elements, Input Capacitor θJC (junction-to-case thermal resistance) and θCA The input capacitors of VCNTL and VIN pins are not (case-to-ambient thermal resistance). θJC is specified required for stability but for supplying surge current from the IC junction to the bottom of the thermal pad during large load transients. This will prevent the input directly below the die. θCA is the resistance from the rail from dropping and improve the performance of the bottom of thermal pad to the ambient air and it includes APL5330. The parasitic inductors between voltage θCS (case-to-sink thermal resistance) and θSA (sink-to- sources or bulk capacitors and the power input pins ambient thermal resistance). The specified path for will limit the slew rate of the surge currents during heat flow is the lowest resistance path and it dissipates large load transients, resulting in voltage drop at VIN majority of the heat to the ambient air. Typically, θCA is and VCNTL pins. the dominant thermal resistance. Therefore, enlarging Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 11 www.anpec.com.tw APL5330 Application Information (Cont.) Layout and Thermal Consideration (Cont.) the internal or bottom ground plane reduces the resistance θ CA . The relationship between power di s s ipa tio n and temperatures is the following equation: PD = (TJ - TA) / ≤ θJA where, PD : Power dissipation TJ : Junction Temperature TA : Ambient Temperature θJA : Junction-to-Ambient Thermal Resistance 102 mil 118 mil SOP-8-P Die Thermal pad Top ground pad Ambient Air Vias Internal Printed g r o u n d circuit plane board Figure 1 Top and side view of layout around the APL5330 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 12 www.anpec.com.tw APL5330 Packaging Information E e1 0.015X45 SOP-8 pin (Reference JEDEC Registration MS-012) H e2 D A1 A 1 L 0.004max. Dim Millimeters Inches Min. Max. Min. Max. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 φ1 1.27BSC 0° Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 0.50BSC 8° 13 0° 8° www.anpec.com.tw APL5330 Packaging Information E1 E 0.015X45 SOP-8-P pin ( Reference JEDEC Registration MS-012) H D1 e1 e2 D A1 A 1 L 0.004max. Dim Millimeters Inches Min. Max. Min. Max. A 1.35 1.75 0.053 0.069 A1 0 0.15 0 0.006 D 4.80 5.00 0.189 0.197 4.00 0.150 D1 E 3.00REF 3.80 E1 0.118REF 2.60REF 0.157 0.102REF H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 1.27BSC 0.50BSC φ1 8° 8° Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 14 www.anpec.com.tw APL5330 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 15 www.anpec.com.tw APL5330 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 ≥350 <2.5 m m 240 +0/-5°C 225 +0/-5°C ≥2.5 m m 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0°C* 260 +0°C* 260 +0°C* 1.6 m m – 2.5 m m 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 m m 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Carrier Tape t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 D1 16 www.anpec.com.tw APL5330 Carrier Tape(Cont.) T2 J C A B T1 Application SOP- 8/ SOP-8-P A B C J T1 T2 W P E 330 ± 1 62 +1.5 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 F D D1 Po P1 Ao Bo Ko t 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 5.5± 1 1.55 +0.1 1.55+ 0.25 2.1± 0.1 0.3±0.013 (mm) Cover Tape Dimensions Application SOP- 8 / SOP-8-P Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 17 www.anpec.com.tw