NT511740D5J 16MEG : x4 CMOS with Extended Data Out NT511740D5J DATA SHEET REV 1.0 May. 2000 1 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Contents Table of Contents.........................................................................................................................................................02 Description ...................................................................................................................................................................03 Features........................................................................................................................................................................03 Product Family ............................................................................................................................................................03 Pin Assignment............................................................................................................................................................04 Electrical Characteristics ............................................................................................................................................05 Absolute Maximum Ratings ......................................................................................................................................05 Recommended DC Operating Conditions .....................................................................................................................05 Capacitance ..........................................................................................................................................................05 DC Electrical Characteristics .....................................................................................................................................06 AC Characteristics .......................................................................................................................................................07 Timing Waveform.........................................................................................................................................................10 Read Cycle ...........................................................................................................................................................10 Write Cycle ...........................................................................................................................................................10 Read Modify Write Cycle ..........................................................................................................................................11 Fast Page Mode Read Cycle .....................................................................................................................................11 Fast Page Mode Write Cycle .....................................................................................................................................12 Fast Page Mode Read Modify Write Cycle ....................................................................................................................13 RAS -only Refresh Cycle ........................................................................................................................................13 CAS -before- RAS refresh ..................................................................................................................................14 Hidden Refresh Read..........................................................................................................................................15 Package Dimension .....................................................................................................................................................16 REV 1.0 May. 2000 2 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V ), refresh cycle (2K Ref), access time (-5 or -6), power consumption (Normal or Low power) and package type (SOJ) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 EDO Mode DRAM family is fabricated using NANYA’s advanced CMOS process to realize high bandwidth, low power consumption and high reliability. It may be used as main memory unit for microcomputer, high level computer and personal computer . FEATURES • • • • Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) TTL(5V) compatible inputs and outputs Single +5V ± 10% power supply (5V product) JEDEC Standard pinout • • • • • CAS before RAS refresh, hidden refresh, RAS -only refresh capability Refresh : 2048 cycles / 32 ms Self-refresh capability (L-ver only) Multi-bit test mode capability Available in plastic SOJ packages PRODUCT FAMILY Family Active Power Access Time (Max.) tRAC tCAC tRC tHPC Dissipation NT511740D5J - 50/5L 50ns 15ns 84ns 20ns 605mW NT511740D5J - 60/6L 60ns 17ns 104ns 25ns 550mW REV 1.0 May. 2000 Voltage 5V Package 26(24)-pin SOJ 3 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out PIN CONFIGURATION (TOP VIEW) NT511740D5J 1 ¡´ 24 Vss DQ0 2 23 DQ3 DQ1 3 22 DQ2 W 4 21 CAS RAS 5 20 OE NC 6 19 A9 A10 7 18 A8 A0 8 17 A7 A1 9 16 A6 A2 10 15 A5 A3 11 14 A4 Vcc 12 13 Vss VCC 300mil 26(24)-pin SOJ Pin Name A0-A10 DQ0-DQ3 REV 1.0 May. 2000 Pin Function Address Inputs Data Input / Output Vss Ground RAS Row Address Strob CAS Column Address Strob W Read/Write Input OE Data Output Enable VCC Power +5.0 V ( + 3.3V ) NC No Connection 4 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VIN,VOUT -1.0 to +7.0 V Voltage on VCC Supply Relative to VSS VCC -1.0 to +7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operation Temperature Topr 0 to 70 °C Voltage on Any Pin Relative to VSS Storage Temperature Tstg -55 to 150 °C *:Ta = 25°C • Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Voltage referenced to Vss, Ta = 0°C to 70°C ) Parameter Symbol Min. Typ. Max. Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 Input High Voltage VIH 2.4 Input Low Voltage VIL *1 : Vcc +2.0V/20ns(5V), Pulse width is measured at Vcc *2 : -2.0V/20ns(5V), Pulse width is measured at Vss -1.0 - *2 V *1 Vcc+1.0 - 0.8 V V Capacitance ( Vcc = 5V, Ta = 25°C, f = 1 MHZ ) Parameter Input Capacitance (A0-A11) Input Capacitance ( RAS , CAS , WE , OE ) Output Capacitance (DQ0-DQ3) Symbol Typ. Max. Unit CIN1 - 5 pF CIN2 - 7 pF CI/O - 7 pF DC Characteristics (Recommended operating conditions unless otherwise noted.) Max Parameter Symbol Min Max Units II(L) -5 5 uA IO(L) -5 5 uA Output High Voltage Level (IOH= -5mA) VOH 2.4 - V Output Low Voltage Level (IOL=4.2mA) VOL - 0.4 V Input Leakage Current (Any input 0 <= VIN <= VIN+0.5V, all other input pins not under test =0 Volt) 5V Output Leakage Current (Data out is disabled, 0 <= VOUT <= VCC) REV 1.0 May. 2000 5 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out DC CHARACTERISTICS ( Continued ) Symbol Power ICC1 Don’t care Normal ICC2 L ICC3 Don’t care ICC4 Don’t care Normal ICC5 L Speed Max Units -5 110 mA -6 100 mA 2 mA 1 mA -5 110 mA -6 100 mA -5 90 mA -6 80 mA 3 mA Don’t care Don’t care 200 uA -5 110 mA -6 100 mA ICC6 Don’t care ICC7 L Don’t care 300 uA ICCS L Don’t care 250 uA ICC1* : Operating Current ( RAS and CAS cycling @ t RC=min.) ICC2 : Standby Current ( RAS = CAS = W =VIH) ICC3* : RAS -only Refresh Current ( RAS =VIH, RAS cycling @ t RC=min.) ICC4* : Hyper Page Mode Current ( RAS =VIL, CAS Address cycling @ t HPC=min.) ICC5 : Standby Current ( RAS = CAS = W =VCC-0.2V) ICC6* : CAS-Before- RAS Refresh Current ( RAS , CAS cycling @ t RC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage (VIH)=VCC-0.2V, Input low voltage (VIL)=0.2V, CAS =0.2V, DQ=Don’t care, t RC=125us(2K/L-ver) , t RAS=tRASmin~300ns ICCS : Self Refresh Current ( RAS = CAS =0.2V, W = OE =A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or open ) *Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS =VIL. In ICC4, address can be changed maximum once within one hyper page mode cycle time, t HPC. REV 1.0 May. 2000 6 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out AC CHARACTERISTICS (0°C <= Ta <= 70°C , See note 1,2) ; Test condition : VCC=5.0V ± 10%, VIH/VIL=2.4/0.8V, VOH/VOL=2.0/0.8V Parameter Symbol -50 -60 Min Max Min Max - 104 - Unit Notes Random read or write cycle time t RC 84 Read-modify-write cycle time t RWC 110 Access time from RAS t RAC 50 60 ns 3,4,10 Access time from CAS t CAC 13 15 ns 3,4,5 Access time from column address t AA 30 ns 3,10 CAS to output in Low-Z t CLZ 0 0 ns 3 Output buffer turn-off delay from CAS t CEZ 0 0 ns 6,14 OE to output in Low-Z t OLZ 0 0 ns 3 Transition time (rise and fall) tT 1 1 ns 2 RAS precharge time t RP 30 40 ns RAS pulse width t RAS 50 60 ns RAS hold time t RSH 7 10 ns CAS hold time t CSH 35 40 ns CAS pulse width t CAS 7 10 ns RAS to CAS delay time t RCD 11 14 ns 4 RAS to column address delay time t RAD 9 12 ns 10 CAS to RAS precharge time t CRP 5 5 ns Row address set-up time t ASR 0 0 ns Row address hold time t RAH 7 10 ns Column address set-up time t ASC 0 0 ns 135 25 ns ns Column address hold time t CAH 7 10 ns Column address to RAS lead time t RAL 25 30 ns Read command set-up time t RCS 0 0 ns Read command hold time referenced to CAS t RCH 0 0 ns 8 Read command hold time referenced to RAS t RRH 0 0 ns 8 Write command hold time t WCH 7 10 ns Write command pulse width t WP 7 10 ns Write command to RAS lead time t RWL 7 10 ns Write command to CAS lead time t CWL 7 10 ns Data set-up time t DS 0 0 ns 9 Data hold time t DH 7 10 ns 9 Refresh period (2K, Normal) t REF 32 32 ms Refresh period (L-ver) t REF 128 128 ms Write command set-up time t WCS REV 1.0 May. 2000 0 0 ns 7 7 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out AC CHARACTERISTICS (Continued ) Parameter Symbol -50 Min -60 Max Min Max Unit Notes CAS to W delay time t CWD 30 34 ns 7 RAS to W delay time t RWD 67 79 ns 7 Column address to W delay time t AWD 42 49 ns 7 CAS precharge to W delay time t CPWD 47 54 ns CAS set-up time ( CAS -before- RAS refresh) t CSR 5 5 ns CAS hold time ( CAS -before- RAS refresh) t CHR 10 10 ns RAS to CAS precharge time t RPC 5 5 ns Access time from CAS precharge t CPA Hyper Page cycle time t HPC 20 Hyper Page read-modify-write cycle time t HPRWC CAS precharge time (Hyper Page cycle) 28 ns 3 25 ns 13 47 56 ns 13 t CP 7 10 ns RAS pulse width (Hyper Page cycle) t RASP 50 30 100k 35 60 100k ns 15 ns RAS hold time from CAS precharge t RHCP OE access time t OEA 35 OE to data delay t OED 12 15 ns Output buffer turn off delay time from OE t OEZ 3 3 ns OE command hold time t OEH 7 10 ns Write command set-up time (Test mode in) t WTS 7 10 ns 11 Write command hold time (Test mode in) t WTH 10 10 ns 11 W to RAS precharge time(C-B-R refresh) t WRP 10 10 ns 13 ns 6 W to RAS hold time(C-B-R refresh) t WRH 10 10 ns Output data hold time t DOH 5 5 ns Output buffer turn off delay from RAS t REZ 0 0 ns 6,14 Output buffer turn off delay from W t WEZ 0 0 ns 6 W to data delay t WED 10 10 ns OE to CAS hold time t OCH 5 5 ns CAS hold time to OE t CHO 5 5 ns OE precharge time t OEP 7 10 ns W pulse width (Hyper Page Cycle) t WPE 7 10 ns RAS pulse width (C-B-R self refresh) t RASS 100 100 ns 15,16,17 RAS precharge time (C-B-R self refresh) t RPS 90 110 ns 15,16,17 CAS hold time (C-B-R self refresh) t CHS -50 -50 ns 15,16,17 REV 1.0 May. 2000 8 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh Cycles before proper device operation is achieved. 2. VIH(min) and VlL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VI L(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the t RCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD >= tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS >= t WCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If t CWD >= t CWD(min), t RWD >= t RWD(min) and tAWD >= tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled Write Cycle and read-modify-write cycles. 9. Operation within the tRAD (max) limit insures that tRAD(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA . 10. These specifications are applied in the test mode. 11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These Parameters should specified in test mode cycles by adding the above value to the specified value in this data sheet. 12. tASC>= 6ns, Assume t T = 2.0ns 13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 14. If tRASS>= 100us, then RAS precharge time must use t RPS instead of t RP. 15. For RAS-only refresh and burst CAS -before- RAS refresh mode, 2048(2K) cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification.. 16. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. REV 1.0 May. 2000 9 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out TIMING WAVEFORM Read Cycle RAS tRC tRP tRAS V IH V IL tCRP tCSH tCRP CAS tRCD V IH V IL tRSH tCAS tRAD tRAL tASR Address V IH V IL tRAH tASC Row tCAH Column tRCH tRCS WE tRRH V IH V IL tAA tROH tOEA OE tREZ V IH V IL tCEZ tCAC tRAC DQ V IH V IL tOEZ Open Valid Data-out tCLZ "H" or "L" Write Cycle(Early Write) RAS tRC tR P tRAS V IH V IL tCRP t CSH tCRP tRCD CAS V IH V IL tRSH tCAS tRAD tRAL tASR Address V IH V IL tRAH tASC Row tCAH Column tCWL tWCS WE V IH V IL OE V IH V IL tWCH tWP tRWL tD S DQ V IH V IL t DH Open Valid data-in "H" or "L" REV 1.0 May. 2000 10 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Read Modify Write Cycle RAS tRWC tR P tRAS V IH V IL tCRP tCSH tCRP CAS tRCD tCAS tASR Address tRSH V IH V IL V IH V IL tRAH tASC Row tCAH Column tCWD tRAD tCWL tRWD WE V IH V IL tRWL tWP tAA tAWD tRCS OE tOEA V IH V IL tOED tOEH t CAC t RAC DQ tOEZ V IH V IL tCLZ tD S Valid Data-out tDH Valid Data-in "H" or "L" Fast Page Mode Read Cycle (Part-1) tR P t RASP RAS VIH VIL t RHCP t HPC t CRP CAS VIH VIL t RCD t CP tC P t CAS t CAS t CAS t RAD t CSH t ASR Address VIH VIL WE VIH VIL t RAH Row t ASC t CAH t ASC Column t CAH t ASC Column t CAH Column t RRH t RCS t OCH t CHO t RAC t OEP t AA OE VIH VIL t OEP t AA t OEA t AA t OEA t CPA t CAC t CAC DQ VIH VIL t CLZ t OEZ t DOH Valid Data-out Valid Data-out t OEA t CAC t REZ t OEZ Valid Data-out Valid Data-out "H" or "L" REV 1.0 May. 2000 11 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Fast Page Mode Read Cycle(Part-2) tRASP RAS tR P V IH V IL tRHCP t CRP tHPC tCRP CAS tRCD V IH V IL tC P tC P tCAS tCAS t CAS t RAD tCSH tASR Address V IH V IL WE V IH V IL tRAH t ASC Row tCAH tASC Column tCAH tASC Column tRCS Column t RCS tRCH tWPE t RAC t AA tAA tAA OE t CAH V IH V IL tCPA tOEA tWEZ tCAC DQ V IH V IL tCEZ H Valid Data-out tCLZ t CAC t DO tCAC Valid Data-out Valid Data-out "H" or "L" Fast page Mode Write Cycle(Early Write) t RASP RAS tR P V IH V IL tHPC tCRP CAS tRCD V IH V IL tHPC tC P tC P tCAS tCAS tCAS t RAD tRSH tCSH tASR Address V IH V IL WE V IH V IL OE V IH V IL DQ V IH V IL tRAH tASC Row tCAH Column tWCS tD S t WCH tDH Valid Data-in tASC tCAH tASC Column tWCS tD S tCAH Column tWCS tWCH tDH tD S Valid Data-in tWCH t DH Valid Data-in "H" or "L" REV 1.0 May. 2000 12 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Fast Page Mode Read Modify Write Cycle t RASP RAS VIH VIL CAS VIH VIL t RWD t CRP tC P t RCD t CWD t RAD t CPWD t HPRWC t ASR t RAH t ASC Address VIH VIL Row t CAH t ASC t CWL Column t RWL t CPA t CAH Column t RCS t AWD t CWD t RCS WE VIH VIL t AWD tD S t RAC t WP tD S t AA OE t AA VIH VIL t OEH t OEH t OEA t OEA t OED t OED t CAC DQ t WP VIH VIL t OEZ Valid Data-out t CLZ t DH t CAC Valid Data-in t DH t OEZ Valid Data-out Valid Data-in t CLZ "H" or "L" RAS-only Refresh Cycle RAS t RC t RP t RAS VIH VIL t RPC t CRP CAS VIH VIL Address VIH VIL DQ VIH VIL t ASR t RAH Row t CEZ Open Note:WE,OE="H" or "L" REV 1.0 May. 2000 "H" or "L" 13 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out CAS before RAS Refresh Cycle t RC t RAS tR P RAS VIH VIL t RPC t CP CAS VIH VIL WE VIH VIL DQ VIH VIL t RP t CSR t RPC t CHR t WR t WRP t WRH P t CEZ Open Note:OE,Address="H" or "L" Hidden Refresh Read Cycle RAS tR P tR P t RAS VIH VIL t CHR t CRP CAS t RC t RC t RAS "H" or "L" t RCD VIH VIL t RSH t RAD t RAH t ASC t ASR Address VIH VIL Row t CAH Column t RCS t RAL WE VIH VIL t RRH t AA t ROH OE t OEA VIH VIL t CAC t CEZ t CLZ t REZ t RAC DQ VIH VIL Open t OEZ Valid Data-out "H" or "L" REV 1.0 May. 2000 14 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Hidden Refresh Write Cycle t RC t RC t RAS RAS t RCD VIH VIL t RSH t RAD t RAL t ASC t ASR VIH VIL tR P t CHR t RAH Address t RAS VIH VIL t CRP CAS tR P Row t CAH Column t RWL t WCS WE VIH VIL OE VIH VIL DQ VIH VIL t WCH t WP tD S t DH Valid Data-in "H" or "L" REV 1.0 May. 2000 15 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out PACKAGE DIMENSION 24/26-PIN PLASTIC SOJ (300mil) 17.27 17.01 7.75 7.49 8.60 8.34 3.75 3.25 0.32 0.17 PIN #1 INDEX 2.63 TYP. SEATING 0.95 TPY 1.27 MAX NOTE : All dimensions in millimeters MIN REV 1.0 May. 2000 0.50 0.38 0.81 MAX 6.98 6.48 0.635 MIN or typical where noted. 16 © NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.