Industrial Temperature K4E661612D,K4E641612D CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Normal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated u s i n g S a m s u n g ′s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y . FEATURES • Extended Data Out Mode operation • Part Identification • 2 CAS Byte/Word Read/Write operation - K4E661612D-TI/P(3.3V, 8K Ref.) • C A S-before-R A S refresh capability - K4E641612D-TI/P(3.3V, 4K Ref.) • R A S-only and Hidden refresh capability • Fast parallel test mode capability • Self-refresh capability (L-ver only) • LVTTL(3.3V) compatible inputs and outputs • Active Power Dissipation • Early Write or output enable controlled write Unit : m W • JEDEC Standard pinout Speed 8K 4K -45 324 468 -50 288 432 -60 252 396 • Available in Plastic TSOP(II) packages • * • + 3 . 3 V ±0 . 3 V p o w e r s u p p l y • I n d u s t r i a l T e m p e r a t u r e o p e r a t i n g ( - 4 0 ~ 8 5°C ) Refresh Cycles Part Refresh NO. cycle K4E661612D* 8K K4E641612D 4K FUNCTIONAL BLOCK DIAGRAM Refresh time Normal L-ver 64ms 128ms RAS UCAS LCAS W Control Clocks Vcc Vss VBB Generator Access mode & R A S only refresh mode Lower Data in Buffer : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) Refresh Control Refresh Counter • Performance Range Speed -45 tR A C 45ns tC A C 12ns tR C 74ns tH P C 17ns -50 50ns 13ns 84ns 20ns -60 60ns 15ns 104ns 25ns A0~A12 (A0~A11)*1 Row Address Buffer A0~A8 (A0~A9)*1 Col. Address Buffer Memory Array 4,194,304 x 16 Cells Column Decoder S en s e A m p s & I/ O Refresh Timer C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e Row Decoder Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer Note) *1 : 4K Refresh S A M S U N G E L E C T R O N I C S C O . , L T D . reserves the right to change products and specifications without notice. DQ0 to DQ7 OE D Q8 to DQ15 Industrial Temperature K4E661612D,K4E641612D CMOS DRAM PIN CONFIGURATION (Top Views) • K4E661612D-T • K4E641612D-T V CC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 N.C V SS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 V SS (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection Industrial Temperature K4E661612D,K4E641612D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN, VO U T -0.5 to +4.6 V Voltage on VC C supply relative to VSS V CC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C PD 1 W IOS Address 50 mA Voltage on any pin relative to VSS Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter (Voltage referenced to Vss, T A= -40 to 85°C) Symbol Min Typ Max Units Supply Voltage VC C 3.0 3.3 3.6 V Ground VSS 0 0 0 V *1 Input High Voltage VI H 2.0 - Vcc+0.3 V Input Low Voltage V IL -0.3 *2 - 0.8 V *1 : Vcc+1.3V at pulse width ≤15ns which is measured at VC C *2 : -1.3 at pulse width≤15ns which is measured at V SS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤V I N≤V CC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤V OUT ≤VCC ) I O(L) -5 5 uA Output High Voltage Level(IO H=-2mA) VO H 2.4 - V Output Low Voltage Level(I OL =2mA) V OL - 0.4 V Industrial Temperature K4E661612D,K4E641612D CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Max Symbol IC C 1 IC C 2 IC C 3 IC C 4 IC C 5 IC C 6 Power D o n ′t c a r e Normal L D o n ′t c a r e D o n ′t c a r e Normal L D o n ′t c a r e Speed Units K4E661612D K4E641612D -45 90 130 m A -50 80 120 m A -60 70 110 m A 1 1 m A 1 1 m A -45 90 130 m A -50 80 120 m A -60 70 110 m A -45 100 100 m A -50 90 90 m A -60 80 80 m A D o n ′t c a r e 0.5 0.5 m A 200 200 uA -45 130 130 m A -50 120 120 m A -60 110 110 m A D o n ′t c a r e IC C 7 L D o n ′t c a r e 350 350 uA IC C S L D o n ′t c a r e 350 350 uA IC C 1* : O p e r a t i n g C u r r e n t ( R A S a n d U C A S , L C A S , A d d r e s s c y c l i n g @ t R C = m i n . ) I C C 2 : S t a n d b y C u r r e n t ( R A S = U C A S = L C A S = W = V IH ) I C C 3 * : R A S - o n l y R e f r e s h C u r r e n t ( U C A S = L C A S = V IH , R A S , A d d r e s s c y c l i n g @ t R C = m i n . ) I C C 4 * : E x t e n d e d D a t a O u t M o d e C u r r e n t ( R A S = V IL , U C A S o r L C A S , A d d r e s s c y c l i n g @ t H P C = m i n . ) IC C 5 : S t a n d b y C u r r e n t ( R A S = U C A S = L C A S = W = V CC - 0 . 2 V ) I C C 6 * : C A S - B e f o r e - R A S R e f r e s h C u r r e n t (R A S a n d U C A S o r L C A S c y c l i n g @ t R C = m i n ) IC C 7 : B a t t e r y b a c k - u p c u r r e n t , A v e r a g e p o w e r s u p p l y c u r r e n t , B a t t e r y b a c k - u p m o d e I n p u t h i g h v o l t a g e ( V IH ) = V C C - 0 . 2 V , I n p u t l o w v o l t a g e ( V IL ) = 0 . 2 V , U C A S , L C A S = C A S - b e f o r e - R A S c y c l i n g o r 0 . 2 V W , O E = V IH , A d d r e s s = D o n ′ t c a r e , D Q = O p e n , T R C = 3 1 . 2 5 u s IC C S : S e l f R e f r e s h C u r r e n t R A S = U C A S = L C A S = 0 . 2 V , W = O E = A 0 ~ A 1 2 ( A 1 1 ) = V C C- 0 . 2 V o r 0 . 2 V , D Q 0 ~ D Q 1 5 = V CC- 0 . 2 V , *Note : 0.2V or Open I C C 1 , I C C 3 , IC C 4 a n d I C C 6 a r e d e p e n d e n t o n o u t p u t l o a d i n g a n d c y c l e r a t e s . S p e c i f i e d v a l u e s a r e o b t a i n e d w i t h t h e o u t p u t o p e n . I C C i s s p e c i f i e d a s a n a v e r a g e c u r r e n t . I n I C C 1 , IC C 3 a n d I C C 6 , a d d r e s s c a n b e c h a n g e d m a x i m u m o n c e w h i l e R A S = V I L. I n I C C 4 , a d d r e s s c a n b e c h a n g e d m a x i m u m o n c e w i t h i n o n e E D O m o d e c y c l e t i m e , t HPC. Industrial Temperature K4E661612D,K4E641612D CAPACITANCE CMOS DRAM (T A = 2 5 °C , V CC = 3 . 3 V , f = 1 M H z ) Symbol Min Max Un i ts Input capacitance [A0 ~ A12] Parameter C IN1 - 5 pF I n p u t c a p a c i t a n c e [R A S , U C A S , L C A S , W , O E ] C IN2 - 7 pF Output capacitance [DQ0 - DQ15] C DQ - 7 pF AC CHARACTERISTICS ( - 4 0 °C ≤ T A ≤ 8 5 °C , S e e n o t e 2 ) T e s t c o n d i t i o n : V CC = 3 . 3 V ±0 . 3 V , V i h / V i l = 2 . 2 / 0 . 7 V , V o h / V o l = 2 . 0 / 0 . 8 V -45 Parameter -50 -60 Unit Symbol Min Max Min Max Min Max s 74 84 104 ns 101 113 138 ns Note Random read or write cycle time tRC Read-modify-write cycle time tRWC Access time fromRAS tRAC 45 50 60 ns 3,4,10 Access time fromCAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 C A S to output in Low-Z tCLZ 3 ns 3 Output buffer turn-off delay from C A S ns 6,20 ns 3 ns 2 3 13 3 3 tCEZ 3 O E to output in Low-Z t OLZ 3 13 Transition time (rise and fall) tT 1 R A S precharge time tR P 25 R A S pulse width tRAS 45 R A S hold time tRSH 8 8 10 ns C A S hold time tCSH 35 38 40 ns C A S pulse width tCAS 7 5K 8 10K 10 10K ns R A S to C A S d e l a y t i m e tRCD 11 33 11 37 14 45 ns 4 R A S to column address delay time tRAD 9 22 9 25 12 30 ns 10 C A S to R A S p r e c h a r g e t i m e 3 50 1 50 13 3 50 30 10K 3 1 50 40 10K 60 ns 10K ns tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 7 7 10 ns Column address set-up time tASC 0 0 0 ns 13 Column address hold time tCAH 7 7 10 ns 13 Column address to R A S lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 7 7 10 ns Write command pulse width tW P 6 7 10 ns Write command to R A S lead time tRWL 8 8 10 ns Write command to C A S lead time tCWL 7 7 10 ns 16 Data set-up time tD S 0 0 0 ns 9,19 Industrial Temperature K4E661612D,K4E641612D AC CHARACTERISTICS CMOS DRAM (Continued) Parameter -45 Symbol Min -50 Max 7 Min -60 Max 7 Min Units Note ns 9,19 Max Data hold time tD H 10 Refresh period (Normal) tR E F 64 64 64 ms Refresh period (L-ver) tR E F 128 128 128 ms Write command set-up time tW C S 0 0 0 ns 7 C A S to W d e l a y t i m e tC W D 24 27 32 ns 7,15 R A S to W d e l a y t i m e tR W D 57 64 77 ns 7 Column address to W delay time tA W D 35 39 47 ns 7 C A S set-up time ( C A S -before-R A S refresh) tC S R 5 5 5 ns 17 C A S hold time (C A S -before-R A S refresh) tC H R 10 10 10 ns 18 R A S to C A S p r e c h a r g e t i m e tR P C 5 5 Access time from C A S precharge tC P A Hyper Page tH P C 17 20 Hyper Page read-modify-write cycle time tH P R W C 47 C A S precharge time (Hyper page cycle) tC P 6.5 R A S pulse width (Hyper page cycle) tR A S P 45 R A S hold time from C A S precharge tR H C P 24 cycle time 24 200K 5 28 ns ns 3 25 ns 21 47 56 ns 21 7 10 ns 14 50 200K 30 12 35 60 200K 35 13 ns ns O E access time 15 tO E A ns O E to data delay tO E D C A S precharge to W delay time tC P W D Output buffer turn off delay time from O E tO E Z 3 O E command hold time tO E H 5 5 5 ns Write command set-up time (Test mode in) tW T S 10 10 10 ns 11 Write command hold time (Test mode in) tW T H 10 10 10 ns 11 W to R A S p r e c h a r g e t i m e ( C - B - R r e f r e s h ) tW R P 10 10 10 ns W to R A S h o l d t i m e ( C - B - R r e f r e s h ) tW R H 10 10 10 ns Output data hold time tD O H 4 5 5 ns Output buffer turn off delay from RAS tR E Z 3 13 Output buffer turn off delay from W 13 8 10 13 ns 36 41 52 ns 11 3 13 3 13 3 13 3 13 ns 3 6 3 13 ns 6,20 3 13 ns 6 tW E Z 3 W to data delay tW E D 8 15 15 ns O E to C A S h o l d t i m e tO C H 5 5 5 ns C A S hold time to OE tC H O 5 5 5 ns O E precharge time tO E P 5 5 5 ns W pulse width (Hyper Page Cycle) tW P E 5 5 5 ns R A S pulse width (C-B-R self refresh) tR A S S 100 100 100 us 22,23,24 90 110 ns 22,23,24 -50 -50 ns 22,23,24 R A S precharge time (C-B-R self refresh) tR P S 74 C A S hold time (C-B-R self refresh) tC H S -50 Industrial Temperature K4E661612D,K4E641612D CMOS DRAM TEST MODE CYCLE ( Note 11 ) -45 Parameter -50 -60 Symbol Units Min Max Min 79 89 110 121 Max Min Note Max Random read or write cycle time tR C Read-modify-write cycle time tR W C Access time fromR A S tR A C 50 55 65 ns 3,4,10,12 Access time fromC A S tC A C 17 18 20 ns 3,4,5,12 Access time from column address tA A 28 30 35 ns 3,10,12 R A S pulse width tR A S 50 10K 55 10K 65 10K ns C A S pulse width tC A S 12 10K 13 10K 15 10K ns R A S hold time tR S H 18 18 20 ns C A S hold time tC S H 39 43 50 ns Column Address to R A S lead time tR A L 28 30 35 ns C A S to W d e l a y t i m e tC W D 29 35 39 ns 7 R A S to W d e l a y t i m e tR W D 62 72 84 ns 7 Column Address to W delay time tA W D 40 47 54 ns 7 Hyper Page cycle time tH P C 22 25 30 ns 21 Hyper Page read-modify-write cycle time tH P R W C 52 53 61 ns 21 R A S pulse width (Hyper page cycle) tR A S P 50 Access time fromC A S precharge tC P A 29 O E access time tO E A 17 O E to data delay tO E D 13 18 20 ns O E command hold time tO E H 13 18 20 ns 200K 55 200K 109 ns 145 ns 65 200K ns 33 40 ns 3 18 20 ns 3 Industrial Temperature K4E661612D,K4E641612D CMOS DRAM NOTES 1 . A n i n i t i a l p a u s e o f 2 0 0 u s i s r e q u i r e d a f t e r p o w e r - u p f o l l o w e d b y a n y 8 R A S - o n l y o r C A S - b e f o r e -R A S r e f r e s h c y c l e s b e f o r e proper device operation is achieved. 2 . I n p u t v o l t a g e l e v e l s a r e V i h / V i l . V IH ( m i n ) a n d V I L( m a x ) a r e r e f e r e n c e l e v e l s f o r m e a s u r i n g t i m i n g o f i n p u t s i g n a l s . T r a n s i t i o n t i m e s a r e m e a s u r e d b e t w e e n V IH ( m i n ) a n d V IL ( m a x ) a n d a r e a s s u m e d t o b e 2 n s f o r a l l i n p u t s . 3 . Measured with a load equivalent to 1 TTL load and 100pF. 4 . O p e r a t i o n w i t h i n t h e t R C D ( m a x ) l i m i t i n s u r e s t h a t tR A C ( m a x ) c a n b e m e t . tR C D ( m a x ) i s s p e c i f i e d a s a r e f e r e n c e p o i n t o n l y . I f t R C D i s g r e a t e r t h a n t h e s p e c i f i e d t R C D ( m a x ) l i m i t , t h e n a c c e s s t i m e i s c o n t r o l l e d e x c l u s i v e l y b y tC A C . 5 . A s s u m e s t h a t t R C D≥ t R C D( m a x ) . 6 . T h i s p a r a m e t e r d e f i n e s t h e t i m e a t w h i c h t h e o u t p u t a c h i e v e s t h e o p e n c i r c u i t c o n d i t i o n a n d i s n o t r e f e r e n c e d t o V o h o r V o l. 7 . t W C S, t R W D , t C W D a n d t A W D a r e n o n r e s t r i c t i v e o p e r a t i n g p a r a m e t e r s . T h e y a r e i n c l u d e d i n t h e d a t a s h e e t a s e l e c t r i c c h a r a c t e r i s t i c s o n l y . I f tW C S ≥ tW C S ( m i n ) , t h e c y c l e s i s a n e a r l y w r i t e c y c l e a n d t h e d a t a o u t p u t w i l l r e m a i n h i g h i m p e d a n c e f o r t h e d u r a t i o n o f t h e c y c l e . I f tC W D ≥ t C W D ( m i n ) , t R W D ≥ t R W D ( m i n ) a n d t A W D ≥ t A W D ( m i n ) , t h e n t h e c y c l e i s a r e a d - m o d i f y - w r i t e c y c l e and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8 . E i t h e r tR C H o r t R R H m u s t b e s a t i s f i e d f o r a r e a d c y c l e . 9 . This parameters are referenced to the C A S leading edge in early write cycles and to the W falling edge in O E controlled write cycle and read-modify-write cycles. 1 0 . O p e r a t i o n w i t h i n t h e t R A D ( m a x ) l i m i t i n s u r e s t h a t tR A C ( m a x ) c a n b e m e t . tR A D ( m a x ) i s s p e c i f i e d a s a r e f e r e n c e p o i n t o n l y . I f t R A D i s g r e a t e r t h a n t h e s p e c i f i e d t R A D ( m a x ) l i m i t , t h e n a c c e s s t i m e i s c o n t r o l l e d b y t A A. 1 1 . These specifiecations are applied in the test mode. 1 2 . I n t e s t m o d e r e a d c y c l e , t h e v a l u e o f t R A C , tA A , tC A C i s d e l a y e d b y 2 n s t o 5 n s f o r t h e s p e c i f i e d v a l u e s . T h e s e p a r a m e t e r s should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 1 3 . t ASC, t CAH a r e r e f e r e n c e d t o t h e e a r l i e r C A S f a l l i n g e d g e . 1 4 . t CP i s s p e c i f i e d f r o m t h e l a s t C A S r i s i n g e d g e i n t h e p r e v i o u s c y c l e t o t h e f i r s t C A S f a l l i n g e d g e i n t h e n e x t c y c l e . 1 5 . tCWD is referenced to the later C A S falling edge at word read-modify-write cycle. K4E64(6)1612D Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - Industrial Temperature K4E661612D,K4E641612D CMOS DRAM 1 6 . tC W L i s s p e c i f i e d f r o m W f a l l i n g e d g e t o t h e e a r l i e r C A S r i s i n g e d g e . 1 7 . tC S R i s r e f e r e n c e d t o e a r l i e r C A S f a l l i n g b e f o r e R A S t r a n s i t i o n l o w . 1 8 . tC H R i s r e f e r e n c e d t o t h e l a t e r C A S r i s i n g h i g h a f t e r R A S t r a n s i t i o n l o w . RAS LCAS UCAS t CSR tCHR 1 9 . tD S i s s p e c i f i e d f o r t h e e a r l i e r C A S f a l l i n g e d g e a n d tD H i s s p e c i f i e d b y t h e l a t e r C A S f a l l i n g e d g e i n e a r l y w r i t e c y c l e . LCAS UCAS tD S DQ0 ~ DQ15 tD H Din 2 0 . If R A S g o e s h i g h b e f o r e C A S high going, the open circuit condition of the output is achieved by C A S high going. 2 1 . t A S C ≥ 6 n s , A s s u m e t T = 2 . 0 n s , i f t ASC ≤ 6 n s , t h e n t H P C ( m i n ) a n d t C A S ( m i n ) m u s t b e i n c r e a s e d b y t h e v a l u e o f " 6 n s - t A S C " . 2 2 . I f t R A S S ≥ 1 0 0 u s , t h e n R A S p r e c h a r g e t i m e m u s t u s e t R P S i n s t e a d o f t R P. 2 3 . F o r R A S - o n l y - R e f r e s h a n d B u r s t C A S - b e f o r e -R A S r e f r e s h m o d e , 4 0 9 6 c y c l e s ( 4 K / 8 K ) o f b u r s t r e f r e s h m u s t b e e x e c u t e d w i t h i n 64ms before and after self refresh, in order to meet refresh specification. 2 4 . For distributed C A S-before-R A S with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. Industrial Temperature K4E661612D,K4E641612D CMOS DRAM WORD READ CYCLE t RC tR A S tR P V IH RAS V IL - tC S H tC R P tRCD tC R P t RSH V IH - tC A S UCAS V IL - tC S H tC R P tR C D tC R P tR S H tC A S V IH LCAS V IL - tR A D tASR V IH A V IL - tR A H tASC ROW ADDRESS t RAL tC A H COLUMN ADDRESS tR C H tR C S tR R H V IH W V IL - t AA tO L Z V IH - tOEA OE V IL - tC A C t CLZ DQ0 ~ DQ7 tCEZ tO E Z t RAC VOH - OPEN DATA-OUT VOL - tC A C tC L Z DQ8 ~ DQ15 t RAC tCEZ tO E Z VOH - OPEN DATA-OUT VOL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM LOWER BYTE READ CYCLE N O T E : D IN = O P E N tRC tRAS t RP V IH RAS V IL - tR P C tC R P V IH UCAS V IL - t CSH tC R P tR C D tR S H V IH - tC A S LCAS V IL - tR A D tASR V IH A V IL - t RAH t ASC ROW ADDRESS tR A L tC A H COLUMN ADDRESS tRCH tRCS tR R H V IH W V IL - tC E Z tAA tO E Z V IH - tOEA OE V IL - tCAC t CLZ DQ0 ~ DQ7 t RAC V OH DATA-OUT OPEN V OL - tO L Z DQ8 ~ DQ15 V OH - OPEN V OL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM UPPER BYTE READ CYCLE N O T E : D IN = O P E N tR C tR A S tR P V IH RAS V IL - tC S H tCRP tRCD tCRP tR S H V IH - tCAS UCAS V IL - tCRP tR P C V IH LCAS V IL - tRAD t RAL t ASR V IH A V IL - tR A H tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRCS tR R H V IH W V IL - tCEZ tA A tOEZ V IH - tOEA OE V IL - tO L Z DQ0 ~ DQ7 V OH - OPEN VOL - t CAC tC L Z DQ8 ~ DQ15 tR A C V OH - OPEN DATA-OUT V OL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM WORD WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tRC tRAS tR P V IH RAS V IL - tC S H tCRP tR C D tR S H V IH - tC R P tC A S UCAS V IL - tC S H tCRP tRCD tR S H V IH - tC R P tC A S LCAS V IL - tR A D tASR t RAH tR A L tA S C tC A H V IH A V IL - ROW ADDRESS COLUMN ADDRESS tW C S tWCH V IH - tW P W V IL - V IH OE V IL - tD S DQ0 ~ DQ7 t DH V IH DATA-IN V IL - tD S t DH DQ8 ~ DQ15 V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM LOWER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tR C t RAS t RP V IH RAS V IL - tCRP V IH UCAS V IL - tC S H tCRP tR C D tRSH V IH - tC R P tC A S LCAS V IL - t RAD tA S R V IH A V IL - tRAH tR A L t ASC ROW ADDRESS tC A H COLUMN ADDRESS tWCS tWCH V IH - tWP W V IL - V IH OE V IL - tD S DQ0 ~ DQ7 tD H V IH DATA-IN V IL - DQ8 ~ DQ15 V IH V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM UPPER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tR C tR A S tR P V IH RAS V IL - tC S H tC R P tRCD tRSH V IH - tCRP tCAS UCAS V IL - tC R P V IH LCAS V IL - t RAD tA S R V IH A V IL - tR A H t RAL tA S C ROW ADDRESS tC A H COLUMN ADDRESS tWCS tW C H V IH - tW P W V IL - V IH OE V IL - DQ0 ~ DQ7 V IH V IL - t DS tD H DQ8 ~ DQ15 V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM WORD WRITE CYCLE ( O E CONTROLLED WRITE ) N O T E : D OUT = O P E N tRC tRAS t RP V IH RAS V IL - t CSH tC R P tR C D tR S H V IH - tC R P tC A S UCAS V IL - tC S H tC R P tRCD tR S H tC R P t CAS V IH LCAS V IL - t RAD tASR V IH A V IL - t RAH tR A L tASC ROW ADDRESS t CAH COLUMN ADDRESS tCWL tR W L V IH - tW P W V IL - V IH OE V IL - DQ0 ~ DQ7 tOEH tO E D t DS tDH V IH DATA-IN V IL - t DS DQ8 ~ DQ15 tDH V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM LOWER BYTE WRITE CYCLE ( O E CONTROLLED WRITE ) N O T E : D OUT = O P E N t RC tR A S tR P V IH RAS V IL - tR P C tCRP V IH UCAS V IL - tCSH tCRP tRCD tR S H V IH - tC R P tCAS LCAS V IL - tRAD t ASR V IH A V IL - tR A H t RAL tASC ROW ADDRESS t CAH COLUMN ADDRESS tC W L tRWL tW P V IH W V IL - V IH OE V IL - DQ0 ~ DQ7 tOEH tOED tD S tD H V IH DATA-IN V IL - DQ8 ~ DQ15 V IH V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) N O T E : D OUT = O P E N tR C tR A S tR P V IH RAS V IL - tC S H tC R P tR C D tCRP tR S H V IH - tC A S UCAS V IL - tC R P tCRP V IH LCAS V IL - tR A D tASR V IH A V IL - t RAH tR A L t ASC ROW ADDRESS t CAH COLUMN ADDRESS tCWL tR W L V IH W tW P V IL - V IH OE V IL - t OEH tO E D DQ0 ~ DQ7 V IH V IL - DQ8 ~ DQ15 t DS tD H V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM WORD READ - MODIFY - WRITE CYCLE tRWC tRAS t RP V IH RAS V IL - tCRP tR C D tRSH V IH - tCAS UCAS V IL - tCRP tR C D tRSH V IH - tCAS LCAS V IL - t RAD tCSH tA S R V IH A V IL - tR A H ROW ADDR. tA S C t CAH COLUMN ADDRESS tA W D tR W L tC W D tCWL V IH - tW P W V IL - tRWD tO E A V IH OE V IL - t OLZ t CLZ tC A C t AA DQ0 ~ DQ7 tO E D tRAC tOEZ V I/OH - VALID DATA-OUT V I/OL - tD S tD H VALID DATA-IN t OLZ t CLZ t CAC tA A DQ8 ~ DQ15 V I/OH V I/OL - tO E D tR A C tOEZ VALID DATA-OUT tD S tD H VALID DATA-IN D o n ′t c a r e Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM LOWER-BYTE READ - MODIFY - WRITE CYCLE t RWC t RAS RAS t RP V IH V IL - tRPC t CRP UCAS VIH VIL - t CRP LCAS t RCD t RSH V IH - t CAS V IL - tRAD tCSH tASR A V IH V IL - tRAH ROW ADDR. tASC t CAH COLUMN ADDRESS tA W D tR W L t CWD W OE tC W L V IH - tW P V IL - t RWD t OEA VIH VIL - t OLZ tCLZ t CAC t AA DQ0 ~ DQ7 V I/OH V I/OL DQ8 ~ DQ15 V OH V OL - tRAC t OED tOEZ VALID DATA-OUT tD S t DH VALID DATA-IN OPEN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM UPPER-BYTE READ - MODIFY - WRITE CYCLE tR W C tRAS RAS V IL - tCRP UCAS tRP V IH - t RCD t RSH V IH - tCAS V IL - t RPC tCRP LCAS V IH V IL - t RAD tCSH tASR A V IH V IL - t RAH ROW ADDR t ASC tCAH COLUMN ADDRESS tA W D tRWL tCWD W OE tC W L V IH - tW P V IL - tR W D t OEA VIH VIL - DQ0 ~ DQ7 VOH - OPEN VOL - tOLZ t CLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tO E Z VALID DATA-OUT tD S tDH VALID DATA-IN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE WORD READ CYCLE t RASP RAS tRP V IH V IL - tCSH tCRP UCAS t RCD tC P t HPC tC P tCAS t CP tCAS tCAS VIL - tREZ tC P tR C D V IL - V IH V IL - t RAD tRAH tASC ROW ADDR tCP tCAS V IH - tASR A tHPC tCAS VIH - tCRP LCAS tRHCP tHPC tCAS t CAH t ASC COLUMN ADDRESS t CAH t CP tCAS tASC COLUMN ADDRESS tCAH COLUMN ADDR tCAS t ASC tCAH COLUMN ADDRESS tRAL tR C S W V IH V IL - t AA t AA tCPA t OCH t OEA VIH - tCHO tOEP tOEA VIL - tCAC DQ0 ~ DQ7 V OH - t CPA t CAC tAA tCAC t CPA t CAC OE tRRH t RCH tOEP tD O H t RAC VALID DATA-OUT V OL - tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ tCAC DQ8 ~ DQ15 VOH - t OEP tD O H t RAC VOL - tOEZ tOEZ VALID VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE LOWER BYTE READ CYCLE tRP t RASP RAS V IH V IL - ¡ó t RPC tC R P UCAS VIH - tCSH VIL - t RHCP tHPC tCP tR C D LCAS tCP t CAS V IH - t CAS t HPC t REZ tC P t CAS t CAS tCAH t ASC t CAH V IL - tASR A tHPC V IH V IL - t RAD tRAH t ASC ROW ADDR t CAH COLUMN ADDRESS t ASC t CAH t ASC COLUMN ADDRESS COLUMN ADDR COLUMN ADDRESS tR A L t RCS W V IH V IL - tAA t CPA t AA OE tRRH tRCH t AA tCPA tCAC tO C H t OEA VIH - tCAC t RAC VOL - tOEP tD O H VALID DATA-OUT VOL - DQ8 ~ DQ15 VOH - t CHO t OEP t OEA VIL - DQ0 ~ DQ7 VOH - t CPA t CAC tAA tCAC tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ OPEN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE UPPER BYTE READ CYCLE t RASP RAS tRP V IH V IL - ¡ó tCSH t CRP UCAS t RHCP tHPC tR C D tC P tC A S VIH - tHPC t HPC tC P t CAS t CP tRPC tCAS tCAS VIL - tCRP LCAS V IL - tASR A t RPC V IH - V IH V IL - t RAD tRAH t ASC ROW ADDR. t CAH t ASC COLUMN ADDRESS tCAH tASC COLUMN ADDRESS t CAH COLUMN ADDR. t ASC t CAH t REZ COLUMN ADDRESS t RAL tR C S W V IH - t CPA t CAC t AA V IL - tCAC t AA tCPA tAA tCPA tCAC tOCH OE tRRH tRCH t OEA VIH - tOEA VIL - DQ0 ~ DQ7 V OH - OPEN V OL - tCAC DQ8 ~ DQ15 VOH - t CHO t OEP t RAC t OEP tD O H VALID DATA-OUT VOL - tO E Z tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ t CLZ Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tR A S P RAS tR H C P VIL - ¡ó t HPC tCRP UCAS tHPC tCP tR C D V IH - tRSH tCP tCAS tC R P t CAS V IL - tCAS ¡ó t HPC tCRP LCAS tR P VIH - t HPC tCP tR C D VIH - t RSH tCP tCAS t CAS VIL - tCAS ¡ó tRAD tR A L tCSH t ASR A VIH VIL - t RAH tASC tCAH OE tCAH t ASC tCAH ¡ó ROW ADDR COLUMN ADDRESS tW C S W t ASC tWCH COLUMN ADDRESS ¡ó tW C S tW P VIH - tWCH t WP COLUMN ADDRESS t WCS ¡ó tWCH tWP VIL - V IH - ¡ó V IL - ¡ó DQ0 ~ DQ7 V IH - t DS V IL - tD S tDH tDS tDH ¡ó VALID DATA-IN V IL - DQ8 ~ DQ15 V IH - tD H VALID DATA-IN VALID DATA-IN ¡ó t DS tD H tD S tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN t RASP RAS tRP V IH - t RHCP V IL - ¡ó tRPC tCRP UCAS VIH VIL - tHPC tC R P LCAS tR C D tHPC tCP V IH - tRSH tC P tCAS tCAS V IL - t CAS ¡ó t RAD tR A L t CSH t ASR A V IH V IL - tRAH ROW ADDR t ASC tCAH COLUMN ADDRESS OE t ASC t CAH COLUMN ADDRESS tWCH tWCS t WP V IH - tW C H COLUMN ADDRESS tW C S ¡ó tWP t CAH ¡ó ¡ó t WCS W tASC t WCH tW P V IL - VIH - ¡ó VIL - ¡ó DQ0 ~ DQ7 V IH V IL - tDS t DH tD S tD H tD S tD H ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó DQ8 ~ DQ15 VIH VIL - Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN t RASP RAS t RHCP V IL - ¡ó tHPC tCRP UCAS tR P V IH - t RCD tHPC t CP VIH - t RSH t CP tC A S tCAS VIL - t CAS ¡ó tRPC tCRP LCAS V IH V IL - t RAD tRAL tCSH t ASR A V IH V IL - tRAH ROW ADDR t ASC t CAH COLUMN ADDRESS V IH - t CAH COLUMN ADDRESS tASC t WCH t WCS t WP tWCH tW C S tWCH tW P V IL - VIH - ¡ó VIL - ¡ó DQ0 ~ DQ7 VIH - ¡ó OE COLUMN ADDRESS ¡ó tWP t CAH ¡ó ¡ó tW C S W t ASC VIL - DQ8 ~ DQ15 V IH V IL - ¡ó tD S t DH tD S tD H t DS tD H ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tCRP UCAS tRSH tR C D t CRP t CP V IH - tCAS t CAS V IL - tCRP LCAS tH P R W C VIL - tR C D t CRP tCP VIH - tCAS t CAS VIL - t RAD t RAH t ASR A VIH VIL - t RAL tCAH tASC tASC ROW ADDR COL. ADDR COL. ADDR t RCS W tCAH tCWL VIH - t WP VIL - tW P tCWD t CWD t AWD tRWD OE tR W L tC W L tRCS V IH - t AWD tC P W D t OEA tOEA V IL - t OED tOED tCAC t AA DQ0 ~ DQ7 V I/OH V I/OL - t DH t CAC t AA t DS tO E Z tDH t RAC tCLZ t CLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT tOED tCAC tAA DQ8 ~ DQ15 V I/OH V I/OL - tDS tO E Z tD H tOEZ t OED t CAC t AA tD S VALID DATA-IN t DH tOEZ t DS t RAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE tR P t RASP RAS V IH - t CSH tHPRWC V IL - tRPC tC R P UCAS V IH V IL - tC R P LCAS tRCD tRSH tCP VIH - t CAS tCAS VIL - t RAD t RAH tASR A V IH V IL - ROW ADDR t CAH tASC t CAH t ASC COL. ADDR tRWL tCWL t RCS t CWL VIH - t WP VIL - tW P tC W D tCWD tA W D tRWD OE tRAL COL. ADDR tRCS W tCRP V IH - tAWD tCPWD tOEA tOEA V IL - tOED t CAC tAA DQ0 ~ DQ7 V I/OH V I/OL - tOEZ tRAC V I/OL - tD H t DH tAA t DS tD S t CLZ tOEZ tCLZ tOLZ DQ8 ~ DQ15 V I/OH - tOED t CAC VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN OPEN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - t CRP UCAS tH P R W C tRCD t RSH t CP V IH - t CAS tC R P tCAS V IL - t RPC t CRP LCAS VIH VIL - tRAD t RAH tASR A VIH VIL - ROW ADDR tCAH t ASC COL. ADDR tR W L tC W L t RCS tCWL VIH - tWP VIL - tW P t CWD t CWD tA W D tAWD tR W D OE t RAL COL. ADDR t RCS W tCAH tASC V IH - t CPWD tOEA tOEA V IL - DQ0 ~ DQ7 V I/OH - OPEN V I/OL - tOLZ t OLZ t OED t AA DQ8 ~ DQ15 VI/OH VI/OL - t RAC tOED t CAC tCAC tO E Z tD H tD S t CLZ t DH tAA tDS tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HYPER PAGE READ AND WRITE MIXED CYCLE t RP t RASP RAS V IH - READ( tCAC ) R E A D (t CPA) R E A D (tAA ) WRITE V IL - tHPC tR H C P t HPC t HPC tC P tCP tCP V IH UCAS tC A S tR C D V IL - tCAS t HPC t HPC tCP tCP LCAS VIH VIL - tASR A V IH V IL - tC A S tRAD t RAH t ASC ROW ADDR tCAH COLUMN ADDRESS tC P t CAH t ASC COLUMN ADDRESS t CAH COL. ADDR t HPC tCAS tCAS tCAS tASC tCAS tCAS t ASC tCAH COL. ADDR tRAL tR C S W tR C H tR C S t RCH V IH - tWCH tR C H tW C S V IL - tWPE t CLZ t CPA OE t WED VIH VIL - DQ0 ~ DQ7 V I/OH - t OEA tCAC t AA VI/OL - tW E Z tD H tDS tAA tREZ tRAC VALID DATA-OUT V I/OL - DQ8 ~ DQ15 VI/OH - t WEZ tOEA tCAC t AA t WEZ VALID DATA-OUT tWEZ VALID DATA-IN tD H t DS VALID DATA-OUT t AA t REZ tRAC VALID DATA-OUT VALID DATA-OUT VALID DATA-IN VALID DATA-OUT Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tR C V IH - RAS t RP t RAS V IL - tRPC t CRP V IH - UCAS V IL - t CRP V IH - LCAS V IL - t ASR V IH - A V IL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRP t RAS VIH VIL - t RPC tRPC t CP UCAS t CSR VIH - tCHR VIL - t CP LCAS t CSR VIH - tCHR VIL - DQ0 ~ DQ7 VO H - tCEZ OPEN V OL DQ8 ~ DQ15 VOH VOL - W OPEN tW R P tWRH VIH VIL Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) t RC RAS tR A S VIH - t RCD t RSH tCHR tRCD tRSH tCHR V IH V IL - t CRP LCAS tRP tRAS VIL - t CRP UCAS tR C tRP VIH VIL - tRAD tASR A VIH VIL - tRAH t ASC t CAH ROW ADDRESS COLUMN ADDRESS tWRH tRCS W VIH VIL - tRAL tAA OE V IH - t OEA V IL - t CEZ t REZ tCAC t CLZ DQ0 ~ DQ7 VO H V OL - DQ8 ~ DQ15 V OH V OL - t RAC tW E Z t OLZ tOEZ OPEN DATA-OUT OPEN DATA-IN DATA-OUT Don′t care Undefined * In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. Industrial Temperature K4E661612D,K4E641612D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS V IH - tRSH t CHR t RCD tRSH t CHR VIL - V IH V IL - tRAD t ASR A tRCD VIH - tCRP LCAS tR P tRAS V IL - tCRP UCAS tR C tR P V IH V IL - t RAH tASC ROW ADDRESS t CAH COLUMN ADDRESS t WRH tWRP t WCS W OE V IH - tW C H tW P V IL - VIH VIL - tD S DQ0 ~ DQ7 VIH - tD H DATA-IN VIL - tD S DQ8 ~ DQ15 V IH V IL - tD H DATA-IN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP t RASS tRPS VIH - RAS VIL - tRPC t RPC tC P VIH - UCAS t CSR tCHS t CSR tCHS VIL - tCP LCAS VIH VIL - DQ0 ~ DQ7 VO H - tCEZ OPEN V OL DQ8 ~ DQ15 VOH - OPEN VOL - tWRP tWRH VIH - W VIL - TEST MODE IN CYCLE NOTE : OE , A = Don′t care tR C tRP VIH - RAS tR P t RAS VIL - tRPC t RPC tCP t CSR VIH - UCAS tCP LCAS W tC H R VIL - t CSR VIH - tC H R VIL - VIL - t WTS tWTH VIH - DQ0 ~ DQ15 VOH VOL - t CEZ OPEN Don′t care Undefined Industrial Temperature K4E661612D,K4E641612D CMOS DRAM PACKAGE DIMENSION 50 TSOP(II) 400mil 0.400 (10.16) 0.455 (11.56) 0.471 (11.96) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.034 (0.875) 0.0315 (0.80) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O