ASDL-7021 IrDA FIR/VFIR Controller in TFBGA Package Data Sheet Description Features The ASDL-7021 is a new generation large scale integration (LSI) IrDA controller supporting speeds of SIR (up to 115Kbps), MIR(1.152Mbps), FIR(4Mbps) and VFIR (16Mbps). It consists of IrDA Control Block, Remote Control Block, Timer Control Block, Global Control block including Buffer Memory and Direct Memory Access Control Block (DMA) integrated into one single chip. General Features • Interfaces with IrDA Compliant IR Transceiver up to VFIR • Miniature 48 pin TFBGA Package Height : 1.2 mm Width : 4.0 mm Depth : 4.0 mm • 8-bit Memory Mapped Interface • Input clock of 48 MHz • 4 transmission speed in 3 Blocks - SIR Block (2.4 to 115.2Kbps) - FIR Block (1.152Mbps for MIR and 4Mbps for FIR) - VFIR Block (16Mbps) • Operating temperature from -40° C ~ 85°C - Critical parameters are guaranteed over temperature and supply voltage • Core Power Supply = 1.8V Clock Power Supply = 3.3V IO Power Supply =1.8V, 2.5V, 3.3V • RAM Block with On-Chip buffer memory of 8KByte x 2 Bank Configuration - 1 bank for external access x 8 bit width - 1 bank for internal access x 8 bit width through on-chip DMA block - These 2 banks can be switched - Each transmit and receive have their own buffer memory of 8KByte x 2 It has all the hardware including Buffer Memory and Direct Memory Access (DMA) that enables convenient access to its peripheral IO and memories from system bus which is similar to simple memory devices. ASDL-7021 is a class of its own as unlike conventional LSI which utilizes external DMA for implementing fast infrared transfer, complicated bus timing and required additional logic for its interface. ASDL-7021 utilizes two memory banks for external access and internal DMA access; these 2 banks are interchangeable to prevent bus contention. These two banks can be switched using memory select function of the internal register and separates internal bus from external, which enables parallel operation of external microcontroller operation and internal IrDA data transfer operation. ASDL-7021 has embedded Universal Remote Control (RC) function for general purpose remote control communication. Together with Lite-On FIR transceiver and IrSimple software, ASDL-7021 is designed to provide Industry a total solution for high speed wireless connectivity solution in miniature packaging. BANK0 Applications • Mobile Data Communication and Universal Remote Control - Mobile Phones - PDAs - Digital Still Camera - Printer - Notebooks - Handy Terminal - Dongles - Industrial and Medical Instrument FIR block CPU BANK1 DMA DMA FIR block CPU BANK1 Features (Cont.) • Remote Control Block Generate Remote Control burst signal • Timer Block - 2 channels of generic 16 bit timer - 1 channel of Mediabusy timer • Moisture Level 3 • Lead-Free and ROHS Compliant • Infrared Interface Block - IrDA send/receive functions (IRTX0, IRRX0) - Remote Control send function (IRTX1) • DMA Block - DMA transfer function between buffer memory and SIR, FIR, VFIR block /SD /RESET IrRXD0 C6 A6 D1,D2,E2,E1,G1,G2,F1,F2 B6 G3,F3,F4,G4,G5,F7,G6,G7 C7 B7 F6 A7 E5 ASDL-7021 E6 A3 D7 A2 B2 E7 C1 D5 E3 GND Figure 1b. Pin layout of ASDL-7021 (Top View) D3 GND GND Figure 1a. Pin Layout of ASDL-7021 C3 GND B3 GND A1 C5 VDDK /IRQ C4 VDDK /OE C2 VDDK /WE F5 VDDC Host I/F E4 V IO1 /CS D6 VIO1 D[7:0] B1 V IO2 V IO3 A[7:0] IrTX0 (IrDA) IrTX1 (Remote) IrOUT0 (IrMode) IrDA Transceiver I/F Ir0UT1 (SD) /XTALIN /XTALOUT CLKIN CLKSEL INTERNAL CLOCK EXTERNAL CLOCK Application Support Information The Application Engineering Group is available to assist you with the application design associated with ASDL-7021 FIR/VFIR Controller. You can contact them through your local sales representatives for additional details. Order Information Part Number Packaging Type Quantity ASDL-7021 Tape and Reel 4000 I/O Pins Configuration Table Pins Description Symbol Buffer Type (Refer to Figure 2) Pin(s) Type Description VDDK C4,C5,C6 POWER 1.8V Power VDDC C2 POWER 3.3V Power VIO1 E4,F5 POWER 1.8V, 2.5V, 3.3V VIO2 D6 POWER 1.8V, 2.5V, 3.3V VIO3 B1 POWER 1.8V, 2.5V, 3.3V GND A1,B3,C3,D3,E3 POWER GND Power Bus Interface Signals (VIO1 Voltage) A0-A7 D1,D2,E2,E1, G1,G2,F1,F2 I I An 8-bit address signal line connects itself directly with an external address bus. It selects the internal buffer memory and the register addresses of each function module. With the assertion of the CS signal, A0 - A7 turn out to be valid, which decides the internal addresses. D0-D7 G3,F3,F4,G4 G5,F7,G6,G7 I/O IO4 An 8-bit data signal line connects itself directly with an external data bus. It is a signal that performs data conversion with the internal buffer memory and each function module.The bus direction is determined by WE and OE. /CS F6 I I CS is a chip select signal for the IC. Asserting CS activates the external bus of this LSI. /WE E5 I I The WE signal turns the direction of a data bus to the input direction, and takes it into the IC for the internal buffer memory and registers designated by the address bus, at the start-up of the signal. /OE E6 I I The OE signal turns the data bus direction to the output direction, and outputs to the data bus the contents of the internal buffer memory and register designated by the address bus. /IRQ D7 O O4 This is a signal line that notifies to the outside that ASDL-7021 requests an interrupt. Other Signals (VIO1 Voltage) /RESET D5 I I This RESET signal resets ASDL-7021. /SD E7 I I (internal PullDown) 1. Low: Shutdown IC is suspending the clock supply to the core. The output signal retains the condition. 2. High: IC is keeping the clock supply to the core. However, when the externally connected quartz crystal is used with CLKSEL=Low, the oscillation of the quartz crystal is kept performed under the condition of CLKSEL=Low, and SD: Low. When you want to stop the quartz crystal oscillation, you must set CLKSEL=High. 3. After wake up from SD, the IC must be reset. CLKSEL C1 I I This is used for selecting whether the input signal from CLKIN should be used for the clock input or whether the quartz crystal should be used at XTALIN and XTALOUT. Using quartz crystal, CLKSEL = Low, external quartz crystal is kept under oscillation CLKSEL = High, external quartz crystal is suspending oscillation Using CLKIN signal, set CLKSEL = High Infrared Interface Signal (VIO2 voltage) IrTXD0 B6 O O4 This outputs the IrDA infrared signal and remote control send signal. IrTXD1 C7 O O4 This outputs the IrDA infrared signal and remote control send signal. IrRXD0 A6 I I This inputs a signal from the infrared module. IrOUT0 B7 O O4 This is an output signal for controlling the infrared module. IrOUT1 A7 O O4 This is an output signal for controlling the infrared module. Clock Signal (VIO3 voltage) CLKIN B2 I I Clock input Clock Signal (VDDC Voltage) /XTALIN A3 I You must connect quartz crystal to create a basic clock or input the clock from outside. Usually you must connect the quartz crystal between XTALIN and XTALOUT. The oscillation frequency of the crystal must be 48MHz. /XTALOUT A2 O TEST1 B5 I I (Internal PullDown) Test signal (Set to N.C). TEST2 A5 I I (Internal PullDown) Test signal (Set to N.C). TEST3 A4 I I (Internal PullDown) Test signal (Set to N.C). TESTSE B4 I I (Internal PullDown) Test signal (Set to N.C). TEST Signal Output BufferType I VIO O4: I(schmitt) I(pulldown) VIO VIO IOL=4mA,IOH=4mA(VIO = 3.3V) IOL=2.2mA,IOH=2.2mA(VIO = 2.5V) IOL=1.4mA,IOH=1.4mA(VIO = 1.8V) O4 VIO IO4 Figure 2. I/O Description Block Diagram Figure 3. Block Diagram of internal blocks of ASDL-7021 VIO Registers Descriptions Block Name IrDA Base Address 0x0000 Offset 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h Register Name IRBA0R(IR Base Address0 Register) IRBA1R(IR Base Address1 Register) IRBA2R(IR Base Address2 Register) IRRSR(IR Ring Size Register) IRPLC0R(IR Physical Layer Config0 Register) (unused) IRPLC1R(IR Physical Layer Config1 Register) (unused) IRPLC2R(IR Physical Layer Config2 Register) IRPLC3R(IR Physical Layer Config3 Register) IRC0R(IR Config0 Register) IRC1R (IR Config1 Register) IRC2R (IR Config2 Register) IRC3R (IR Config3 Register)(unused) IRE0R(IR Enable0 REG.) IRE1R (IR Enable1REG.) IRMPL0R(IR Max Packet Length0 REG.) IRMPL1R (IR Max Packet Length1REG.) IRRP0R(IR Ring Prompt0 REG.) IRRP1R (IR Ring Prompt Register1 REG.) (unused) IRRP2R (IR Ring Prompt Register2 REG.) (unused) IRRP3R (IR Ring Prompt Register3 REG.) (unused) IRRBC0R(IR Receive Byte Count0 REG.) IRRBC1R (IR Receive Byte Count1 REG.) IRRRPR0R(IR Rx Ring Pointer Readback REG.) IRTRPR0R (IR Tx Ring Pointer Readback REG.) IRSF0R(IR SIR Flags0 REG.) IRSF1R (IR SIR Flags1 REG.) IRLPC0R(IR Latched Phy Config0 REG.) IRLPC1R (IR Latched Phy Config 1REG.) IRAC0R(IR Address Compare0 REG.) IRAC1R (IR Address Compare1 REG.) IRAC2R (IR Address Compare2 REG.) IRAC3R (IR Address Compare3 REG.) IRLT0R(IR Latency Timer0 REG.) IRLT1R (IR Latency Timer1 REG.) IRLT2R (IR Latency Timer2 REG.) IRLT3R (IR Latency Timer3 REG.) IRLIV0R(IR LED Indicator and Rx value0 REG.) IRLIV1R (IR LED Indicator and Rx value1 REG.) (unused) IRLIV2R (IR LED Indicator and Rx value2 REG.) (unused) IRLIV3R (IR LED Indicator and Rx value3 REG.) (unused) IRCS0R(IR Clock Speed0 REG.) IRCS1R (IR Clock Speed1 REG.) IRCS2R (IR Clock Speed2 REG.) (unused) IRCS3R (IR Clock Speed3 REG.) (unused) IRPM0R(IR Power management REG.) IRPM1R (IR Power management REG.) (unused) IRPM2R (IR Power management REG.) (unused) IRPM3R (IR Power management REG.) (unused) IRIS0R(Interrupt status read back0 REG.) IRIS1R (Interrupt status read back1 REG.) (unused) IRIS2R (Interrupt status read back2 REG.) (unused) IRIS3R (Interrupt status read back3 REG.) (unused) IRIE0R (Interrupt enable read back0 REG.) IRIE1R (Interrupt enable read back1 REG.) (unused) IRIE2R (Interrupt enable read back2 REG.) (unused) IRIE3R (Interrupt enable read back3 REG.) (unused) Block Name IrDA Base Address 0x0080 (TXFL FIFO) IrDA 0x0090 (RXFL FIFO) Global Control 0x00A0 DMA Control Remote Control 0x00B0 0x00C0 Timer Control 0x00D0 0x00E0 0x00F0 Offset 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0000h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0000h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0000h 0001h 0002h 0003h 0004h 0005h 0006h Register Name TXFL0R(TX Frame Length0 REG.) TXFL1R(TX Frame Length1 REG.) Unused TXSR(TX Status REG.) TXFA0R(TX Frame Address0 REG.) TXFA1R(TX Frame Address1 REG.) TXFA2R(TX Frame Address2 REG.) TXFA3R(TX Frame Address3 REG.) TXSIR(TX Status IncrementREG.) TXFCR(TX Frame Count REG) RXFL0R(RX Frame Length0 REG.) RXFL1R(RX Frame Length1 REG.) Unused RXSR(RX Status REG.) RXFA0R(RX Frame Address0 REG.) RXFA1R(RX Frame Address1 REG.) RXFA2R(RX Frame Address2 REG.) RXFA3R(RX Frame Address3 REG.) RXSIR(RX Status IncrementREG.) MTDR (Memory Transmit Data REG) Write Only MRDR(Memory Receive Data REG) Read Only MCR(Memory Control REG.) GISR(Global Interrupt Status REG.) IRSR (IR Select REG.) IOR(Ir Output REG) IIR(Ir Input REG) ISIER(Ir Sir Interupt Enable REG) ISISR(Ir Sir Interupt Status REG) DMACR(DMA Control REG) RCCCLR(Remote Control Carrier Count Low REG) RCCCHR(Remote Control Carrier Count High REG) RCLLR(Remote Control Length Low REG.) RCLHR(Remote Control Length High REG.) RCCR(Remote Control Control REG) RCCRCLR(Remote Control Carrier RX Count Low REG) RCCRCHR (Remote Control Carrier RX Count High REG) TSSR0(Timer Source Setting REG.0) TIER0(Timer Interrupt Enable REG.0) TCSR0(Timer Contorol Status REG.0) TCMLR0(Timer Compare Mach Low REG.0) TCMHR0(Timer Compare Mach High REG.0) TCLR0(Timer Count Low REG.0) TCHR0(Timer Count High REG.0) TSSR1(Timer Source Setting REG.1) TIER1(Timer Interrupt Enable REG.1) TCSR1(Timer Contorol Status REG.1) TCMLR1(Timer Compare Mach Low REG.1) TCMHR1(Timer Compare Mach High REG.1) TCLR1(Timer Count Low REG.1) TCHR1(Timer Count High REG.1) TSSR2(Timer Source Setting REG.2) TIER2(Timer Interrupt Enable REG.2) TCSR2(Timer Contorol Status REG.2) TCMLR2(Timer Compare Mach Low REG.2) TCMHR2(Timer Compare Mach High REG.2) TCLR2(Timer Count Low REG.2) TCHR2(Timer Count High REG.2) Absolute Maximum Ratings For implementations where case to ambient thermal resistance is ≤ 50°C/W. Parameter Symbol Min. Max. Units Core Power Supply Voltage VDDK -0.3 VIO+0.3 V Clock Power Supply Voltage VDDC -0.3 3.63 V IO Power Supply Voltage VIO -0.3 3.63 V Input Output Voltage VI/VO -0.3 3.63 V Operating Environnent Temperature TA -40 85 °C Storage Temperature TS -40 150 °C Electrical Specifications (DC) Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range and VIO = 3.3+0.33V VIO= 3.3+/-0.33V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Core Power Supply VDDK 1.62 1.8 1.98 V Clock Power Supply VDDC 2.97 3.3 3.63 V IO Power Supply VIO 2.97 3.3 3.63 V Input Low Voltage VIL 0.8 V LVTTL Input High Voltage VIH V LVTTL Switch Threshold Vt 1.5 V LVTTL Schmitt-Trigger –ve Threshold Voltage Vt- 1.1 V LVTTL Schmitt- Trigger +ve Threshold Voltage Vt+ Input Leakage Current IIN Tri-State Output Leakage Current IOZ Output Low Voltage VOL Output High Voltage VOH 2.4 Input Pull-Down Resistance RPD 40 75 Current (VFIR running state) – VDDK Ioz1k 18.6 Current (IDLE state) – VDDK IOZ2k 18.0 Current (VFIR running state) – VIO1 IOZ1IO1 Current (IDLE state) – VIO1 IOZ2IO1 Current (VFIR running state) – VIO2 IOZ1IO2 Current (IDLE state) – VIO2 IOZ2IO2 Current (IDLE state) – VIO3 IOZ2IO3 Clock Power Supply Current-VDDC IOZ1C 2.0 0.8 Conditions 1.6 2.0 V LVTTL -10 ±1 10 µA VI=VIO or GND -10 ±1 10 µA VI=VIO or GND 0.4 V IOL = 2 ~16mA V IOH = 2 ~16mA 190 kΩ VIN =VIO 20.5 22.5 mA SD:High 20.3 22.0 mA SD:High 940 µA SD:High 30 µA SD:High 52 µA SD:High 1 µA SD:High 38 µA SD:High 5.93 mA Capacitor 20pF 14 0.1 4.01 4.8 VIO= 2.5+/-0.25V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Core Power Supply VDDK 1.62 1.8 1.98 V Clock Power Supply VDDC 2.97 3.3 3.63 V IO Power Supply VIO 2.25 2.5 2.75 V Input Low Voltage VIL 0.25*VIO V CMOS Input High Voltage VIH Switch Threshold Vt Schmitt-Trigger –ve Threshold Voltage Vt- Schmitt- Trigger +ve Threshold Voltage Vt+ Input Leakage Current IIN Tri-State Output Leakage Current IOZ Output Low Voltage VOL Output High Voltage VOH 1.85 Input Pull-Down Resistance RPD 45 0.625*VIO 0.25*VIO Conditions V CMOS 1.15 V CMOS 0.94 V CMOS 1.4 0.625*VIO V CMOS -10 ±1 10 µA VI=VIO or GND -10 ±1 10 µA VI=VIO or GND 0.4 V IOL = 1.1 ~8.8mA V IOH = 1.1 ~8.8mA kΩ VIN =VIO 115 290 VIO= 1.8+/-0.18V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Core Power Supply VDDK 1.62 1.8 1.98 V Clock Power Supply VDDC 2.97 3.3 3.63 V IO Power Supply VIO 1.62 1.8 1.98 V Input Low Voltage VIL 0.3*VIO V CMOS Input High Voltage VIH V CMOS Switch Threshold Vt 0.85 V CMOS Schmitt-Trigger –ve Threshold Voltage Vt- 0.65 V CMOS Schmitt- Trigger +ve Threshold Voltage Vt+ Input Leakage Current IIN Tri-State Output Leakage Current IOZ Output Low Voltage VOL Output High Voltage VOH 0.75*VIO Input Pull-Down Resistance RPD 80 0.7*VIO 0.3*VIO Conditions 1.08 0.7*VIO V CMOS -10 ±1 10 µA VI=VIO or GND -10 ±1 10 µA VI=VIO or GND 0.4 V IOL = 0.7 ~5.6mA V IOH = 0.7 ~5.6mA kΩ VIN =VIO 210 510 Shutdown Currents (Internal Clock is Used) [1] Parameter Min. Typ. Max. Unit Conditions Note Shutdown Current 1 (VDDK) 17.8 18.8 19.7 mA /SD: LOW CLKSEL: LOW CLKIN: LOW External quartz crystal is kept under oscillation External quartz crystal is suspending oscillation Shutdown Current 2 (VDDK) 0.4 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Clock Power Supply Current (VDDC) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO1) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO2) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO3) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Currents (External Clock is Used) [1] Parameter Min. Typ. Max. Unit Conditions Shutdown Current 3 (VDDK) 13.2 21.9 mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Clock Power Supply Current (VDDC) 0.1 mA /SD: LOW CLKSEL: HIGH LKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO1) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO2) 0.1 mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO3) (1) Test Conditions: - /RESET = HIGH (VIO1) - A[7:0] = Must be driven either HIGH (VIO1) or LOW (0V) - D[7:0] = Must be driven either HIGH (VIO1) or LOW (0V) - /CS = HIGH (VIO1) - /WE = HIGH (VIO1) - /OE = HIGH (VIO1) - IrRXD0 = HIGH (VIO2) 10 8.5 Note Clock Standards Standard values of the system clock input Frequency: 48MHz ± 100ppm Input Duty: Must be within 50% ± 5%. Power-up Procedures V VDDC,VIO(=1.8 to 3.3V) VDDK(=1.8V) t Recommended Power-Up Procedure Turn on the core power supply VDDK before you turn on the VDDC and VIO power supply and shut it down later V VDDC,VIO(=1.8 to 3.3V) V VDDK(=1.8V) Allowable Limit of Power-Up Procedure If you want to turn on the core power supply VDDK after you turn on VDDC and VIO power supply, you must keep V = VIO-VDDK < 0.5V during the time before VDDK becomes stable 11 V t A.C Timing 1) Reset Input Timing t RST /RESET -on Oscillation Item Symbol Reset Pulse Width tRST Min Typ Max 50 2) Stabilization Time of Power-on Oscillation (Internal Clock is Used) Oscillation Stabilization Term Internal clock VCC t RST t SOC1 /RESET /SD Parameter Symbol Typical Value Power-on Oscillation stabilization time tSOC1 20ms Reset Pulse Width tRST 50ns 12 Unit ns Stabilization Time of Power-on Oscillation (External Clock is Used) Oscillation Stabilization Term External clock VCC t RST t SOC1 /RESET /SD Parameter Symbol Typical Value Power-on Oscillation stabilization time tSOC1 50ns Reset Pulse Width tRST 50ns 3) Return Oscillation Stabilization Time via CLKSEL Oscillation stabilization term Internal clock CLKSEL t SOC1 t RST /RESET Item Symbol CLKSEL return oscillation stabilization time TSOC1 Oscillation stabilization time when the quartz crystal is connected 13 Min Typ 20 Max Unit msec 4) Read Operations /CS Valid data A[7:0] t ASR t AHR t RDW /OE t DRD t DHW Valid data D[7:0] t WTH t OET /OE Item Symbol Min Address setting time tASR 0 ns Address retaining time tAHR 0 ns Data delay time tDRD Read pulse amplitude tRDW 80 ns Output retaining time tDHW 0 ns Turnaround time tOET 50 ns 14 Max 80 Unit ns 5) Write Operations /CS Valid data A[7:0] t ASW t WRW /WR t AHW t DSW t DHW Valid data D[7:0] t WET /WE Item Symbol Min Address setting time tASW 0 ns Address retaining time tAHW 0 ns Write pulse amplitude tWRW 50 ns Data setting time tDSW 10 ns Data retaining time tDHW 0 ns Turnaround time tWET 70 ns 15 Max Unit 6) Send Pulse Amplitude Item SIR send pulse amplitude Symbol Conditions Min Typ Max Unit tTSPW 3/16 pulse amplitude 20.7 20.8 20.9 μs 19,200bps 10.3 10.4 10.5 μs 38,400bps 5.16 5.18 5.19 μs 57,600bps 3.43 3.40 3.47 μs 115,200bps 1.70 1.72 1.74 μs 1.665 1.72 1.769 μs 104.0 104.1 104.2 μs 19,200bps 52.0 52.1 52.2 μs 38,400bps 25.2 26.0 26.1 μs 57,600bps 17.2 17.3 17.4 μs 115,200bps 8.5 8.6 8.7 μs 226 227 228 ｎs 868 875 ｎs 125 126 ｎs 9,600bps 1.6μS SIR send cycle 9,600bps pulse amplitude 1.6μs fixed Typ register IRPLC2R,IRPLC3R PW[4:0] = 0x4E 20.8nsec Step changeable tTSRT MIR send pulse amplitude 1.152Mbps tTMPW MIR send cycle 1.152Mbps tTMRT 854 FIR send pulse amplitude 4Mbps tTFPW 124 FIR send cycle 4Mbps tTFRT VFIR send pulse amplitude 16Mbps tTFPW 16 Typ register IRPLC2R,IRPLC3R PW[4:0] = 0x4E 20.8nsec Step changeable 500 41.0 41.7 ｎs 43.0 ｎs ASDL-7021 Package Dimension: 17 18 ASDL-7021 Tape and Reel Dimension: 19 PIN 1 Orientation Cover tape Carrier tape Orientation 20 Moisture Proof Packaging All ASDL-7021 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. UNITS IN A SEALED MOISTURE-PROOF PACKAGE PACKAGE IS OPENED (UNSEALED) PARTS ARE NOT RECOMMENDED TO BE USED NO ENVIRONMENT LESS THAN 30C AND LESS THAN 60%RH YES PACKAGE IS OPENED LESS THAN 168 HOURS YES NO BAKING IS NECESSARY NO NO PACKAGE IS OPENED LESS THAN 15 DAYS YES PERFORM RECOMMENDED BAKING CONDITIONS Figure 4. Baking Conditions Chart Baking Conditions Recommended Storage Conditions Package Temp Time In bulk 125 °C ≥ 24hours Baking should only be done once. 21 Storage Temperature 10°C to 30°C Relative Humidity below 60% RH Time from unsealing to soldering After removal from the bag, the parts should be soldered within 7 days if stored at the recommended storage conditions. If times longer than 7 days are needed, the parts must be stored in a dry box. T - TEMPERATURE (°C) Recommended Reflow Profile MAX 260C 255 R3 230 217 200 180 R2 R4 60 sec to 180 sec Above 217 C 150 R1 120 R5 80 25 0 P1 HEAT UP 50 100 P2 SOLDER PASTE DRY 150 200 P3 SOLDER REFLOW 300 t-TIME (SECONDS) Symbol DT Maximum DT/Dtime or Duration Heat Up P1, R1 25°C to 150°C 3°C/s Solder Paste Dry P2, R2 150°C to 200°C 60s to 180s Solder Reflow P3, R3 P3, R4 200°C to 255°C 255°C to 200°C 3°C/s -6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s > 217°C 60s to 150s Process Zone Time maintained above 217°C Peak Temperature 260°C Time within 5°C of actual Peak Temperature Time 25°C to Peak Temperature > 255°C 20s to 40s 25°C to 260°C 8mins The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates or duration. The DT/Dtime rates or duration are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and ASDL-7021 pins are heated to a temperature of 150°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 3°C per second to allow for even heating of both the PC board and ASDL-7021 pins. Process zone P2 should be of sufficient time duration (100 to 180 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). 22 250 P4 COOL DOWN Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 40 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 40 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and ASDL-7021 pins to change dimensions evenly, putting minimal stresses on the ASDL-7021. Appendix A: General Application Guide for the ASDL-7021 Integrated FIR/VFIR IrDA Controller IrTX0(IrDA) /CS IrTX1(Remote /OE IrRXD0 /WE IrOUT0(IrMode/S CLK) IrOUT1 (SD) IrDA Transceiver (can be STC or non-STC with/without RC) /SD ASDL-7021 FIR/VFIR IrDA Controller /RESET /IRQ Host Microcontroller Address Bus CLKSEL RECOMMENDED FIR HW: ASDL-3023, HSDL-3021, HSDL-3020 and HSDL-3220 CLKIN Data Bus Figure A1. Block Diagram of ASDL-7021 interface with Recommended Transceiver and Host Microcontroller For company and product information, please go to our web site: WWW.liteon.com or http://optodatabook.liteon.com/databook/databook.aspx Data subject to change. Copyright © 2007 Lite-On Technology Corporation. All rights reserved.