PJSMF03LC Series 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V, as well available for 12V, 15V, and 24V Systems. This TVS array offers an integrated solution to protect up to 5 data lines where the board space is a premium. SPECIFICATION FEATURES 100W Power Dissipation (8/20µs Waveform) Low Leakage Current Very Low Clamping Voltage 1 IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Operating voltage options for 3.3V, 5V, 12V, 15V, and 24V Industry Standard SOT363 (SC70-6L) Package 6 5 4 1 2 3 APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories SOT363 Memory Card Port Protection MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8/20µs Waveform) P pp 100 W ESD Voltage (HBM) V ESD 25 kV Operating Temperature Range TJ -55 to +150 °C Storage Temperature Range Tstg -55 to + 150 °C Rating ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJSMF03LC Parameter Reverse Stand-Off Voltage Conditions Symbol Min VWRM Typical Max Units 3.3 V 5.6 V 250 µA Reverse Breakdown Voltage VBR Reverse Leakage Current IR Clamping Voltage (820µs) Vc I pp = 5A 7.5 V Clamping Voltage (8/20µs) Vc I pp = 9A 9 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 160 pF Off State Junction Capacitance Cj 3.3 Vdc Bias f = 1MHz Between I/O pins and pin 2 90 pF 9/14/2005 I BR = 10 mA VR = 3.3V Page 1 4.7 www.panjit.com PJSMF03LC Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJSMF05LC Parameter Reverse Stand-Off Voltage Symbol Conditions Min Typical VWRM Max Units 5 V Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5V 0.5 Clamping Voltage (8/20µs) Vc I pp = 5A 10 Clamping Voltage (8/20µs) Vc I pp = 9A Off State Junction Capacitance Cj Off State Junction Capacitance Cj 6.2 V µA V 11 V 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 100 pF 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 45 pF Max Units 12 V PJSMF12LC Parameter Reverse Stand-Off Voltage Symbol Conditions Typical VWRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 12V Clamping Voltage (8/20µs) Vc Clamping Voltage (8/20µs) Vc Off State Junction Capacitance Min Cj 13.3 V 0.5 µA I pp = 3A 18 V I pp = 5A 20 V 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 50 pF Max Units 15 V PJSMF15LC Parameter Reverse Stand-Off Voltage Symbol Conditions VWRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 15V Clamping Voltage (8/20µs) Vc Clamping Voltage (8/20µs) Vc Off State Junction Capacitance 9/14/2005 Min Cj Typical 16.6 V 0.5 µA I pp = 3A 23 V I pp = 4A 25 V 40 pF 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Page 2 www.panjit.com PJSMF03LC Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJSMF24LC Parameter Reverse Stand-Off Voltage Symbol Conditions Min Typical VWRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 24V Clamping Voltage (8/20µs) Vc Clamping Voltage (8/20µs) Vc Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Symbol Conditions Max Units 24 V 26.7 V 0.5 µA I pp = 1A 35 V I pp = 2A 45 V 30 pF Max Units 36 V PJSMF36LC Parameter Reverse Stand-Off Voltage VWRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 36V Clamping Voltage (8/20µs) Vc Clamping Voltage (8/20µs) Vc Off State Junction Capacitance 9/14/2005 Min Cj Typical 38 V 0.5 µA I pp = 1A 40 V I pp = 2A 50 V 25 pF 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Page 3 www.panjit.com PJSMF03LC Series TYPICAL CHARACTERISTICS 25°C unless otherwise noted Non-Repetitive Peak Pulse Power vs Pulse Time Pulse Waveform Percent of Ipp Peak Pulse Power - Ppp (W) 1000 100 10 1 10 100 1000 110 100 90 80 70 60 50 40 30 20 10 0 50% of Ipp @ 20µs Rise time 10-90% - 8µs 0 5 10 Pulse Duration, µsec 15 20 25 30 time, µsec Capacitance vs. Biasing Voltage @1MHz Typical Leakage Current vs Temperature Clamping Voltage vs Ipp 8x20µsec Surge 100 10 9 8 0.0100 7 6 5 4 0.0010 3 2 1 0 90 0.0001 Capacitance, pF PJSMF05LC Ipp, Amps Current, µA 0.1000 5V 3V 80 70 60 PJSMF05LC 50 40 30 6 7 25 50 8 9 75 100 Clamping Voltage, V 10 125 11 1 2 3 4 5 Bias Voltage, Vdc Temp,°C 9/14/2005 0 150 Page 4 www.panjit.com PJSMF03LC Series LAYOUT DIMENSIONS AND SUGGESTED PAD LAYOUT 9/14/2005 Page 5 www.panjit.com