PJQMF05LC 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION PRELIMINARY This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating at 5Vdc and below. This TVS array offers an integrated solution to protect up to 5 data lines where the board space is a premium. 6 5 4 1 2 3 SPECIFICATION FEATURES 100W Power Dissipation (8x20µsec Waveform) Low Leakage Current, Maximum of 2µA @ 5Vdc Very Low Clamping Voltage, Max of 10V @ 9Apk 8x20µsec 6 IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance 5 4 Max off state Capacitance of 90pF @ 0Vdc 1 MHz New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm Same Footprint compared to the SOT563 1 2 3 APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) 1 Portable Instrumentation Mobile Phones and Accessories 3 2 QFN 2X2 6 Memory Card Port Protection 5 4 QFN 1.6x1.6 sq mm Package MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8x20µsec Waveform) P pp 100 W Peak Pulse Current (8x20µsec Waveform) I pp 10 A V ESD >25 kV Operating Temperature Range TJ -55 to +125 °C Storage Temperature Range Tstg -55 to + 150 °C Rating ESD Voltage (HBM) ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C Parameter Reverse Stand-Off Voltage Conditions Symbol Min VWRM Typical Max Units 5 V 7.2 V Reverse Breakdown Voltage VBR Reverse Leakage Current IR VR = 5V 2.0 µA Clamping Voltage (8x20µsec) Vcl I pp = 5A 9 V Clamping Voltage (8x20µsec) Vcl I pp = 9A 10 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 90 pF Off State Junction Capacitance Cj 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 45 pF 1/26/2004 I BR = 1 mA Page 1 6 www.panjit.com PJQMF05LC TYPICAL CHARACTERISTICS 25°C unless otherwise noted Pulse Waveform Percent of Ipp Peak Pulse Power - Ppp (W) 100 10 1 10 100 1000 110 100 90 80 70 60 50 40 30 20 10 0 50% of Ipp @ 20µs Rise time 10-90% - 8µs 0 5 10 Pulse Duration, µsec 15 20 25 30 time, µsec Capacitance vs. Biasing Voltage @1MHz Clamping Voltage vs Ipp 8x20µsec Surge 100 10 9 8 7 6 5 4 3 2 1 0 90 Capacitance, pF Ipp, Amps PRELIMINARY Non-Repetitive Peak Pulse Power vs Pulse Time 1000 80 70 60 50 40 30 6 7 8 9 10 11 Clamping Voltage, V 1/26/2004 0 1 2 3 4 5 Bias Voltage, Vdc Page 2 www.panjit.com PJQMF05LC TYPICAL APPLICATION EXAMPLE PRELIMINARY 1 I/O Data lines 2 3 4 5 Ground (Pin 2) 1/26/2004 Page 3 www.panjit.com PJQMF05LC PACKAGE DIMENSIONS AND SUGGESTED BOND PAD LAYOUT BOTTOM VIEW TOP VIEW 0.50 ± 0.05 mm 1.60 ± 0.05 mm 0.20 ± 0.05 mm 0.20 ± 0.05 mm 1.1 ± 0.05 mm 1.60 ± 0.05 mm 0.6 ± 0.05 mm SIDE VIEW 0.203 ± 0.05 mm 0.75 ± 0.05 mm PREFERRED ALTERNATE 0.25 ± 0.05 mm 0.25 ± 0.05 mm 0.40 ± 0.05 mm 0.40 ± 0.05 mm 0.90 ± 0.05 mm 0.55 mm 1.0 ± 0.05 mm 1.00 ± 0.05 mm 0.50 ± 0.05 mm 0.50 ± 0.05 mm 1/26/2004 Page 4 www.panjit.com