PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) FEATURES BLOCK DIAGRAM SEL OE VCON Oscillator Amplifier w/ X+ integrated varicaps PLL (Phase Locked Loop) OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 17 26 XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 Die ID: A1313-13A C502A 4 5 6 7 8 GNDBUF 3 GND 2 NC (0,0) 1 GND Y X Name Value Size 62 x 65 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil OUTSEL0 (Pad #25) Q 0 0 High Drive CMOS 0 1 Standard CMOS 1 0 LVDS 1 1 PECL (default) OE_SELECT (Pad #9) OE_CTRL (Pad #30) PLL520-10 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS OE_SEL^ OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) PLL by-pass 16 DIE SPECIFICATIONS Q X- GNDBUF 9 GND PLL520-10 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with an integrated Phase Locked Loop for selectable 1x (no PLL), 2x, 4x or 8x multipliers. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. 25 GND DESCRIPTION XIN (1550,1475) GND • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50uW. Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. GND • • 65 mil 62 mil • • DIE CONFIGURATION 0 1 (Default) 0 Selected Output State Tri-state 1 (Default) Output enabled 0 (Default) Output enabled 1 Tri-state Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0” 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) FREQUENCY SELECTION TABLE Pad #28 SEL3 Pad #29 SEL2 Pad #19 SEL1 Pad #20 SEL0 Selected Multiplier 0 0 1 1 Fin x 8 1 0 1 1 Fin x 4 1 1 1 0 Fin x 2 1 1 1 1 No multiplication (no PLL) All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CONDITIONS CX+ CXC0 65MHz to 130 MHz (VDD=3.3V) γ OF Fund. MIN. TYP. MAX. UNITS 2 2 pF 350 130 MHz 2.6 65 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL VCXO Stabilization Time * CONDITIONS T VCXOSTB MIN. From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V VCON = 0 to 3.3V VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW TYP. MAX. UNITS 10 ms 200* ppm ±100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB ppm pF % ppm/V kΩ kHz 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage I DD CONDITIONS MIN. PECL/LVDS/CMOS V DD 2.97 45 45 45 @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle TYP. Short Circuit Current 50 50 50 ±50 MAX. UNITS 100/80/40 mA 3.63 55 55 55 V % mA 5. Jitter Specifications PARAMETERS CONDITIONS Period jitter RMS Period jitter peak-to-peak Integrated jitter RMS MIN. 77.76MHz 155.52MHz 622.08MHz 77.76MHz 155.52MHz 622.08MHz Integrated 12 kHz to 20 MHz at 77.76MHz Integrated 12 kHz to 20 MHz at 155.52MHz Integrated 12 kHz to 20 MHz at 622.08MHz TYP. MAX. 2.5 4 5 24 29 32 0.5 1.5 1.5 UNITS ps ps ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 77.76MHz 155.52MHz 622.08MHz @10Hz @100Hz @1kHz @10kHz @100kHz UNITS -75 -75 -75 -95 -95 -95 -125 -120 -115 -145 -125 -118 -155 -123 -115 dBc/Hz Note: Phase Noise at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 7. CMOS Output Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD R L = 100 Ω (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. V OH V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS V DD – 1.620 V V 11. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50Ω TYP. OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PAD ASSIGNMENT Pad # Name X (µm) Y (µm) Description 1 GND 248 109 Ground. 2 GND 361 109 Ground. 3 GND 473 109 Ground. 4 GND 587 109 Ground. 5 GND 702 109 Ground. 6 N/C 874 109 No Connection. 7 GND 1042 109 Ground. 8 GNDBUF 1171 109 Ground, Buffer circuitry. 9 OE_SELECT 1400 125 Used to select between PECL or CMOS logic states for OE. Internal pull up. 10 LVDS 1400 259 LVDS output. 11 PECL 1400 476 PECL output. 12 VDDBUF 1400 616 3.3V power supply, Buffer circuitry. 13 VDDBUF 1400 716 3.3V power supply, Buffer circuitry. 14 PECLB 1400 871 Complementary PECL output. 15 LVDSB 1400 1089 Complementary LVDS output. 16 CMOS 1400 1227 CMOS output 17 GNDBUF 1389 1365 Ground, Buffer Circuitry. 18 OUTSEL1 1232 1365 Used to select CMOS, PECL or LVDS output type. Internal pull up. 19 SEL1 1042 1365 Used to select multiplication factor. Internal pull up. 20 SEL0 854 1365 Used to select multiplication factor. Internal pull up. 21 VDD 659 1365 3.3V power supply. 22 VDD 559 1365 3.3V power supply. 23 VDD 459 1365 3.3V power supply. 24 VDD 358 1365 3.3V power supply. 25 OUTSEL0 194 1365 Used to select CMOS, PECL or LVDS output type. Internal pull up. 26 XIN 109 1223 Crystal input. See crystal specification page 2. 27 XOUT 109 1017 Crystal output. See crystal specification page 2. 28 SEL3 109 858 Used to select multiplication factor. Internal pull up. 29 SEL2 109 646 Used to select multiplication factor. Internal pull up. 30 OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table on page 1. 31 VCON 109 181 Voltage control input. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7 PLL520-10 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-10 D C TEMPERATURE C=COMMERCIAL I=INDUSTRAL PART NUMBER PACKAGE TYPE D=DIE Order Number Marking Package Option PLL520-10DC P520-10DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8