PLL520-40 CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) FEATURES DIE CONFIGURATION XIN VDD VDD VDD VDD N/C DRIVE_SEL^ Reserved 23 22 21 20 19 18 XOUT 27 N/C 28 N/C 29 OE CTRL^ 30 VCON 31 Die ID: A1313-13C 5 6 X 7 8 GNDBUF 4 GNDBUF 3 Reserved (0,0) 2 GND Y 1 GND C502A GND The PLL520-40 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with CMOS outputs. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. 24 GND DESCRIPTION 25 26 GND • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 130MHz (no PLL). Low Injection Power for crystal 50uW. CMOS outputs (High Drive (30mA) or Standard Drive (10mA) output). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Thickness 10 mil. 62 mil • • • • N/C 65 mil (1550,1475) 17 GNDBUF 16 CMOS 15 N/C 14 N/C 13 12 VDDBUF VDDBUF 11 CMOS 10 N/C 9 N/C Note: ^ denotes internal pull up DIE SPECIFICATIONS BLOCK DIAGRAM OE XOUT Value Size Reverse side Pad dimensions Thickness 62 x 65 mil GND 80 micron x 80 micron 10 mil DRIVE_SEL AND OE_CTRL TABLE VCON Oscillator XIN Name Amplifier w/ integrated varicaps Q PLL520-40 DRIVE_SEL (Pad #19) 0 1 OE_CTRL (Pad #30) 0 1 Output Drive High Drive CMOS Standard CMOS (default) State Tri-state Output enabled (default) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-40 CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CONDITIONS CX+ CXC0 65MHz to 130MHz (VDD=3.3V) γ OF Fund. MIN. TYP. MAX. UNITS 2 2 pF 300 130 MHz MAX. UNITS 10 ms 2.6 65 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V VCON = 0 to 3.3V MIN. TYP. 200* ppm ±100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB 25 ppm pF % ppm/V kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-40 CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current CONDITIONS MIN. I DD V DD TYP. MAX. UNITS 50 40 3.63 55 mA V % mA MAX. UNITS 2.97 45 @ 50% V DD (CMOS) ±50 5. Jitter Specifications PARAMETERS CONDITIONS Period jitter RMS Period jitter peak-to-peak MIN. 77.76MHz 77.76MHz Integrated 12 kHz to 20 MHz at 77.76MHz Integrated jitter RMS TYP. 2.5 18.5 ps ps 0.5 ps 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 77.76MHz -75 -95 -125 -145 -155 dBc/Hz Phase Noise relative to carrier Note: Phase Noise at VCON = 0V 7. CMOS Output Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-40 CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PAD ASSIGNMENT Pad # Name X (µm) Y (µm) Description 1 Optional GND 248 109 Optional Ground. 2 Optional GND 361 109 Optional Ground. 3 Optional GND 473 109 Optional Ground. 4 Optional GND 587 109 Optional Ground. 5 GND 702 109 Ground. 6 Reserved 874 109 Reserved for future use. 7 Optional GNDBUF 1042 109 Optional Ground, buffer circuitry. 8 Optional GNDBUF 1171 109 Optional Ground, buffer circuitry. 9 Not connected 1400 125 Not Connected. 10 Not connected 1400 259 Not Connected.. 11 CMOS OUT 1400 476 CMOS output. 12 VDDBUF 1400 616 Power supply, buffer circuitry. 13 Optional VDDBUF 1400 716 Optional power supply, buffer circuitry. 14 Not connected 1400 871 Not Connected. 15 Not connected 1400 1089 Not Connected. 16 Optional CMOS OUT 1400 1227 Optional CMOS output. 17 GNDBUF 1389 1365 Ground, buffer circuitry. 18 Reserved 1232 1365 19 DRIVE_SEL 1042 1365 20 Not connected 854 1365 Reserved for future use. Used to select drive strength. See DRIVE_SEL AND OE_CTRL TABLE on page 1. Not Connected. 21 Optional VDD 659 1365 Optional power supply. 22 Optional VDD 559 1365 Optional power supply. 23 VDD 459 1365 Power supply. 24 Optional VDD 358 1365 Optional power supply. 25 Not connected 194 1365 Not Connected. 26 XIN 109 1223 Crystal input. See Crystal Specifications on page 2. 27 XOUT 109 1017 Crystal output. See Crystal Specifications on page 2. 28 Not connected 109 858 Not Connected. 29 Not connected 109 646 30 OE_CTRL 109 397 31 VCON 109 181 Not Connected. Used to enable/disable the output(s). See DRIVE_SEL AND OE_CTRL TABLE on page 1. Internal pull up. Voltage control input. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-40 CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-40 D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE Order Number Marking Package Option PLL520-40DC P520-40DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5