PLL620-80 Low Phase Noise XO (9.5-65MHz Output) DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS 4 5 6 Reserved X 7 OE_SEL^ 8 GNDBUF 3 GNDBUF 2 GND (0,0) 1 GND Y GNDBUF 9 GND The PLL620-80 is a XO IC specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs. 25 GND DESCRIPT ION (1550,1475) GND 19MHz to 65MHz crystal input. Output range: 9.5MHz – 65MHz Selectable OE Logic (enable high or enable low). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 2.5V or 3.3V Power Supply. Available in die form. 62 mil 65 mil OUTPUT SELECTION AND ENABLE DIE SPEC IFICATIONS Name Value Size Reverse side Pad dimensions Thickness 62 x 65 mil GND 80 micron x 80 micron 10 mil OUT_SEL1* (Pad 18) 0 0 1 1 OUT_SEL0* (Pad 25) 0 1 0 1 OE_SELECT (Pad 9) OE_CTRL (Pad 30) 0 1 (Default) 0 (Default) 1 0 BLOCK DIAGRAM 1 (Default) OE Q XIN XOUT Q Oscillator Amplifier Selected Output* High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state Pads #9, #18 & #25: Bond to GND to set to “0”, No connection results to “default” setting through internal pull-up. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” OUTPUT FREQUENCY SELECTOR S2 PLL620-80 S2 Output 0 1(Default)* Input/2 Input *In ternally set to ‘Default’ through 60KΩ pull-up resistor 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 1 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature VDD VI VO TS TA Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model TJ MIN. MAX. UNITS -0.5 -0.5 -65 -40 4.6 VDD +0.5 VDD +0.5 150 85 V V V C C 125 260 2 C C kV Exposure of the device under conditions beyond the limits specified by M axim um Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational lim its noted in this specification is not im plied. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL F XIN CL (xta l) C0 RE CONDITIONS Fundamental Die MIN. TYP. 19 MAX. UNITS 65 MHz pF pF 8* 5 30 AT cut Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tes ted to any specific limits . 3. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage IDD VDD Output Clock Duty Cycle Short Circuit Current CONDITIONS MIN. TYP. PECL/LVDS/ CMOS @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 2.25 45 45 45 50 50 50 50 MAX. UNITS 100/80/40 3.63 55 55 55 mA V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 2 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) 4. Jitter Specifications PARAMETERS CONDITIONS Period jitter RMS at 27MHz Period jitter peak-to-peak at 27MHz Accumulated jitter RMS at 27MHz MIN. TYP. MAX. 2.3 18.5 2.3 20 24 25 With capacitive decoupling between VDD and GND. Over 10,000 cycles Accumulated jitter peak-to-peak at 27MHz Random Jitter With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “ RJ” measured on Wavecrest SIA 3000 2.3 UNITS ps ps ps Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 27MHz -75 -100 -125 -140 -145 dBc/Hz Phase Noise relative to carrier Note: Phase Noise measured on Agilent E5500 6. CMOS Output Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL IOH IOL IOH IOL CONDITIONS VOH = VDD -0.4V, VDD =3.3V VOL = 0.4V, VDD = 3.3V VOH = VDD -0.4V, VDD =3.3V VOL = 0.4V, VDD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 3 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage VOD VOH VOL VOS Offset Magnitude Change VOS Power-off Leakage IOXD Output Short Circuit Current IOSD CONDITIONS VOD RL = 100 (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 1.4 1.1 1.2 1.375 mV mV V V V 0 3 25 mV 1 10 uA -5.7 -8 mA Vou t = VDD or GND VDD = 0V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 CL = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50 VOD V OS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% V DIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 4 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. VOH VOL RL = 50 to (VDD – 2V) (see figure) VDD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS VDD – 1.620 V V 10. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50 TYP. OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 5 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) PAD DESCRIPT IONS Pad # Name X (m) Y (m) Description 1 2 GND GND 248 361 109 109 Ground. Ground. 3 4 5 6 7 8 Optional GND GND GND Reserved GNDBUF GNDBUF 473 587 702 874 1042 1171 109 109 109 109 109 109 9 OE_SEL 1400 125 10 11 12 13 14 15 16 17 LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF 1400 1400 1400 1400 1400 1400 1400 1389 259 476 616 716 871 1089 1227 1365 18 OUTSEL1 1232 1365 19 20 21 22 23 24 Reserved Not connected VDD Optional VDD VDD VDD 1042 854 659 559 459 358 1365 1365 1365 1365 1365 1365 25 OUTSEL0 194 1365 26 27 28 XIN XOUT Not connected 109 109 109 1223 1017 858 29 S2 109 646 30 OE_CTRL 109 397 31 Not connected 109 181 Optional Ground. Ground. Ground. Reserved for future use. Ground, buffer circuitry. Ground, buffer circuitry. This is the selector input to choose the OE control logic. See the OE SELECTION AND ENABLE table on page 1. Internal pull up. LVDS output. PECL output. Power supply, buffer circuitry. Power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output. Ground, buffer circuitry. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Reserved for future use. Not Connected. Power supply. Optional Power supply. Power supply. Power supply. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Crystal input. See Crystal Specifications on page 3. Crystal output. See Crystal Specifications on page 3. Not Connected. Output Divide by Two selector pin, as presented on the OUTPUT FREQUENCY SELECTOR Table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not connected. Note: for optim al Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 6 PLL620-80 Low Phase Noise XO (9.5-65MHz Output) ORDERING INFORMATION For part ordering, please contact our Sales D epartment: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-80 PART NUMBER DC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PLL620-80DC P620-80DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or system s without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/28/09 Page 7