Revised April 2000 SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs General Description Features The SCAN18541T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). ■ IEEE 1149.1 (JTAG) Compliant ■ Dual output enable signals per byte ■ 3-STATE outputs for bus-oriented applications ■ 9-bit data busses for parity applications ■ Reduced-swing outputs source 32 mA/sink 64 mA ■ Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V ■ TTL compatible inputs ■ 25 mil pitch SSOP (Shrink Small Outline Package) ■ Includes CLAMP and HIGHZ instructions ■ Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number SCAN18541TSSC MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Names Pin Names Description AI(0–8) Input Pins, A Side BI(0–8) Input Pins, B Side AOE1, AOE2 3-STATE Output Enable Input Pins, A Side BOE1, BOE2 3-STATE Output Enable Input Pins, B Side AO(0–8) Output Pins, A Side AO(0–8) Output Pins, B Side Truth Tables Inputs AOE1 AOE2 AI(0–8) AO(0–8) L L H H H X X Z X H X Z L L L L Inputs BOE1 DS010965 BI(0–8) BO(0–8) L L H H H X X Z X H X Z L L L L H = HIGH Voltage Level L = LOW Voltage Level © 2000 Fairchild Semiconductor Corporation BOE2 X = Immaterial Z = High Impedance www.fairchildsemi.com SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs October 1991 SCAN18541T Block Diagrams Byte A Tap Controller Byte B Note: BSR stands for Boundary Scan Register. www.fairchildsemi.com 2 cant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18541T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. Instruction Register Scan Chain Definition The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB→LSB Instruction Code The INSTRUCTION register is an 8-bit register which captures the default value of 10000001. The two least signifi- Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGH-Z All Others BYPASS Scan Cell TYPE1 Scan Cell TYPE2 3 www.fairchildsemi.com SCAN18541T Description of Boundary-Scan Circuitry SCAN18541T Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (42 Bits in Length) www.fairchildsemi.com 4 (Continued) Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type 41 AOE1 3 Input TYPE1 40 AOE2 54 Input TYPE1 39 AOE 38 BOE1 26 37 BOE2 31 36 BOE 35 AI0 34 Scan Cell Type Internal TYPE2 Input TYPE1 Input TYPE1 Internal TYPE2 55 Input TYPE1 AI1 53 Input TYPE1 33 AI2 52 Input TYPE1 32 AI3 50 Input TYPE1 31 AI4 49 Input TYPE1 30 AI5 47 Input TYPE1 29 AI6 46 Input TYPE1 28 AI7 44 Input TYPE1 27 AI8 43 Input TYPE1 26 BI0 42 Input TYPE1 25 BI1 41 Input TYPE1 24 BI2 39 Input TYPE1 23 BI3 38 Input TYPE1 22 BI4 36 Input TYPE1 21 BI5 35 Input TYPE1 20 BI6 33 Input TYPE1 19 BI7 32 Input TYPE1 18 BI8 30 Input TYPE1 17 AO0 2 Output TYPE2 16 AO1 4 Output TYPE2 15 AO2 5 Output TYPE2 14 AO3 7 Output TYPE2 13 AO4 8 Output TYPE2 12 AO5 10 Output TYPE2 11 AO6 11 Output TYPE2 10 AO7 13 Output TYPE2 9 AO8 14 Output TYPE2 8 BO0 15 Output TYPE2 7 BO1 16 Output TYPE2 6 BO2 18 Output TYPE2 5 BO3 19 Output TYPE2 4 BO4 21 Output TYPE2 3 BO5 22 Output TYPE2 2 BO6 24 Output TYPE2 1 BO7 25 Output TYPE2 0 BO8 27 Output TYPE2 5 Control Signals A–in B–in A–out B–out www.fairchildsemi.com SCAN18541T Description of Boundary-Scan Circuitry SCAN18541T Absolute Maximum Ratings(Note 1) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC ) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA Supply Voltage (VCC) SCAN Products DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V +20 mA Minimum Input Edge Rate ∆V/∆t ±70 mA VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications. ±70 mA Junction Temperature +140°C SSOP Storage Temperature 125 mV/ns VIN from 0.8V to 2.0V DC VCC or Ground Current Per Output Pin 0V to VCC −40°C to +85°C Operating Temperature (TA) −0.5V to VCC +0.5V DC Output Source/Sink Current (IO) 0V to VCC Output Voltage (VO) −20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) −65°C to +150°C ESD (Min) 2000V DC Electrical Characteristics Symbol VIH Parameter VCC (V) TA = +25°C Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 VIL Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 VOH Minimum HIGH 4.5 3.15 3.15 Output Voltage 5.5 4.15 4.15 (Note 3) 4.5 2.4 2.4 5.5 2.4 2.4 VOL 4.5 2.4 5.5 2.4 Maximum LOW 4.5 0.1 0.1 Output Voltage 5.5 0.1 0.1 (Note 3) 4.5 0.55 0.55 5.5 0.55 0.55 4.5 0.55 5.5 0.55 Units V V V V V V V V Conditions VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH IOH = −32 mA VIN = VIL or VIH IOH = −24 mA IOUT = 50 µA VIN = VIL or VIH IOL = 64 mA VIN = VIL or VIH IOL = 48 mA IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA IIN Maximum Input 5.5 2.8 3.6 µA VI = VCC TDI, TMS Leakage −385 −385 µA VI = GND −160 −160 µA VI = GND Minimum Input Leakage 5.5 5.5 94 94 mA VOLD = 0.8V Max −40 −40 mA VOHD = 2.0V Min ±5.0 µA VI (OE) = VIL, VIH −100 mA VO = 0V IOLD Minimum Dynamic IOHD Output Current (Note 2) IOZ Maximum Output Leakage Current 5.5 ±0.5 IOS Output Short 5.5 −100 Circuit Current ICC Maximum Quiescent Supply Current www.fairchildsemi.com VI = VCC, GND (min) 5.5 16.0 88 µA 5.5 750 820 µA 6 VO = Open TDI, TMS = VCC VO = Open TDI, TMS = GND Symbol Parameter (Continued) TA = +25°C VCC (V) ICCt Maximum ICC TA = −40°C to +85°C Typ Units Conditions Guaranteed Limits 5.5 2.0 2.0 VI = VCC–2.1V mA VI = VCC–2.1V Per Input 5.5 2.15 2.15 TDI/TMS Pin, mA Test One with the Other Floating Note 2: Maximum test duration 2.0 ms, one output loaded at a time. Note 3: All outputs loaded; thresholds associated with output under test. Noise Specifications Symbol VOLP Parameter Maximum HIGH Output Noise (Note 4)(Note 5) VOLV Minimum LOW Output Noise (Note 4)(Note 5) VOHP Maximum Overshoot (Note 4)(Note 6) VOHV Minimum VCC Droop (Note 4)(Note 6) VIHD Minimum HIGH Dynamic Input Voltage Level (Note 6)(Note 7) VILD TA = +25°C VCC Maximum LOW Dynamic Input Voltage Level (Note 6)(Note 7) TA = −40°C to +85°C Guaranteed Limits Units (V) Typ 5.0 1.0 1.5 V 5.0 −0.6 −1.2 V 5.0 VOH+1.0 VOH+1.5 V 5.0 VOH−1.0 VOH−1.8 V 5.5 1.6 2.0 2.0 V 5.5 1.4 0.8 0.8 V Note 4: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Note 6: Worst case package. Note 7: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). AC Electrical Characteristics Normal Operation: Symbol Parameter tPLH, Propagation Delay tPHL Data to Q tPLZ, Disable Time VCC TA = +25°C (V) CL = 50 pF tPZL, Enable Time tPZH CL = 50 pF (Note 8) Min 5.0 2.5 9.0 2.5 9.8 2.5 9.0 2.5 9.8 1.5 10.2 1.5 10.7 1.5 10.2 1.5 10.7 2.0 11.8 2.0 12.8 2.0 9.5 2.0 10.5 5.0 tPHZ 5.0 Typ TA = −40°C to +85°C Max Min Units Max ns ns ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. 7 www.fairchildsemi.com SCAN18541T DC Electrical Characteristics SCAN18541T AC Electrical Characteristics Scan Test Operation: Symbol Parameter tPLH, Propagation Delay tPHL TCK to TDO tPLZ, Disable Time tPHZ TCK to TDO tPZL, Enable Time tPZH TCK to TDO tPLH, Propagation Delay tPHL TCK to Data Out VCC TA = +25°C (V) CL = 50 pF (Note 9) Min 5.0 5.0 5.0 5.0 Typ TA = −40°C to +85°C CL = 50 pF Max Min Max 3.5 13.2 3.5 14.5 3.5 13.2 3.5 14.5 Units ns 2.5 11.5 2.5 11.9 2.5 11.5 2.5 11.9 3.0 14.5 3.0 15.8 3.0 14.5 3.0 15.8 5.0 18.0 5.0 19.8 5.0 18.0 5.0 19.8 5.0 18.6 5.0 20.2 5.0 18.6 5.0 20.2 ns ns ns ns ns During Update-DR State tPLH, Propagation Delay tPHL TCK to Data Out 5.0 During Update-IR State tPLH, Propagation Delay tPHL TCK to Data Out 5.0 During Test Logic 5.5 19.9 5.5 21.5 5.5 19.9 5.5 21.5 4.0 16.4 4.0 18.2 4.0 16.4 4.0 18.2 5.0 19.5 5.0 20.8 5.0 19.5 5.0 20.8 ns ns Reset State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 ns During Update-DR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 During Update-IR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 During Test Logic 5.0 19.9 5.0 21.5 5.0 19.9 5.0 21.5 5.0 18.9 5.0 20.9 5.0 18.9 5.0 20.9 6.5 22.4 6.5 24.2 6.5 22.4 6.5 24.2 ns 7.0 23.8 7.0 25.7 ns 7.0 23.8 7.0 25.7 Reset State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 ns During Update-DR State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 During Update-IR State tPZL, Propagation Delay tPZH TCK to Data Out During Test Logic 5.0 Reset State Note: All Propagation Delays involving TCK are measured from the falling edge of TCK. Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. www.fairchildsemi.com 8 Scan Test Operation: Symbol VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF Parameter (Note 10) tS Setup Time, H or L 5.0 3.0 3.0 ns 5.0 4.5 4.5 ns 5.0 3.0 3.0 ns 5.0 4.5 4.5 ns 5.0 3.0 3.0 ns 5.0 3.0 3.0 ns 5.0 8.0 8.0 ns 5.0 2.0 2.0 ns 5.0 4.0 4.0 ns 5.0 4.5 4.5 ns H 15.0 15.0 ns L 5.0 5.0 5.0 25 25 MHz 5.0 100 100 ns 0.0 100 100 ms Data to TCK (Note 11) tH Hold Time, H or L TCK to Data (Note 11) tS Setup Time, H or L AOE n, BOEn to TCK (Note 12) tH Hold Time, H or L TCK to AOEn, BOEn (Note 12) tS Setup Time, H or L Internal AOE, BOE, to TCK (Note 13) tH Hold Time, H or L TCK to Internal AOE, BOE (Note 13) tS Setup Time, H or L TMS to TCK tH Hold Time, H or L TCK to TMS tS Setup Time, H or L TDI to TCK tH Units Guaranteed Minimum Hold Time, H or L TCK to TDI tW fMAX Pulse Width TCK Maximum TCK Clock Frequency TPU Wait Time, Power Up to TCK TDN Power Down Delay 5.0 Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. Note 11: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 12: Timing pertains to BSR 37, 38, 40 and 41 only. Note 13: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. 9 www.fairchildsemi.com SCAN18541T AC Operating Requirements SCAN18541T Extended AC Electrical Characteristics TA = +25°C VCC = 5.0V Symbol Parameter CL = 50 pF TA = −40°C to +85°C 18 Outputs VCC = 5.0V ± 0.5V Switching CL = 250 pF (Note 14) Min Typ (Note 5) Max Min Max tPLH, Propagation Delay 3.0 11.0 4.0 13.0 tPHL Data to Output 3.0 11.0 4.0 15.0 tPZH, Output Enable Time tPZL tPHZ, Output Disable Time tPLZ tOSHL Pin to Pin Skew (Note 18) HL Data to Output tOSLH Pin to Pin Skew (Note 18) LH Data to Output Units 2.5 11.5 2.5 14.0 2.0 11.5 2.0 11.5 ns (Note 16) ns (Note 17) ns 0.5 1.0 1.0 ns 0.5 1.0 1.0 ns Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 15: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 16: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 17: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 18: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.0 pF VCC = 5.0V COUT Output Pin Capacitance 13.0 pF VCC = 5.0V CPD Power Dissipation Capacitance 34.0 pF VCC = 5.0V www.fairchildsemi.com 10 Conditions SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com