Revised January 2001 SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs General Description Features The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). ■ High performance BiCMOS technology ■ 25Ω series resistors in outputs eliminate the need for external terminating resistors ■ Dual output enable control signals ■ 3-STATE outputs for bus-oriented applications ■ 25 mil pitch SSOP (Shrink Small Outline Package) ■ IEEE 1149.1 (JTAG) Compliant ■ Includes CLAMP, IDCODE and HIGHZ instructions ■ Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT ■ Power Up 3-STATE for hot insert ■ Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number SCAN182245ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide SCAN182245AMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Description Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 2001 Fairchild Semiconductor Corporation DS011657 Description A1(0–8) Side A1 Inputs or 3-STATE Outputs B1(0–8) Side B1 Inputs or 3-STATE Outputs A2(0–8) Side A2 Inputs or 3-STATE Outputs B2(0–8) Side B2 Inputs or 3-STATE Outputs G1, G2 Output Enable Pins (Active LOW) DIR1, DIR2 Direction of Data Flow Pins www.fairchildsemi.com SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs December 1993 SCAN182245A Truth Tables Inputs Inputs B1(0–8) B2(0–8) DIR2 A2(0–8) L L H ← H L L L ← L L H H → H L L H L → L Z H X Z G1 (Note 1) DIR1 A1(0–8) L L H ← H L L L ← L L H H → H L H L → H X Z G2 (Note 1) H = HIGH Voltage Level L = LOW Voltage Level Z X = Immaterial Z = High Impedance Note 1: Inactive-to-Active transition must occur to enable outputs upon power-up. Functional Description when HIGH enables data from A Ports to B Ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition. The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, Block Diagrams A1, B1, G1 and DIR1 A2, B2, G2 and DIR2 Note: BSR stands for Boundary Scan Register. Note: BSR stands for Boundary Scan Register. Tap Controller www.fairchildsemi.com 2 The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. Instruction Register Scan Chain Definition The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB → LSB Instruction Code SCAN182245A Product IDCODE (32-Bit Code per IEEE 1149.1) Versio n 0000 MSB Entity Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGH-Z 01000001 SAMPLE-IN Part Manufacture r Required 01000010 SAMPLE-OUT Number ID by 1149.1 00100010 EXTEST-OUT 1 10101010 IDCODE 11111111 BYPASS All Others BYPASS 111111 000000000 00000001111 0 MSB Scan Cell TYPE1 Scan Cell TYPE2 3 www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Scan Chain Definition (80 Bits in Length) www.fairchildsemi.com 4 SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample In is Active 5 www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample Out and EXTEST-Out are Active www.fairchildsemi.com 6 (Continued) BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type Bit No. Pin Name Pin No. Pin Type Scan Cell Type 79 DIR1 3 Input TYPE1 35 B10 2 Input TYPE1 78 G1 54 Input TYPE1 34 B11 4 Input TYPE1 77 AOE1 Internal TYPE2 33 B12 5 Input TYPE1 76 BOE1 Internal 32 B13 7 Input TYPE1 31 B14 8 Input TYPE1 10 Input TYPE1 75 DIR2 26 Input TYPE2 Control TYPE1 Signals 74 G2 31 Input TYPE1 30 B15 73 AOE2 Internal TYPE2 29 B16 11 Input TYPE1 72 BOE2 Internal TYPE2 28 B17 13 Input TYPE1 B1–in 71 A10 55 Input TYPE1 27 B18 14 Input TYPE1 70 A11 53 Input TYPE1 26 B20 15 Input TYPE1 69 A12 52 Input TYPE1 25 B21 16 Input TYPE1 68 A13 50 Input TYPE1 24 B22 18 Input TYPE1 67 A14 49 Input TYPE1 A1–in 23 B23 19 Input TYPE1 66 A15 47 Input TYPE1 22 B24 21 Input TYPE1 65 A16 46 Input TYPE1 21 B25 22 Input TYPE1 64 A17 44 Input TYPE1 20 B26 24 Input TYPE1 63 A18 43 Input TYPE1 19 B27 25 Input TYPE1 62 A20 42 Input TYPE1 18 B28 27 Input TYPE1 61 A21 41 Input TYPE1 17 A10 55 Output TYPE2 60 A22 39 Input TYPE1 16 A11 53 Output TYPE2 59 A23 38 Input TYPE1 15 A12 52 Output TYPE2 58 A24 36 Input TYPE1 A2–in 14 A13 50 Output TYPE2 57 A25 35 Input TYPE1 13 A14 49 Output TYPE2 A1–out 56 A26 33 Input TYPE1 12 A15 47 Output TYPE2 55 A27 32 Input TYPE1 11 A16 46 Output TYPE2 54 A28 30 Input TYPE1 10 A17 44 Output TYPE2 53 B10 2 Output TYPE2 9 A18 43 Output TYPE2 52 B11 4 Output TYPE2 8 A20 42 Output TYPE2 51 B12 5 Output TYPE2 7 A21 41 Output TYPE2 50 B13 7 Output TYPE2 6 A22 39 Output TYPE2 49 B14 8 Output TYPE2 B1–out 5 A23 38 Output TYPE2 48 B15 10 Output TYPE2 4 A24 36 Output TYPE2 A2–out 47 B16 11 Output TYPE2 3 A25 35 Output TYPE2 46 B17 13 Output TYPE2 2 A26 33 Output TYPE2 45 B18 14 Output TYPE2 1 A27 32 Output TYPE2 44 B20 15 Output TYPE2 0 A28 30 Output TYPE2 43 B21 16 Output TYPE2 42 B22 18 Output TYPE2 41 B23 19 Output TYPE2 40 B24 21 Output TYPE2 B2–out 39 B25 22 Output TYPE2 38 B26 24 Output TYPE2 37 B27 25 Output TYPE2 36 B28 27 Output TYPE2 7 B2–in www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry SCAN182245A SCAN ABT Live Insertion and Power Cycling Characteristics SCAN ABT is intended to serve in Live Insertion backplane applications. It provides 2nd Level Isolation1 which indicates that while external circuitry to control the output enable pin is unnecessary, there may be a need to implement differential length backplane connector pins for VCC and GND. As well, pre-bias circuitry for backplane pins may be necessary to avoid capacitive loading effects during live insertion. control the flip-flop. To bring the device out of high impedance, the Gn input must receive an inactive-to-active transition, a high-to-low transition on Gn in this case to change the state of the flip-flop. With a low on the Q output of the flip-flop, the NOR gate is free to allow propagation of a Gn signal. During power-down, the Power-On-Reset circuitry will become active and reset the flip-flop at approximately 1.8V VCC. Again, the Q output of the flip-flop returns to a high and disables the NOR gate from inputs from the Gn pin. The device will then remain in high impedance for the remaining ramp down from 1.8V to 0.0V VCC. SCAN ABT provides control of output enable pins during power cycling via the circuit in Figure 1. It essentially controls the Gn pin until VCC reaches a known level. During power-up, when VCC ramps through the 0.0V to 0.7V range, all internal device circuitry is inactive, leaving output and I/O pins of the device in high impedance. From approximately 0.8V to 1.8V VCC, the Power-On-Reset circuitry, (POR), in Figure 1 becomes active and maintains device high impedance mode. The POR does this by providing a low from its output that resets the flip-flop The output, Q, of the flip-flop then goes high and disables the NOR gate from an incidental low input on the Gn pin. After 1.8V VCC, the POR circuitry becomes inactive and ceases to Some suggestions to help the designer with live insertion issues: • The Gn pin can float during power-up until the PowerOn-Reset circuitry becomes inactive. • The Gn pin can float on power-down only after the Power-On-Reset has become active. The description of the functionality of the Power-On-Reset circuitry can best be described in the diagram of Figure 2. FIGURE 1. 1 Section 7, “Design Consideration for Fault Tolerant Backplanes”, Application Note AN-881. SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices. FIGURE 2. www.fairchildsemi.com 8 Recommended Operating Conditions Storage Temperature −65°C to +150 °C Ambient Temperature under Bias −55°C to +125 °C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150 °C Supply Voltage VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V (∆V/∆t) Minimum Input Edge Rate Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or −0.5V to +5.5V Power-Off State −0.5V to VCC in the HIGH State Current Applied to Output in LOW State (Max) Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Twice the Rated IOL (mA) −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) Note 3: Either voltage limit or current limit is sufficient to protect inputs. 10V ESD (HBM) Min. 2000V DC Electrical Characteristics Symbol VCC Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage Min VOH Output HIGH Voltage Min Min VOL Output LOW Voltage IIH Input HIGH Current Min Typ Max 2.0 All Others TMS, TDI Units V Conditions Recognized HIGH Signal 0.8 V Recognized LOW Signal −1.2 V IIN = −18 mA 2.5 V IOH = −3 mA 2.0 V IOH = −32 mA Min 0.8 V IOL = 15 mA Max 5 µA VIN = 2.7V (Note 4) Max 5 µA VIN = VCC Max 5 µA VIN = VCC IBVI Input HIGH Current Breakdown Test Max 7 µA VIN = 7.0V IBVIT Input HIGH Current Breakdown Test (I/O) Max 100 µA VIN = 5.5V IIL Input LOW Current Max −5 µA VIN = 0.5V (Note 4) Max −5 µA VIN = 0.0V Max −385 µA VIN = 0.0V V IID = 1.9 µA All Others TMS, TDI VID Input Leakage Test 0.0 4.75 IIH + IOZH Output Leakage Current Max 50 µA VOUT = 2.7V IIL + IOZL Output Leakage Current Max −50 µA VOUT = 0.5V IOZH Output Leakage Current Max 50 µA VOUT = 2.7V IOZL Output Leakage Current Max −50 µA VOUT = 0.5V IOS Output Short-Circuit Current Max −275 mA VOUT = 0.0V All Other Pins Grounded −100 ICEX Output HIGH Leakage Current Max 50 µA VOUT = VCC IZZ Bus Drainage Test 0.0 100 µA VOUT = 5.5V, All Others GND ICCH Power Supply Current Max 250 µA VOUT = VCC; TDI, TMS = VCC Max 1.0 mA VOUT = VCC; TDI, TMS = GND ICCL ICCZ ICCT ICCD Power Supply Current mA VOUT = LOW; TDI, TMS = VCC Max 65.8 mA VOUT = LOW; TDI, TMS = GND Max 250 µA TDI, TMS = VCC Max 1.0 mA TDI, TMS = GND VIN = VCC − 2.1V Max Power Supply Current Additional ICC/Input Dynamic ICC All Other Inputs Max 2.9 mA TDI, TMS inputs Max 3 mA VIN = VCC − 2.1V No Load Max 0.2 mA/ Outputs Open MHz One Bit Toggling, 50% Duty Cycle Note 4: Guaranteed not tested. 9 www.fairchildsemi.com SCAN182245A Absolute Maximum Ratings(Note 2) SCAN182245A AC Electrical Characteristics Normal Operation: TA = −40°C to +85°C VCC Symbol Parameter (Note 5) Propagation Delay tPLH tPHL A to B, B to A tPLZ Disable Time 5.0 5.0 tPHZ tPZL CL = 50 pF (V) Enable Time 5.0 tPZH Units Min Typ Max 1.0 3.1 5.2 1.5 4.4 6.5 1.5 4.8 8.6 1.5 5.2 8.9 1.5 5.5 9.1 1.5 4.6 8.2 ns ns ns Note 5: Voltage Range 5.0V ± 0.5V AC Electrical Characteristics Scan Test Operation TA = −40°C to +85°C VCC Symbol Parameter (Note 6) Propagation Delay tPLH tPHL TCK to TDO tPLZ Disable Time tPHZ TCK to TDO tPZL tPZH TCK to TDO tPLH Propagation Delay tPHL TCK to Data Out during Update-DR State 5.0 5.0 Enable Time tPLH Propagation Delay tPHL TCK to Data Out during Update-IR State tPLH Propagation Delay tPHL TCK to Data Out during Test Logic Reset State tPLZ Disable Time tPHZ TCK to Data Out during Update-DR State tPLZ Disable Time tPHZ TCK to Data Out during Update-IR State tPLZ Disable Time tPHZ TCK to Data Out during Test Logic Reset State tPZL Enable Time tPZH TCK to Data Out during Update-DR State tPZL Enable Time tPZH TCK to Data Out during Update-IR State tPZL Enable Time tPZH TCK to Data Out during Test Logic Reset State 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Note 6: Voltage Range 5.0V ± 0.5V Note: All Propagation Delays involving TCK are measured from the falling edge of TCK. www.fairchildsemi.com CL = 50 pF (V) 10 Units Min Typ Max 2.9 6.1 10.2 4.2 7.7 12.1 2.1 5.9 10.7 3.3 7.4 12.5 4.6 8.7 13.7 2.8 6.8 11.5 2.8 6.3 10.7 4.5 8.2 13.0 3.3 7.2 12.2 5.0 9.3 14.8 3.7 8.4 14.0 5.7 10.8 17.2 2.8 7.6 13.9 3.5 8.4 14.5 3.6 8.7 15.1 3.8 9.2 15.9 4.0 9.8 17.1 4.2 9.9 16.6 4.4 9.3 15.5 3.0 7.5 13.3 5.2 10.7 17.4 3.9 9.0 15.4 5.7 12.0 19.8 3.0 10.2 17.6 ns ns ns ns ns ns ns ns ns ns ns ns Scan Test Operation VCC Symbol Parameter Setup Time tS Data to TCK (Note 8) tH Hold Time Data to TCK (Note 8) Setup Time, H or L tS G1, G2 to TCK (Note 9) Hold Time, H or L tH TCK to G1, G2 (Note 9) tS Setup Time, H or L DIR1, DIR2 to TCK (Note 10) Hold Time, H or L tH TCK to DIR1, DIR2 (Note 10) tS Setup Time Internal OE to TCK (Note 11) tH Hold Time, H or L TCK to Internal OE (Note 10) Setup Time, H or L tS TMS to TCK tH Hold Time, H or L TCK to TMS tS Setup Time, H or L TDI to TCK Hold Time, H or L tH TCK to TDI tW Pulse Width TCK: H L fMAX Maximum TCK Clock Frequency Wait Time, tPU Power Up to TCK tDN Power Down Delay TA = −40°C to +85°C (V) CL = 50 pF (Note 7) Guaranteed Minimum 5.0 4.8 ns 5.0 2.5 ns 5.0 4.1 ns 5.0 1.7 ns 5.0 4.2 ns 5.0 2.3 ns 5.0 3.8 ns 5.0 2.3 ns 5.0 8.7 ns 5.0 1.5 ns 5.0 6.7 ns 5.0 5.0 ns Units 10.2 5.0 ns 8.5 5.0 50 MHz 5.0 100 ns 0.0 100 ms Note 7: Voltage Range 5.0V ± 0.5V Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 9: Timing pertains to BSR 74 and 78 only. Note 10: Timing pertains to BSR 75 and 79 only. Note 11: Timing pertains to BSR 72, 73, 76 and 77 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Capacitance Symbol Parameter Typ Units Conditions, TA = 25°C CIN Input Capacitance 5.9 pF VCC = 0.0V (Gn, DIRn) CI/O (Note 12) Output Capacitance 13.7 pF VCC = 5.0V (An, Bn) Note 12: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. 11 www.fairchildsemi.com SCAN182245A AC Operating Requirements SCAN182245A Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A www.fairchildsemi.com 12 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 13 www.fairchildsemi.com SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)