SS8021 Stereo Headphone Power Amplifier FEATURES DESCRIPTION High performance Class AB amplifier High signal-to-noise ratio Low distortion Low power consumption Large output voltage swing Excellent power supply ripple rejection Supply voltage range of 3.0V to 6.5V Surface-mount package - SO-8 APPLICATIONS The SS8021 is an output-rail-to-rail stereo audio power amplifier housed in an 8-pin SOP package capable of delivering 125mW of continuous power into 16Ω loads and 75mW into 32 Ω loads with THD <0.1% per channel. The gain of the amplifiers can be easily set with two external resistors - R I (input resistor) and RF (feedback resistor). The SS8021 is a dual channel, low voltage, low power, high performance amplifier. The quiescent current is typically 3mA at 5V. With excellent AC performance (small THD), it can be designed into a wide range of headphone driving applications. CD-ROM DVD-ROM CD-R/W MP3 Portable Stereo ORDERING INFORMATION SS8021(G)XX Packing: TR Tape and reel : TB Tubes This device is normally supplied with Pb-free lead finish (second-level interconnect) as SS8021G, but can be supplied with a traditional lead finish (SS8021) upon request. PIN CONFIGURATION SS8021 SYMBOL PIN DESCRIPTION OUTA 1 8 VDD OUTA INA(neg) 2 7 OUTB INA(neg) INA(pos) 2 3 inverting input A non-inverting input A INA(pos) 3 6 INB(neg) VSS 4 5 INB(pos) VSS INB(pos) INB(neg) OUTB VDD 4 5 6 7 8 negative supply non-inverting input B inverting input B output B positive supply 8/21/2004 Rev.2.01 www.SiliconStandard.com 1 output A 1 of 8 SS8021 BLOCK DIAGRAM SS8021 INA(pos) 3 7 + 2 VDD _ INA(neg) VSS 8 1 OUTA _ 6 + 5 4 OUTB INB(neg) INB(pos) ABSOLUTE MAXIMUM RATINGS (Note1) SYMBOL PARAMETER VDD Tstg Tamb Supply voltage Storage temperature Operating ambient temperature ESD ESD voltage CONDITION MIN MAX UNIT 0 -65 -40 7.0 +150 +85 V °C °C - 2 KV HBM Notes: 1. Absolute Maximum Ratings are limits beyond which damage to the device may occur. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER Thermal resistance from junction to ambient in free air SO8 VALUE UNIT 240 °C/W TEST AND APPLICATION INFORMATION VDD 220µF + 3.9kΩ VOUTA RL 100kΩ 2.2µF VINA 3.9kΩ 1 2 3 8 _ + + SS8021 2.2µF 3.9kΩ 6 _ VINB + 5 C6 100µF 7 1µF 4 100kΩ 3.9kΩ 220µF + VOUTB RL Fig.1 Measurement circuit for inverting application 8/21/2004 Rev.2.01 www.SiliconStandard.com 2 of 8 SS8021 ELECTRICAL CHARACTERISTICS VDD = 5V; VSS= 0V; TA = 25°C; f I= 1kHz; RL = 32Ω connected to VDD/2; unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT Supplies VDD VSS IDD Supply voltage 3.0 5.0 6.5 V Single Dual 3.0 1.5 5.0 2.5 6.5 3.25 V V no load -1.5 - -2.5 3.0 -3.25 5.0 V mA no load - 15 25 mW Negative supply voltage Supply current Ptot Total power dissipation DC Characteristics VI(OS) Input offset voltage -50 - 50 mV VCM GV Common mode voltage Open-loop voltage gain RL = 5kΩ 0 60 90 3.5 - V dB IO RO Maximum output current Output resistance THD+N <0.1% closed-loop - 70 0.1 - mA Ω VDD-VOH VOL-VSS Output Voltage Swing High Output Voltage Swing Low Sourcing current = 100mA Sinking current = 100mA PSRR Power supply rejection ratio fi = 1kHz; Vripple(rms) = 100mVrms RL=32Ω ,Cb=1µF, PO=70mW - 0.4 0.5 70 1 1 - V V dB - 65 - dB note 2 open-loop; RL = 5kΩ note 1; RL = 16Ω ; f=1kHz - < 0.1 5 125 - % MHz mW note 1; RL = 32Ω ; f=1kHz - 75 - mW α CS Channel separation AC Characteristics THD fG Total harmonic distortion Unity gain frequency PO Maximum output power Notes: 1. Values are proportional to VDD; THD+N < 0.1% 2. VDD = 5.0V; VO(P-P) = 4.0V (at 0 dB) 8/21/2004 Rev.2.01 www.SiliconStandard.com 3 of 8 SS8021 Electrical Characteristics CIN=2.2µF, COUT=330µF, Cb=1µF, Av=1, Ri=18kΩ , Rf=18kΩ ; Av=-2, Ri=18kΩ , Rf=36kΩ ; Av=-4, Ri=9kΩ ,Rf=36kΩ ,TA=25°C THD+N vs Output Power THD+N vs Frequency 10 5 2 10 5 VDD=5V RL=32Ω Av=-1 1 1 0.5 0.5 % 0.2 0.2 0.1 0.1 1kHz 0.02 0.01 1m 5m Av=-2V/V 0.05 10m Av=-1V/V 0.02 20Hz 2m Av=-4V/V % 20kHz 0.05 VDD=5V RL=32Ω Po=50mW 2 20m 50m 100m 0.01 20 200m 50 100 200 500 W THD+N vs Frequency 2k 5k 10k 20k THD+N vs Output Power 10 10 5 2 1k Hz 5 VDD=5V RL=32Ω Av=-1 2 1 VDD=5V RL=16Ω Av=-1 1 0.5 0.5 % 20kHz % 0.2 0.2 1kHz Po=70mW 0.1 0.1 0.05 0.05 20Hz Po=60mW 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 0.02 0.01 2m 20k 5m 10m Hz THD+N vs Frequency 2 5 2 VDD=3.3V RL=32Ω Av=-1 1 Av=-4V/V 0.5 0.5 Av=-2V/V 20kHz % 0.2 0.2 0.1 0.1 0.05 0.05 Av=-1V/V 50 100 200 0.02 500 1k 2k 5k 10k 20k 1kHz 20Hz 0.01 1m 2m 5m 10m 20m 50m 100m W Hz 8/21/2004 Rev.2.01 200m THD+N vs Output Power VDD=5V RL=16Ω Po=50mW % 0.01 20 100m 10 1 0.02 50m W 10 5 20m www.SiliconStandard.com 4 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) THD+N vs Frequency THD+N vs Output Power 10 10 5 2 5 VDD=3.3V RL=32Ω Po=25mW 2 1 VDD=3.3V RL=16Ω Av=-1 1 Av=-4V/V 0.5 20kHz 0.5 % % Av=-2V/V 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 20 Av=-1V/V 50 100 20Hz 1kHz 0.02 200 500 1k 2k 5k 10k 0.01 2m 20k 3m 4m 5m 6m 7m 10m 20m Hz 30m 40m 50m 70m 100m W THD+N vs Frequency Output Noise 10 100u 90u 5 2 80u VDD=3.3V RL=16Ω Po=25mW 70u 60u 50u 1 0.5 Av=-4V/V VDD=5V RL=32Ω Av=-1 Cb=1µF BW=20kHz , No filters 40u Av=-2V/V % V 30u 0.2 0.1 A- Weighting 20u Av=-1V/V 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 10u 20 20k 50 100 200 500 Hz Channel Separation -40 -45 -50 -10 VDD=5V RL=32Ω Av=-1 Po=70mW Cb=1µF -20 -30 -40 -50 Channel A to B -55 d B 5k 10k 20k +0 -25 -35 2k Power Supply Rejection Ratio -20 -30 1k Hz d B -60 -65 VDD=5V RL=32Ω Av=-1 Vripple=100mVrms Cb=1µF Vpin 3,5=2.5V FORCED -60 -70 -70 -75 -80 Channel B to A -80 -90 -85 -100 -90 -110 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k -120 20 Hz 8/21/2004 Rev.2.01 50 100 200 500 1k 2k 5k 10k 20k Hz www.SiliconStandard.com 5 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) Open Loop Frequency Response 8/21/2004 Rev.2.01 www.SiliconStandard.com 6 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) Supply Current vs. Temperature 2.4 2.4 2.2 Supply Current (mA) Supply Current (mA) Supply Current vs.Supply Voltage 2.6 2.2 2 1.8 1.6 1.4 VDD=5V 2 1.8 1.6 1.4 VDD=3V 1.2 1.2 1 1 2.5 3.5 4.5 5.5 Supply Voltage(V) 6.5 -50 Offset Voltage vs. Supply Voltage -25 0 25 50 75 Temperature (°C) 100 125 Offset Voltage vs.Temperature 5 5 4.5 4.6 Offset Voltage (mV) Offset Voltage (mV) 4.8 4.4 4.2 4 3.8 3.6 3.4 4 VDD=3V 3.5 VDD=5V 3 2.5 3.2 3 2 2.5 3.5 4.5 5.5 Supply Voltage (V) 6.5 -50 Sinking Current vs. Vo-Vss 0 25 50 75 Temperature (°C) 100 125 Sourcing Current vs. VDD-Vo 350 350 300 Sourcing Current(mA) 300 Sinking Current(mA) -25 VDD=5V 250 200 150 VDD=3V 100 VDD=5V 250 200 VDD=3V 150 100 50 50 0 0 0 8/21/2004 Rev.2.01 0.5 1 1.5 2 VO-Vss(V) 2.5 3 0 www.SiliconStandard.com 0.5 1 1.5 2 VDD - VO(V) 2.5 3 7 of 8 SS8021 PHYSICAL DIMENSIONS C E H L D Θ 7 7° (4X) Taping Specification A2 A A1 y e B Feed Direction Typical SOP Package Orientation 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. MIN. DIMENSION IN MM NOM. MAX. MIN. DIMENSION IN INCH NOM. A 1.35 1.60 1.75 0.053 0.063 0.069 A1 0.10 ----- 0.25 0.004 ----- 0.010 A2 B ----0.33 1.45 ----- ----0.51 ----0.013 0.057 ----- ----0.020 C D E e H L 0.19 4.80 3.80 ----5.80 0.40 ------------1.27 --------- 0.25 5.00 4.00 ----6.20 1.27 0.007 0.189 0.150 ----0.228 0.016 ------------0.050 --------- 0.010 0.197 0.157 ----0.244 0.050 y Θ ----- ----- 0.10 ----- ----- 0.004 0º ----- 8º 0º ----- 8º SYMBOL MAX. Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 8/21/2004 Rev.2.01 www.SiliconStandard.com 8 of 8