AKM AK4702EQ

ASAHI KASEI
[AK4702EQ]
AK4702EQ
2ch DAC with AV SCART switch
GENERAL DESCRIPTION
The AK4702 offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture
for its modulator, the AK4702 delivers a wide dynamic range while preserving linearity for improved
THD+N performance. The AK4702 integrates a combination of SCF and CTF filters, removing the need
for high cost external filters and increasing performance for systems with excessive clock jitter. The
AK4702 also including the audio switches and volumes designed primarily for digital set-top-box systems.
The AK4702 is offered in a space saving 48-pin LQFP package.
FEATURES
DAC
† Sampling Rates Ranging from 8kHz to 50kHz
† 18bit 8x FIR Digital Filter
† 2nd order Analog LPF
† On chip Buffer with Single-ended Output
† Digital de-emphasis for 32k, 44.1k and 48kHz sampling
† I/F format: 18bit MSB justified, 18/16bit LSB justified, I2S
† Master clock: 256fs, 384fs
† High Tolerance to Clock Jitter
Analog switches for SCART
Audio section
† THD+N: -86dB (@2Vrms)
† Dynamic Range: 96dB (@2Vrms)
† Stereo Analog Volume with Zero-cross Detection Circuit
(+6dB to –60dB & Mute)
† Five Analog Inputs
Two Stereo Input (TV, VCR SCART)
One Mono Input for Tone
† Five Analog Outputs
Two Stereo Outputs (TV, VCR SCART)
One Mono Output
† Loop-through mode for standby
† Pop Noise Free Circuit for Power on/off
Video section
† 75ohm driver
† 6dB Gain for Outputs
† Adjustable gain
† Four CVBS/Y inputs (ENCx2, TV, VCR),
Three CVBS/Y output (RF, TV, VCR)
† Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR)
† Bi-directional control for VCR-Chroma/Red
† Two G and B inputs (ENC, VCR), One G and B outputs (TV)
Power supply
† 5V+/-5% and 12.6V~10V
† Low Power Dissipation
Package
† Small 48pin LQFP
MS0424-E-00
2005/09
-1-
ASAHI KASEI
[AK4702EQ]
MONOOUT
MONOIN
VOL
-6dB/0dB/2.44dB
MCLK
TVOUTL
LRCK
DAC
BICK
TVOUTR
SDATA
Volume #1
Volume #0
TV1/0
VCRINL
MONO
+6 to -60dB
(2dB/step)
VCRINR
VCROUTL
TVINL
VCROUTR
TVINR
Bias (Mute)
VCOM5
VCR1/0
VCOM12
SCK
SDA
VD
Register
VP
Control
VSS
PDN
Audio Block
MS0424-E-00
2005/09
-2-
ASAHI KASEI
( Typical connection )
[AK4702EQ]
( Typical connection )
VVD1
VVD2
6dB
RFV
6dB
TVVOUT
RF Mod
VVSS
ENC CVBS/Y
ENCV
ENC Y
ENCY
VCR CVBS/Y
TV CVBS
VCRVIN
TVVIN
0, 1, 2, 3dB
ENC R/C
ENC C
VCR R/C
ENCRC
6dB
ENCC
TVRC
TV SCART
VCRRC
ENC G/CVBS
ENCG
VCR G
VCRG
ENC B
ENCB
VCR B
VCRB
6dB
TVG
6dB
TVB
6dB
VCRVOUT
VCR SCART
6dB
VCRC
Video Block
( Typical connection )
( Typical connection )
VCR FB
VCRFB
2V
6dB
TVFB
0V
TV SCART
0/ 6/ 12V
TVSB
VCRSB
VCR SCART
0/ 6/ 12V
Monitor
INT
Video Blanking Block
MS0424-E-00
2005/09
-3-
ASAHI KASEI
[AK4702EQ]
„ Ordering Guide
-10 ∼ +70°C
AK4702EQ
48pin LQFP (0.5mm pitch)
TVFB
VCRVOUT
RFV
PDN
SDA
SCL
LRCK
SDTI
BICK
MCLK
VD
VSS
48
47
46
45
44
43
42
41
40
39
38
37
„ Pin Layout
VCRC
1
36
PVCOM
VVSS
2
35
DVCOM
TVVOUT
3
34
VP
VVD2
4
33
MONOOUT
TVRC
5
32
TVOUTL
TVG
6
31
TVOUTR
TVB
7
30
VCROUTL
29
VCROUTR
AK4702EQ
Top View
21
22
23
24
VCRSB
TVSB
VCRINR
VCRINL
INT
25
20
12
VCRB
ENCC
19
TVINR
VCRG
26
18
11
VCRRC
ENCRC
17
TVINL
VCRFB
27
16
10
VCRVIN
ENCG
15
MONOIN
TVVIN
28
14
9
ENCY
ENCB
13
8
ENCV
VVD1
„ Compatibility with AK4702
THD+N at 3Vrms output
DG, DP
AK4702
-60dB
-/+3%, -/+3deg (min/max)
MS0424-E-00
AK4702EQ
0.4%, 0.8deg (typ)
2005/09
-4-
ASAHI KASEI
[AK4702EQ]
PIN/FUNCTION
No.
1
2
3
4
Pin Name
VCRC
VVSS
TVVOUT
VVD2
I/O
O
O
-
5
6
7
8
TVRC
TVG
TVB
VVD1
O
O
O
-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
INT
VCRSB
TVSB
VCRINR
VCRINL
TVINR
TVINL
MONOIN
VCROUTR
VCROUTL
TVOUTR
TVOUTL
MONOOUT
VP
35
DVCOM
O
36
PVCOM
O
I
I
I
I
I
I
I
I
I
I
I
I
O
I/O
O
I
I
I
I
I
O
O
O
O
O
-
Function
Chrominance Output Pin for VCR
Video Ground Pin. 0V.
Composite/Luminance Output Pin for TV
Video Power Supply Pin #2. 5V
Normally connected to VVSS with a 0.1µF ceramic capacitor in parallel with
a 10µF electrolytic cap.
Red/Chrominance Output Pin for TV
Green Output Pin for TV
Blue Output Pin for TV
Video Power Supply Pin #1. 5V
Normally connected to VVSS with a 0.1µF ceramic capacitor in parallel with
a 10µF electrolytic cap.
Blue Input Pin for Encoder
Green Input Pin for Encoder
Red/Chrominance Input Pin1 for Encoder
Chrominance Input Pin2 for Encoder
Composite/Luminance Input Pin1 for Encoder
Composite/Luminance Input Pin2 for Encoder
Composite/Luminance Input Pin for TV
Composite/Luminance Input Pin for VCR
Fast Blanking Input Pin for VCR
Red/Chrominance Input Pin for VCR
Green Input Pin for VCR
Blue Input Pin for VCR
Interrupt Pin for Video Blanking
Slow Blanking Input/Output Pin for VCR
Slow Blanking Output Pin for TV
Rch VCR Audio Input Pin
Lch VCR Audio Input Pin
Rch TV Audio Input Pin
Lch TV Audio Input Pin
MONO Input Pin
Rch Analog Output Pin1
Lch Analog Output Pin1
Rch Analog Output Pin2
Lch Analog Output Pin2
MONO Analog Output Pin
Power Supply Pin. 12V
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
DAC Common Voltage Pin
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
Audio Common Voltage Pin
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap. The caps affect the settling time of audio bias level.
MS0424-E-00
2005/09
-5-
ASAHI KASEI
[AK4702EQ]
PIN/FUNCTION (Continued)
37
38
VSS
VD
-
Ground Pin. 0V.
DAC Power Supply Pin. 5V
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
39
MCLK
I
Master Clock Input Pin
An external TTL clock should be input on this pin.
40
BICK
I
Audio Serial Data Clock Pin
41
SDTI
I
Audio Serial Data Input Pin
42
LRCK
I
L/R Clock Pin
43
SCL
I
Control Data Clock Pin
44
SDA
I/O
Control Data Pin
45
PDN
I
Power-Down Mode Pin
When at “L”, the AK4702 is in the power-down mode and is held in reset. The
AK4702 should always be reset upon power-up.
46
RFV
O
Composite Output Pin for RF modulator
47
VCRVOUT
O
Composite/Luminance Output Pin for VCR
48
TVFB
O
Fast Blanking Output Pin for TV
Note: All input pins except pull-up/down pin should not be left floating.
MS0424-E-00
2005/09
-6-
ASAHI KASEI
[AK4702EQ]
Internal Equivalent Circuits
Pin No.
Pin Name
39
40
41
42
43
45
MCLK
BICK
SDTI
LRCK
SCL
PDN
Type
Equivalent Circuit
Description
VD
200
Digital IN
VSS
VD
44
SDA
200
Digital I/O
I2C Bus voltage must
not exceed VD.
VSS
21
INT
Normally connected to
VD(5V) through
10kohm resister
externally.
Digital OUT
VSS
46
47
48
1
3
5
6
7
RFV
VCROUT
TVFB
VCRC
TVVOUT
TVRC
TVG
TVB
VVD1
VVD2
Video OUT
VVSS
MS0424-E-00
VVSS
2005/09
-7-
ASAHI KASEI
Pin No.
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
[AK4702EQ]
Type
Equivalent Circuit
VVD1
200
Video IN
VVSS
VP
22
23
VCRSB
TVSB
Description
VP
200
The 120kohm is not
attached for TVSB.
Video SB
(120k)
VSS
VSS
VSS
VP
24
25
26
27
28
VCRINR
VCRINL
TVINR
TVINL
MONOIN
200
Audio IN
VSS
VP
29
30
31
32
33
VCROUTR
VCROUTL
TVOUTR
TVOUTL
MONOOU
T
VP
100
Audio OUT
VSS
VD
35
36
DVCOM
PVCOM
VSS
VD
VD
100
VCOM OUT
VSS VSS
MS0424-E-00
VSS
2005/09
-8-
ASAHI KASEI
[AK4702EQ]
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V;Note: 1)
Parameter
Power Supply
Symbol
VD
VVD1
VVD2
VP
|VSS-VVSS| (Note: 2)
IIN
VIND
VINV
VINA
Ta
Tstg
Input Current (any pins except for supplies)
Input Voltage
Video Input Voltage
Audio Input Voltage
Ambient Operating Temperature
Storage Temperature
Note: 1. All voltages with respect to ground.
Note: 2. VSS and VVSS must be connected to the same analog ground plane.
min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0
6.0
14
0.3
±10
VD+0.3
VVD1+0.3
VP+0.3
70
150
Units
V
V
V
V
V
mA
V
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=VVSS=0V; Note: 1)
Parameter
Power Supply
Symbol
VD
VVD1
VVD2
VP
Note: 3. Analog output voltage scales with the voltage of VD.
AOUT ([email protected]) = 2Vrms × VD/5.
min
4.75
4.75
VVD1
10
typ
5.0
5.0
5.0
12
max
5.25
VVD2
5.25
12.6
Units
V
V
V
V
14
20
5
30
40
10
mA
mA
mA
10
10
10
100
100
100
µA
µA
µA
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs)
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”; Note: 4)
VD
VVD1+VVD2
VP
Power-Down Mode (PDN = “L”; Note: 5)
VD
VVD1+VVD2
VP
Note: 4. STBY bit ="L", All video outputs active.
No signal, no load for A/V switches. fs=48kHz “0”data input for DAC.
Note: 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS.
MS0424-E-00
2005/09
-9-
ASAHI KASEI
[AK4702EQ]
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD = 4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.0
Low-Level Input Voltage
VIL
Low-Level Output Voltage
VOL
(SDA pin : Iout= 3mA, INT pin : Iout=
1mA)
Input Leakage Current
Iin
-
typ
-
max
0.8
0.4
Units
V
V
V
-
± 10
µA
ANALOG CHARACTERISTICS (AUDIO)
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 18bit Input
Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; Volume#0=Volume#1=0dB, 0dB=2Vrms output; unless
otherwise specified)
Parameter
min
typ
max
Units
18
bit
DAC Resolution
Stereo Input: (TVINL/TVINR/VCRINL/VCRINR pins)
Analog Input Characteristics
Input Voltage
2
Vrms
Input Resistance
100
150
kΩ
Mono Input: (MONOIN pin)
Analog Input Characteristics
Input Voltage
1
Vrms
Input Resistance
40
60
kΩ
Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note: 6)
Analog Output Characteristics
Volume#0 Step Width (0dB to –6dB)
6
dB
Volume#1 Step Width (+6dB to –12dB)
1.6
2
2.4
dB
(-12dB to –40dB)
0.5
2
3.5
dB
(-40dB to –60dB)
0.1
2
3.9
dB
THD+N
(at 2Vrms output. Note: 7)
-86
-80
dB
Dynamic Range (-60dB Output, A-weighted. Note: 7)
92
96
dB
S/N
(A-weighted. Note: 7)
92
96
dB
Interchannel Isolation (Note: 7, Note: 8)
80
90
dB
Interchannel Gain Mismatch (Note: 7, Note: 8)
0.3
dB
Gain Drift
200
ppm/°C
Load Resistance (AC-Lord; Note: 9)
TVOUTL/R, VCROUTL/R, MONOOUT
4.5
kΩ
Output Voltage
(Note: 9, Note: 10)
1.85
2
2.15
Vrms
Power Supply Rejection (PSR. Note: 11)
50
dB
Note: 6. Measured by Audio Precision System Two Cascade.
Note: 7. DAC to TVOUT.
Note: 8. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS.
Note: 9. THD+N : -80dB(min. at 2Vrns).
Note: 10. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD,
Stereo output ([email protected]) = 2Vrms × VD/5 when volume#0=volume#1=0dB. Do not output signals over 3Vrms.
Note: 11. The PSR is applied to VD with 1kHz, 100mV.
MS0424-E-00
2005/09
- 10 -
ASAHI KASEI
[AK4702EQ]
FILTER CHARACTERISTICS (AUDIO)
(Ta = 25°C; VP=10.0∼12.6V, VD = 4.75∼5.25V, VVD1=VVD2 = 4.75∼5.25V; fs = 48kHz; DEM0 = “1”, DEM1 = “0”)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
21.77
kHz
Passband
±0.05dB
(Note: 12)
24.0
kHz
-6.0dB
Stopband
(Note: 12)
SB
26.23
kHz
Passband Ripple
PR
dB
± 0.06
Stopband Attenuation
SA
54
dB
Group Delay
(Note: 13)
GD
19.1
1/fs
Digital Filter + LPF
FR
dB
Frequency Response 0 ∼ 20.0kHz
± 0.5
Note: 12. The passband and stopband frequencies scale with fs (system sampling rate).
ex.) PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note: 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18bit data of
both channels to input register to the output of analog signal.
ANALOG CHARACTERISTICS (VIDEO)
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= “00” unless specified.)
Parameter
Conditions
min
typ
Sync tip clamp
0.7
voltage at output
Chrominance bias
2.2
voltage at output
Gain
Input=0.3Vp-p, 100kHz
5.5
6
RGB Gain
Input=0.3Vp-p, 100kHz
Load Resistance
Load Capacitance
Dynamic Output
Signal
Y/C Cross talk
S/N
Differential Gain
Differential Phase
Units
V
V
6.5
dB
VVOL1/0= “00”
5.5
6
6.5
dB
VVOL1/0= “01”
6.7
7.2
7.7
dB
VVOL1/0= “10”
7.7
8.2
8.7
dB
VVOL1/0= “11”
Interchannel Gain
Mismatch
Frequency response
Input impedance
Input Signal
max
8.6
9.1
9.6
dB
Input=0.3Vp-p, 100kHz (Note: 14)
-0.3
-
0.3
dB
Input=0.3Vp-p, Response at 6MHz
Chrominance input (internally biased)
f=100kHz, maximum with distortion < 1.0%,
gain=6dB.
Except RFV pin (Note: 15)
RFV pin (Note: 16)
C1 (Note: 15)
C2 (Note: 15, Note: 16)
f=100kHz, maximum with distortion < 1.0%
-1
40
-
-0.5
60
-
1.5
dB
kohm
Vpp
150
20k
-
-
-
400
15
3
ohm
ohm
pF
pF
Vpp
-
-50
-
dB
-
74
-
dB
-
+0.4
-
%
-
+0.8
-
Degree
f=4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC, VCRVOUT and VCRC outputs.
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW= 15kHz to 5MHz.
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
MS0424-E-00
2005/09
- 11 -
ASAHI KASEI
[AK4702EQ]
Note: 14. TVRC, TVG, TVB.
Note: 15. Refer the Figure 1.
R1
75 ohm
Video Signal Output
R2
75 ohm
C2
C1
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2, and Load Capacitance C1 and C2.
Note: 16. AC load. Refer the Figure 2.
Video Signal Output
R1
C2
max: 15pF
20k ohm
(AC load)
Figure 2. Load Resistance R1 and Load Capacitance C1
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=10.0 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Symbol
Min
typ
2.048
fCLK
Master Clock Frequency 256fs:
40
dCLK
Duty Cycle
3.072
fCLK
384fs:
40
dCLK
Duty Cycle
fs
8
LRCK Frequency
Duty
45
Duty Cycle
Audio Interface Timing
312.5
tBCK
BICK Period
100
tBCKL
BICK Pulse Width Low
100
tBCKH
Pulse Width High
50
tBLR
BICK “↑” to LRCK Edge
(Note: 17)
50
tLRB
LRCK Edge to BICK “↑”
(Note: 17)
50
tSDH
SDTI Hold Time
50
tSDS
SDTI Setup Time
Control Interface Timing (I2C Bus):
fSCL
SCL Clock Frequency
4.7
tBUF
Bus Free Time Between Transmissions
4.0
tHD:STA
Start Condition Hold Time
(prior to first clock pulse)
4.7
tLOW
Clock Low Time
4.0
tHIGH
Clock High Time
4.7
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling (Note: 18)
0.25
tSU:DAT
SDA Setup Time from SCL Rising
tR
Rise Time of Both SDA and SCL Lines
tF
Fall Time of Both SDA and SCL Lines
4.0
tSU:STO
Setup Time for Stop Condition
0
tSP
Pulse Width of Spike Noise
Suppressed by Input Filter
Reset Timing
tPD
150
PDN Pulse Width
(Note: 19)
MS0424-E-00
max
12.8
60
19.2
60
50
55
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
100
-
kHz
µs
µs
1.0
0.3
50
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
2005/09
- 12 -
ASAHI KASEI
[AK4702EQ]
Note: 17. BICK rising edge must not occur at the same time as LRCK edge.
Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 19. The AK4702 should be reset by PDN= “L” upon power up.
Note: 20. I2C is a registered trademark of Philips Semiconductors.
MS0424-E-00
2005/09
- 13 -
ASAHI KASEI
[AK4702EQ]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Serial Interface Timing
MS0424-E-00
2005/09
- 14 -
ASAHI KASEI
[AK4702EQ]
tPD
PDN
VIL
Power-down Timing
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
MS0424-E-00
2005/09
- 15 -
ASAHI KASEI
[AK4702EQ]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the DAC section of AK4702 are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 1 illustrates
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC section of AK4702 is in the normal operating mode (STBY bit = “0”). If these clocks are not provided, the AK4702
may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4702
should be reset by STBY = “0” after threse clocks are provided. If the external clocks are not present, place the AK4702
in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4702 remains in power-down mode
until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
256fs
384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 1. System clock example
„ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial
mode as shown in Table 2. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode
0
1
2
DIF1
0
0
1
DIF0
0
1
0
SDTI Format
16bit LSB Justified
18bit LSB Justified
18bit MSB Justified
3
1
1
18bit I2S Compatible
BICK
≥32fs
≥36fs
≥36fs
≥36fs or
32fs
Figure
Figure 3
Figure 3
Figure 4
Figure 5
Default
Table 2. Audio Data Formats
LRCK
BICK
SDTI
Mode 0
Don’t care
15 14
0
Don’t care
15
0
Don’t care
15 14
0
15
0
15:MSB, 0:LSB
SDTI
Mode 1
Don’t care
17
16
14
17
16
14
17:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 0,1 Timing
MS0424-E-00
2005/09
- 16 -
ASAHI KASEI
[AK4702EQ]
LRCK
BICK
SDTI
17 16
1
0
Don’t care
17 16
1
0
Don’t care
17
16
17:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 2 Timing
LRCK
BICK
SDTI
17 16
0
1
Don’t care
17 16
1
0
Don’t care
17
17:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 3 Timing
„ De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by the
DEM0 and DEM1 bits.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 3. De-emphasis filter control
MS0424-E-00
2005/09
- 17 -
ASAHI KASEI
[AK4702EQ]
„ Volume/Switch Control
The AK4702 has analog volume controls and switch matrixes designed primarily for SCART routing. Those are
controlled via the control register as shown in, Table 4, Table 5, Table 7 and Table 8. (Please refer to the block diagram in
figure 1.)
DVOL1
DVOL0
Gain
0
0
1
1
0
1
0
1
0dB
-6dB
2.44dB
(Reserved)
Output Level
(at volume#1=0dB)
2Vrms
1Vrms
2.65Vrms
(Reserved)
Table 4. Volume #0 (Digital Volume for DAC)
L5
L4
L3
L2
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
…
…
…
…
0
0
0
0
0
0
0
0
Note: Do not exceed 3Vrms as analog output.
L1
1
0
0
1
…
0
0
L0
0
1
0
1
…
1
0
Gain
+6dB
+4dB
+2dB
0dB (default)
…
-60dB
Mute
Table 5. Volume #1 (Analog Volume)
TV1
0
0
1
1
TV0
0
1
0
1
Source of TVOUTL/R
DAC
VCRIN (default)
Mute
(Reserved)
Table 6. TVOUT Switch Configuration
VOL
0
0
0
0
1
1
1
1
TV1
0
0
1
1
0
0
1
1
TV0
0
1
0
1
0
1
0
1
Source of MONOOUT
DAC (L+R)/2
Bypass the
DAC (L+R)/2
volume #1
DAC (L+R)/2
(Reserved)
DAC (L+R)/2
Through the
volume #1
VCRIN (L+R)/2
Mute
(Reserved)
Table 7. MONOOUT Switch Configuration
VCR1
0
0
1
1
VCR0
0
1
0
1
Source of VCROUTL/R
DAC
TVIN (default)
Mute
(Reserved)
Table 8. VCROUT Switch Configuration
MS0424-E-00
2005/09
- 18 -
ASAHI KASEI
[AK4702EQ]
„ Zero-cross Detection and Offset Calibration
To minimize the click noise when changing the gain of volume#1, the AK4702 has a zero-cross detection and an offset
calibration function.
1. Zero-cross detection function
When the ZERO bit = “1”, the zero-cross detection function is enabled. The gain of volume#1 changes at the first
zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within
the time set by ZTM1-0 bits (256/fs to 2048/fs). The zero-cross counter is initialized whenever a gain is issued. The
zero-cross is detected on L/R channels independently. To disable this function, set the ZERO bit to “0”.
ZERO: Zero-cross detection enable for volume#1
0
:
Disable. The volume value changes immediately without zero-cross.
1
:
Enable (default). The volume value changes at a zero-crossing point or when timeout (ZTM1-0 bit
setting) occurs.
The internal comparator for zero-cross detection has a small offset. Therefore, the gain of volume #1 may change due to
a zero-cross timeout before the comparator-based zero-cross detection occurs.
When the new gain value 1EH(-2dB) is written while the gain of both Lch and Rch are 1FH(0dB), if the Lch detects the
zero-cross prior to Rch, only the gain of Lch changes to 1EH(-2dB) while Rch waits for a zero-cross. After that, if the gain
is set to 1DH(-4dB) before either a zero-cross or zero-cross timeout, the Rch keeps the same value and changes from 1FH
to 1DH at next zero-cross or timeout.
WR[Gain=1EH]
WR[Gain=1DH]
Zero-cross
Gain Registers
1FH
Lch Gain
1FH
1DH
1EH
1DH
1EH
1DH
1FH
Rch Gain
Timer (256/fs to2048/fs)
zero-cross timer initialized
Timeout;
(may have click noise)
Figure 6. Zero-cross Operation (ZERO= “1”)
2. Offset calibration function
Offset calibration is enabled when the CAL bit = “1”. This function begins when the TVOUT source is switched to DAC
after the STBY bit is changed to “0”. It takes 1664/fs to execute the offset calibration cycle. During the offset calibration
cycle, the analog outputs are muted. Once the offset calibration is executed, the calibration memory is held until PDN=
“L” or the new calibration is executed. When the switch is changed from DAC to VCR during calibration, the calibration
is discontinued, and resumed when TVOUT is switched back to DAC. If volume#1 gain is changed during calibration, the
change takes place after calibration is complete.
„ Standby Mode
When the MUTE bit = “0” and the STBY bit = “1”, the AK4702 is forced into TV-VCR loop through mode. In this mode,
the sources of TVOUTL/R and MONOOUT are fixed to VCRINL/R, the sources of VCROUTL/R are fixed to TVINL/R
respectively. The gain of volume#1 is fixed to 0dB. Since all registers are NOT initialized by STBY= “1”, a register
switch configuration requires standby mode (STBY= “0”).
MS0424-E-00
2005/09
- 19 -
ASAHI KASEI
[AK4702EQ]
„ System Reset and Power-down control
The AK4702 should be reset once by bringing PDN = “L” upon power-up. The AK4702 has several power-down modes.
The PDN pin, MUTE bit and STBY bit control them as shown in Table 9 and Table 10.
PDN pin: Power down pin.
“H”: Normal operation
“L”: Device power down.
MUTE bit: Analog Mute bit.
“1”: Mute all analog outputs
“0”: Normal operation
STBY bit : Standby bit.
“1”: Standby mode, DAC is powered down, volume is fixed to 0dB, the analog audio/video paths are
fixed to TV-VCR loop-through.
“0”: Normal operation.
After when the PDN pin is set to “H”, the AK4702 is in standby mode and muted. To exit the mute and enter standby
mode, set the MUTE bit to “0” and the STBY bit to “1”. To use the DAC or change analog switches, set the STBY bit to
“0”. The DAC will power up and the internal timing starts clocking LRCK “↑” after exiting reset and power down states
by MCLK. The AK4702 is in power-down mode until MCLK and LRCK are input.
Mode
PDN pin
MUTE
bit
STBY
bit
MCLK,
BICK, LRCK
DAC
Powered
Down
Powered
Down
0
Device power-down
“L”
*
*
Not Needed
1
Standby and mute
(default)
“H”
1
1
Not Needed
2
Standby
“H”
0
1
Not Needed
Powered
Down
3
4
Mute
Normal operation
“H”
“H”
1
0
0
0
Needed
Needed
Active
Active
Analog
outputs
Register
control
GND
Not Available
GND
Available
fixed to
TV-VCR
loop-through
GND
Active
Available
Available
Available
Table 9. Power-down modes (audio)
Mode
PDN pin
STBY bit
Video outputs
TVFB,
TVSB
VCRSB
Hi-z
Hi-z
Internally pulled down by
120kohm(typ) resister
Active
Active
Active
Active
0
Power-down
“L”
*
1
Standby
“H”
1
2
Normal operation
“H”
0
Active
(Path is fixed)
Active
Table 10. Power-down modes (video)
MS0424-E-00
2005/09
- 20 -
ASAHI KASEI
[AK4702EQ]
The Figure 7 shows an example of the system timing at the power-down and power-up by PDN pin.
PDN pin
MUTE bit
STBY bit
“Stand-by“
“1” (default)
“Mute”
“0”
“Stand-by“
“1”
“1”
“0”
“1” (default)
“0”
“1”
Clock in
don’t care (2)
normal operation
don’t care (2)
Data in
don’t care
“0”
Audio data
GD
(1)
don’t care
“0”
GD (1)
D/A Out
(internal)
TV-Source
select
fixed to VCR in(Loop-through)
VCR in
(default)
DAC
VCR in
(4)
offset calibration
TV out
VCR in
VCR in
(3)
Notes:
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3) Please mute the analog outputs externally if click noise(3) adversely affects the system.
(4) In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUT is switched to
DAC after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”.
Figure 7. Power-down/up sequence example
MS0424-E-00
2005/09
- 21 -
ASAHI KASEI
[AK4702EQ]
„ Mode Control Interface
I2C-bus Control Mode
The AK4702 supports the standard-mode I2C-bus (max: 100kHz). Then AK4702 doesn’t support the fast-mode I2C-bus
system (max: 400kHz).
1. WRITE Operations
Figure 8 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 14). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4702, the AK4702 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 15). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4702. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 10). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 11). The AK4702 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 14).
The AK4702 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4702
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 08H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 16) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 8. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 9. The first byte
0
0
0
A4
A3
Figure 10. The second byte
D7
D6
D5
D4
D3
Figure 11. Byte structure after the second byte
MS0424-E-00
2005/09
- 22 -
ASAHI KASEI
[AK4702EQ]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of
each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If
the address exceeds 08H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be overwritten.
The AK4702 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4702 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4702 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4702
discontinues transmission
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 12. CURRENT ADDRESS READ
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition,
slave address(R/W=“0”) and then the register address to read. After the register’s address is acknowledge, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4702 generates an
acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4702 discontinues transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 13. RANDOM ADDRESS READ
MS0424-E-00
2005/09
- 23 -
ASAHI KASEI
[AK4702EQ]
SDA
SCL
S
P
start condition
stop condition
Figure 14. START and STOP conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 15. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 16. Bit transfer on the I2C-bus
MS0424-E-00
2005/09
- 24 -
ASAHI KASEI
[AK4702EQ]
„ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control
DEM1
DEM0
DIF1
DIF0
0
0
MUTE
STBY
01H
Switch
VMUTE
MMON
VCR1
VCR0
MONO
VOL
TV1
TV0
02H
Main Volume
0
0
L5
L4
L3
L2
L1
L0
03H
Zerocross
0
0
CAL
DVOL1
DVOL0
ZERO
ZTM1
ZTM0
04H
Video Switch
VRF1
VRF0
VVCR2
VVCR1
VVCR0
VTV2
VTV1
VTV0
05H
Video output enable
CIO
TVFB
VCRC
VCRV
TVB
TVG
TVR
TVV
06H
Video Volume/Clamp
0
VCLP1
VCLP0
0
CLAMP1
CLAMP0
VVOL1
VVOL0
07H
S/F Blanking control
SBIO1
SBIO0
SBV1
SBV0
SBT1
SBT0
FB1
FB0
08H
S/F Blanking monitor
0
0
0
0
0
FVCR
SVCR1
SVCR0
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN=“H”, all registers can be accessed.
Do not write any data to the register over 08H.
„ Register Definitions
Addr
Register Name
00H
Control
D7
D6
D5
D4
D3
D2
D1
DEM1
DEM0
DIF1
DIF0
0
0
MUTE
0
1
1
1
0
0
1
R/W
default
D0
STBY
R/W
1
STBY: Standby control
0
: Normal Operation
1
: Standby Mode(default). All registers are not initialized.
DAC
: powered down and timings are reset.
Gain of Volume#1
: fixed to 0dB,
Source of TVOUT
: fixed to VCRIN,
Source of VCROUT
: fixed to TVIN,
Source of MONOOUT : fixed to VCRIN,
Source of TVVOUT
: fixed to VCRVIN(or Hi-Z),
Source of TVRC
: fixed to VCRRC(or Hi-Z),
Source of TVG
: fixed to VCRG(or Hi-Z),
Source of TVB
: fixed to VCRB(or Hi-Z),
Source of VCRVOUT : fixed to TVVIN(or Hi-Z),
Source of VCRC
: fixed to Hi-Z or VSS(controlled by CIO bit).
MUTE: Audio output control
0
: Normal Operation
1
: ALL Audio outputs to GND (default)
DIF1-0: Audio data interface format control
00 : 16bit LSB Justified
01 : 18bit LSB Justified
10 : 18bit MSB Justified
11 : 18bit I2S Compatible (Default)
DEM1-0: De-emphasis Response Control
00 : 44.1kHz
01 : off (Default)
10 : 48kHz
11 : 32kHz
MS0424-E-00
2005/09
- 25 -
ASAHI KASEI
Addr
01H
Register Name
Switch
[AK4702EQ]
D7
D6
D5
D4
VMUTE
MMON
VCR1
VCR0
R/W
default
D3
D2
D1
D0
MONO
VOL
TV1
TV0
R/W
1
1
0
1
0
1
0
1
TV1-0: TVOUT source switch
00 : DAC
01 : VCRIN (Default)
10 : MUTE
11 : (Reserved)
VOL: Source select for MONOOUT
0
: Bypass the volume (fixed to DAC out)
1
: Through the volume (Default)
MONO: Mono select for TVOUT
0
: Stereo. (Default)
1
: Mono. (L+R)/2
VCR1-0: VCROUT source switch
00 : DAC
01 : TVIN (Default)
10 : MUTE
11 : (Reserved)
MMON: Mute of MONOIN input
0
: Add the MONOIN
1
: Mute the MONOIN (default)
VMUTE: Mute switch for volume#1
0
: Normal operation
1
: Mute the volume#1 (Default)
Addr
Register Name
02H
Main Volume
D7
D6
D5
D4
D3
D2
D1
D0
0
0
L5
L4
L3
L2
L1
L0
1
1
1
1
R/W
default
R/W
0
0
0
1
L5-0: Volume#1 control
Those registers control both Lch and Rch of Volume#1.
111111 to
100011 : (Reserved)
100010
: Volume gain = +6dB
100001
: Volume gain = +4dB
100000
: Volume gain = +2dB
011111
: Volume gain = +0dB (default)
011110
: Volume gain = -2dB
...
000011
: Volume gain = -56dB
000010
: Volume gain = -58dB
000001
: Volume gain = -60dB
000000
: Volume gain = Mute
MS0424-E-00
2005/09
- 26 -
ASAHI KASEI
Addr
Register Name
03H
Zerocross
[AK4702EQ]
D7
D6
D5
D4
0
0
CAL
DVOL1
R/W
default
D3
D2
D1
D0
DVOL0
ZERO
ZTM1
ZTM0
0
1
1
1
R/W
0
0
1
0
ZTM1-0: The time length control of zero-cross timeout
00 : typ. 256/fs
01 :
512/fs
10 :
1024/fs
11 :
2048/fs (default)
ZERO: Zero-cross detection enable for volume control#1
0
: Disable
The volume value changes immediately without zero-cross.
1
: Enable (default)
The volume value changes when timeout or zero-cross before timeout.
This function is disabled when STBY= “1”.
DVOL1-0: Digital volume control for DAC (Volume#0)
00 : 0dB
01 : -6dB
10 : +2.44dB
11 : (Reserved)
CAL: Offset calibration Enable
0
: Offset calibration disable.
1
: Offset calibration enable(default)
MS0424-E-00
2005/09
- 27 -
ASAHI KASEI
[AK4702EQ]
Addr
Register Name
04H
Video Switch
R/W
default
D7
D6
D5
D4
VRF1
VRF0
VVCR2
VVCR1
D3
D2
D1
D0
VVCR0
VTV2
VTV1
VTV0
1
0
0
R/W
1
0
0
1
1
VTV0-2: selector for TV video output
Mode
VTV2-0
TVVOUT
TVRC
TVG
Shutdown
000
Hi-Z
Hi-Z
Hi-Z
Encoder CVBS
Encoder R
Encoder G
Encoder CVBS
001
ENCV
ENCRC
ENCG
or RGB
Encoder
Encoder
Encoder Y/C 1
010
Luminance
Chrominance
Hi-Z
ENCV
ENCRC
Encoder
Encoder
Encoder Y/C 2
011
Luminance
Chrominance
Hi-Z
ENCY
ENCC
VCR
VCR CVBS/Y
VCR R/C
VCR G
100
(default)
VCRVIN
VCRRC
VCRG
TV CVBS/Y
Hi-Z
Hi-Z
TV CVBS
101
TVVIN
(reserved)
110
(reserved)
111
Table 11. TV video output (see note)
TVB
Hi-Z
Encoder B
ENCB
Hi-Z
Hi-Z
VCR B
VCRB
Hi-Z
-
VVCR0-2: selector for VCR video output
Mode
VVCR2-0
Shutdown
000
Encoder CVBS
001
or Y/C 1
Encoder CVBS
010
or Y/C 2
TV CVBS
011
(default)
VCR
100
(reserved)
(reserved)
(reserved)
101
110
111
VCRVOUT
VCRC
Hi-Z
Hi-Z
Encoder CVBS/Y
Encoder Chrominance
ENCV
ENCRC
Encoder CVBS/Y
Encoder Chrominance
ENCY
ENCC
TV CVBS
Hi-Z
TVVIN
VCR CVBS/Y
VCR R/C
VCRVIN
VCRRC
Table 12. VCR video output (see note)
VRF0-1: selector for RF video output
Mode
Encoder
CVBS1
Encoder
CVBS2
VCR
(default)
Shutdown
VRF1-0
RF CVBS
Encoder CVBS1
ENCV
Encoder CVBS2
ENCG (Note: 22)
VCR
VCRVIN
Hi-Z
00
01
10
11
Table 13. RF video output (see note)
Note: 21: When input the video signal via ENCRC or VCRRC pin, set CLAMP1-0 bits respectively.
Note: 22 When VTV2-0=“001”, TVG=“1” and VRF1-0=“01”, RFV output is same as TVG (Encoder G).
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ASAHI KASEI
[AK4702EQ]
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
05H
output enable
CIO
TVFB
VCRC
VCRV
TVB
TVG
TVR
TVV
0
0
0
0
0
0
0
0
R/W
default
R/W
Each video outputs can be set to Hi-Z individually.
TVV : TVVOUT output control
TVR : TVRCOUT output control
TVG : TVGOUT output control
TVB : TVBOUT output control
VCRV : VCRVOUT output control
VCRC : VCRC output control
TVFB : TVFB output control
0
: Hi-Z (default)
1
: Active.
When CIO= “1”, the VCRC pin is connected to GND even if VCRC= “0”.
When CIO= “0”, the VCRC pin follows the setting of VCRC bit.
CIO: VCR Chrominance I/O control
0
: Active (output).
1
: Connected to GND
CIO
0
0
1
1
VCRC
State of VCRC pin
0
Hi-z (default)
1
Active
0
Connected to GND
1
Connected to GND
Table 14 VCRC output control
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ASAHI KASEI
[AK4702EQ]
Addr
Register Name
D7
D6
D5
D4
06H
Video Volume
0
VCLP1
VCLP0
0
R/W
default
D3
D2
D1
D0
CLAMP1
CLAMP0
VVOL1
VVOL0
0
1
0
0
R/W
0
0
0
0
VVOL1-0: RGB video gain control
VVOL1
0
0
1
1
VVOL0
0
1
0
1
Gain
Output level (Typ. @Input=0.7Vpp)
+6dB
1.4Vpp (default)
+7.2dB
1.6Vpp
+8.2dB
1.8Vpp
+9.1dB
2.0Vpp
Table 15. RGB gain
CLAMP1 : Encoder R/Chroma (ENCRC pin)input clamp control
0
: DC restore clamp active (for RED signal. default)
1
: Biased (for Chroma signal.)
CLAMP0 : VCR R/C (VCRC pin)input clamp control
0
: DC restore clamp active (for RED signal)
1
: Biased (for Chroma signal. default.)
VCLP1-0 : DC restore source control
VCLP1
0
0
1
1
VCLP0
Sync Source of DC Restore
0
ENCV (default)
1
ENCY
0
VCRVIN
1
(Reserved)
Table 16. DC restore source control
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ASAHI KASEI
[AK4702EQ]
Addr
Register Name
07H
S/F Blanking
D7
D6
D5
D4
SBIO1
SBIO0
SBV1
SBV0
R/W
default
D3
D2
D1
D0
SBT1
SBT0
FB1
FB0
0
0
0
0
R/W
0
0
0
0
FB1-0: TV Fast Blanking output control (for TVFB)
FB1
0
0
1
1
FB0
0
1
0
1
TV FB Output Level
0V (default)
4V
Same as VCR FB input (4V/0V)
(Reserved)
(note: minimum load is 150ohm)
Table 17. TV Fast Blanking output
SBT1-0: TV Slow Blanking output control (for TVSB)
SBT1-0 do not work correctly when VP<11.4V
SBT1
0
0
1
1
SBT0
0
1
0
1
Slow Blanking Output Level
<2V (default)
5V<, <7V
(Reserved)
10V<
(note: minimum load is 10kohm)
Table 18. TV Slow Blanking output
SBV1-0: VCR Slow Blanking output control (for VCRSB)
SBV1-0 do not work correctly when VP<11.4V
SBV1
0
0
1
1
SBV0
0
1
0
1
Slow Blanking Output Level
<2V (default)
5V<, <7V
(Reserved)
10V<
(note: minimum load is 10kohm)
Table 19. VCR Slow Blanking output
SBIO1-0: TV/VCR Slow Blanking I/O control
SBIO1-0 do not work correctly when VP<11.4V
SBIO1
SBIO0
0
0
0
1
1
0
1
1
VCR Slow Blanking Direction TV Slow Blanking Direction
Output
Output
(Controlled by SBV1,0)
(Controlled by SBT1,0)
(Reserved)
(Reserved)
Input
Output
(Stored in SVCR1,0)
(Controlled by SBT1,0)
Input
Output
(Stored in SVCR1,0)
(Same output as VCR SB)
Table 20. TV/VCR Slow Blanking output
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(default)
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ASAHI KASEI
Addr
Register Name
08H
SB/FB Monitor
R/W
default
[AK4702EQ]
D7
D6
D5
D4
0
0
0
0
D3
D2
D1
D0
0
FVCR
SVCR1
SVCR0
0
0
0
0
READ
0
0
0
0
SVCR1-0: VCR Slow blanking status monitor
Those bits reflect the voltage at VCRSB pin for both Input/Output modes
SVCR1-0 do not work correctly when VP<11.4V
SVCR1 SVCR0
VCRSB Level
0
0
< 2V
0
1
4.5 to 7V
1
0
(Reserved)
1
1
9.5<
Table 21. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is enabled when TVFB bit = “1”.
FVCR
VCRFB Input Level
0
<0.4V
1
1 V<
Table 22. VCR Fast Blanking monitor (Typical threshold is 0.7V)
Changes to the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes “L” for
2usec(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resister.
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ASAHI KASEI
[AK4702EQ]
SYSTEM DESIGN
RFV
MONOOUT
CVBS
Audio MONO
RF Mod
Phono
TVOUTL
TVOUTR
TVRC
TVG
TVB
TVFB
TVVOUT
CVBS/Y
Y
C
Encoder
R/C
G/CVBS
B
TVVIN
ENCV
TVINL
ENCY
TVINR
ENCC
TVSB
ENCRC
ENCGV
VCRFB
ENCB
VCRVIN
MCLK
MPEG
BICK
Decoder
LRCK
SDATA
VCRRC
MCLK
Processor
SCK
SDA
PDN
Interrupt
Audio R
R/C
G
B
Fast Blank
TV SCART
Y/CVBS
Y/CVBS
Audio L
Audio R
Slow Blank
Fast Blank
Y/CVBS
R/C
VCRC
BICK
VCRG
LRCK
VCRB
SDATA
VCRINL
Micro
Audio L
VCRINR
VCRVOUT
SCK
SDA
VCROUTL
PDN
VCROUTR
INT
VCRSB
G
B
VCR SCART
Audio L
Audio R
Y/CVBS
Audio L
Audio R
Slow Blank
Figure 17. Typical Connection Diagram
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ASAHI KASEI
[AK4702EQ]
1. Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit and be separated from system digital
supply. Decoupling capacitor, especially the 0.1µF ceramic capacitor for high frequency noise should be placed as near to
VD (VP, VVD1, VVD2) as possible.
2. Voltage Reference
Each VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from VCOM pins in order to avoid unwanted coupling into the AK4702.
3. Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(Typ.). The output signal range is typically 2Vrms
([email protected]=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio pass band. Therefore, any external filters are not required for typical application.
The output voltage is a positive full scale for 7FFFFFH (@18bit) and a negative full scale for 800000H (@18bit). The
ideal output is 5.6V(Typ.) for 000000H (@18bit). The DC voltage on analog outputs are eliminated by AC coupling.
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ASAHI KASEI
[AK4702EQ]
4. External Circuit Example
Analog Audio Input pin
300ohm
MONOIN
TVINL/R
VCRINL/R
0.47µF
(Cable)
Analog Audio Output pin
MONOOUT
TVOUTL/R
VCROUTL/R
300ohm
10µF
(Cable)
Total > 4.5kohm
Analog Video Input pin
75ohm
(Cable)
ENCV, ENCY, VCRVIN,
TVVIN, ENCRC, ENCC,
VCRRC, ENCG, VCRG,
ENCB, VCRB
0.1µF
75ohm
Analog Video Output pin (Except RFV pin)
75ohm
TVVOUT, TVRC
TVG, TVR
VCRVOUT, VCRC
(Cable)
max
15pF
max
400pF
75ohm
Analog Video Output pin (RFV pin)
The AK4702 does not have 75ohm driver. Please use an external buffer if the input impedance of the
RF modulator is less than 20kohm.
Buffer
Zin>20kohm
RFV
RF Modulator
Max 15pF
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ASAHI KASEI
[AK4702EQ]
Slow Blanking pin
TVSB
VCRSB
(Cable)
400ohm
(max 500ohm)
max 3nF
(with 400ohm)
min: 10k ohm
Fast Blanking Input pin
VCRFB
75ohm
(Cable)
75ohm
Fast Blanking Output pin
75ohm
TVFB
(Cable)
75ohm
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ASAHI KASEI
[AK4702EQ]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.145 ± 0.05
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.5 ± 0.2
0.10
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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ASAHI KASEI
[AK4702EQ]
MARKING
AK4702EQ
XXXXXXX
1
XXXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD)
05/09/20
Revision
00
Reason
First Edition
Page
MS0424-E-00
Contents
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ASAHI KASEI
[AK4702EQ]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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