AKM AKD4366

ASAHI KASEI
[AK4366]
AK4366
Low Power 24-Bit 2ch DAC with HP-AMP
GENERAL DESCRIPTION
The AK4366 is 24bit DAC with built-in Headphone Amplifier. The integrated headphone amplifier features
“pop-free” power-on/off, a mute control and delivers 50mW of power at 16Ω. The AK4366 is housed in a
16pin TSSOP package, making it suitable for portable applications.
FEATURE
† Multi-bit ∆Σ DAC
† Sampling Rate: 8kHz∼48kHz
† 64x Oversampling
† On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
† Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
† System Clock: 256fs/384fs/512fs
- AC Couple Input Available
† Audio I/F Format: MSB First, 2’s Compliment
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
† µP Interface: 3-wire
† Bass Boost Function
† Headphone Amplifier
- Output Power: 50mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
- Pop noise Free at Power-ON/OFF and Mute
† Power Supply: 2.2V ∼ 3.6V
† Power Supply Current: [email protected] (@HP-AMP no-output)
† Ta: −40 ∼ 85°C
† Small Package: 16pin TSSOP
MS0248-E-01
2004/03
-1-
ASAHI KASEI
[AK4366]
VDD
MCLK
BICK
LRCK
SDATA
Audio
Interface
Clock
Divider
VCOM
VCOM
DAC
(Lch)
ATT
&
Bass
Boost
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
DEM
&
Digital
Filter
DAC
(Rch)
PDN
HVDD
P/S
DIF0/CSN
DEM/CCLK
MUTET
Serial I/F
MUTEN /CDTI
VSS
Figure 1. AK4366 Block Diagram
MS0248-E-01
2004/03
-2-
ASAHI KASEI
[AK4366]
„ Ordering Guide
AK4366VT
AKD4366
−40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation board for AK4366
„ Pin Layout
MUTEN/CDTI
1
16
HPL
DEM/CCLK
2
15
HPR
DIF0/CSN
3
14
HVDD
SDATA
4
13
VSS
12
VDD
Top View
LRCK
5
BICK
6
11
MUTET
MCLK
7
10
VCOM
PDN
8
9
MS0248-E-01
P/S
2004/03
-3-
ASAHI KASEI
[AK4366]
PIN/FUNCTION
No.
Pin Name
I/O
MUTEN
I
CDTI
I
DEM
I
CCLK
I
DIF0
I
4
CSN
SDATA
I
I
5
LRCK
I
6
BICK
I
7
MCLK
I
8
PDN
I
9
P/S
I
10
VCOM
O
11
MUTET
O
12
13
14
15
16
VDD
VSS
HVDD
HPR
HPL
O
O
1
2
3
Function
Headphone Amp Mute Pin (P/S pin = “H”)
“H”: Normal operation, “L”: Mute
Control Data Input Pin (P/S pin = “L”)
De-emphasis Pin (P/S pin = “H”)
“H”: ON(44.1kHz), “L”: OFF
Control Data Clock Pin (P/S pin = “L”)
Audio Interface Format Pin (P/S pin = “H”)
“H”: I2S, “L”: 24bit MSB justified
Control Data Chip Select Pin (P/S pin = “L”)
Audio Serial Data Input Pin
L/R Clock Pin
This clock determines which audio channel is currently being input on SDATA pin.
Serial Bit Clock Pin
This clock is used to latch audio data.
Master Clock Input Pin
Power-down & Reset Pin
When at “L”, the AK4366 is in power-down mode and is held in reset.
The AK4366 should always be reset upon power-up.
Control Mode Select Pin (Internal Pull-down Pin)
“H”: Parallel, “L”: 3-wire Serial
Common Voltage Output Pin
Normally connected to VSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF
electrolytic capacitor.
Mute Time Constant Control Pin
Connected to VSS pin with a capacitor for mute time constant.
Power Supply Pin
Ground Pin
Power Supply Pin for Headphone Amp
Rch Headphone Amp Output Pin
Lch Headphone Amp Output Pin
Note: All digital input pins except internal pull-down pin must not be left floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MUTET, HPR, HPL
DEM, DIF0
Setting
These pins should be open.
These pins should be connected to VSS.
MS0248-E-01
2004/03
-4-
ASAHI KASEI
[AK4366]
ABSOLUATE MAXIMUM RATING
(VSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies Analog, Digital
VDD
−0.3
HP-AMP
HVDD
−0.3
Input Current (any pins except for supplies)
IIN
Input Voltage
VIN
−0.3
Ambient Temperature
Ta
−40
Storage Temperature
Tstg
−65
Note 1. All voltages with respect to ground.
max
4.6
4.6
±10
VDD+0.3 or 4.6
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies Analog, Digital
VDD
2.2
2.4
(Note 2)
HP-AMP
HVDD
2.2
2.4
Note 1. All voltages with respect to ground.
Note 2. VDD should be same voltage as HVDD.
max
3.6
3.6
Units
V
V
* AKM assumes no responsibility for usage beyond the conditions in this datasheet.
MS0248-E-01
2004/03
-5-
ASAHI KASEI
[AK4366]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=HVDD=2.4V, VSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band
width=10Hz ∼ 20kHz; Load impedance is a serial connection with RL =16Ω and CL=220µF. (Refer to Figure 19); unless
otherwise specified)
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 3)
Analog Output Characteristics
THD+N (−4.8dBFS Output, [email protected], 2.4V)
dB
−55
−45
dB
(−3dBFS Output, [email protected], 3.3V)
−55
dB
(−3dBFS Output, [email protected], 3.3V)
−57
D-Range (−60dBFS Output, A-weighted, 2.4V)
84
92
dB
94
dB
(−60dBFS Output, A-weighted, 3.3V)
S/N
(A-weighted, 2.4V)
84
92
dB
(A-weighted, 3.3V)
94
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
dB
Gain Drift
200
ppm/°C
Load Resistance
(Note 4)
16
Ω
Load Capacitance
300
pF
Output Voltage
(Note 5)
1.02
1.13
1.24
Vpp
(−4.8dBFS Output)
Max Output Power
26
mW
(RL=16Ω, 2.4V)
50
mW
(RL=16Ω, 3.3V)
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 6)
VDD
1.6
2.8
mA
HVDD
1.0
2.0
mA
Power-Down Mode (PDN pin = “L”)
(Note 7)
1
100
µA
Note 3. DACL=DACR= “1”, ATTL=ATTR=0dB.
Note 4. AC Load
Note 5. Output voltage is proportional to VDD voltage. Vout = 0.47 x VDD(typ)@−4.8dBFS.
Note 6. PMDAC=PMHPL=PMHPR= “1”, MUTEN= “1” and HP-Amp output is off.
Note 7. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at VSS.
MS0248-E-01
2004/03
-6-
ASAHI KASEI
[AK4366]
FILTER CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter: (Note 8)
Passband
PB
0
20.0
kHz
−0.05dB (Note 9)
22.05
kHz
−6.0dB
Stopband
(Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 10)
GD
20.8
1/fs
Group Delay Distortion
0
µs
∆GD
DAC Digital Filter + Analog Filter: (Note 8) (Note 11)
Frequency Response
FR
dB
0 ∼ 20.0kHz
±0.5
BOOST Filter:
(Note 11) (Note 12)
Frequency Response
20Hz
FR
dB
5.76
MIN
100Hz
dB
2.92
1kHz
dB
0.02
20Hz
FR
dB
10.80
MID
100Hz
dB
6.84
1kHz
dB
0.13
20Hz
FR
dB
16.06
MAX 100Hz
dB
10.54
1kHz
dB
0.37
Note 8. BOOST OFF (BST1-0 bit = “00”)
Note 9. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB).
Note 10. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 24bit
data of both channels to the input registers to the output of the analog signal.
Note 11. DAC Æ HPL, HPR
Note 12. These frequency responses scale with fs. If high-level signal is input, the AK4366 clips at low frequency.
Boost Filter (fs=44.1kHz)
20
MAX
Level [dB]
15
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0248-E-01
2004/03
-7-
ASAHI KASEI
[AK4366]
DC CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
Input Voltage at AC Coupling
(Note 13)
VAC
1.0
Input Leakage Current
(Note 14)
Iin
Note 13. Only MCLK pin. (Figure 19)
Note 14. P/S pin has internal pull-down device, nominally 100kΩ.
typ
-
max
30%DVDD
±10
Units
V
V
Vpp
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
2.048
24.576
MHz
Pulse Width Low
(Note 15)
tCLKL
0.4/fCLK
ns
Pulse Width High
(Note 15)
tCLKH
0.4/fCLK
ns
AC Pulse Width
(Note 18)
tACW
20
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle:
Duty
45
55
%
Serial Interface Timing (Note 16)
BICK Period
tBCK
1/(64fs)
ns
BICK Pulse Width Low
tBCKL
130
ns
Pulse Width High
tBCKH
130
ns
(Note 17)
tLRB
50
ns
LRCK Edge to BICK “↑”
(Note 17)
tBLR
50
ns
BICK “↑” to LRCK Edge
SDATA Hold Time
tSDH
50
ns
SDATA Setup Time
tSDS
50
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
tCSS
50
ns
CSN “↑” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
Note 15. Except AC coupling.
Note 16. Refer to “Serial Data Interface”.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
MS0248-E-01
2004/03
-8-
ASAHI KASEI
[AK4366]
„ Timing Diagram
1/fCLK
tACW
1000pF
MCLK Input
tACW
Measurement Point
VAC
100kΩ
VSS
VSS
Figure 3. MCLK AC Coupling Timing
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 4. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing
MS0248-E-01
2004/03
-9-
ASAHI KASEI
[AK4366]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 6. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 7. WRITE Data Input Timing
tPD
PDN
VIL
Figure 8. Power-down & Reset Timing
MS0248-E-01
2004/03
- 10 -
ASAHI KASEI
[AK4366]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4366 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
MCLK (MHz)
256fs
384fs
512fs
2.048
3.072
4.096
2.8224
4.2336
5.6448
3.072
4.608
6.144
4.096
6.144
8.192
5.6448
8.4672
11.2896
6.144
9.216
12.288
8.192
12.288
16.384
11.2896
16.9344
22.5792
12.288
18.432
24.576
Table 1. System Clock Example
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
In serial mode (P/S pin = “L”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is
input with AC coupling, the MCKAC bit should be set to “1”.
In parallel mode (P/S pin = “H”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PDN pin = “L”).
For low sampling rates, DR and S/N degrade because of the outband noise. In serial mode (P/S pin = “L”), DR and S/N
are improved by setting DFS1 bit to “1”. Table 2 shows S/N of HP-amp output. When the DFS1 bit is “1”, MCLK needs
512fs.
DFS1
DFS0
0
0
1
0
1
x
S/N (fs=8kHz, A-weighted)
Over Sample
fs
MCLK
Rate
HP-amp
64fs
256fs/384fs/512fs
56dB
8kHz∼48kHz
128fs
256fs/384fs/512fs
75dB
8kHz∼24kHz
256fs
512fs
92dB
8kHz∼12kHz
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp
MS0248-E-01
Default
2004/03
- 11 -
ASAHI KASEI
[AK4366]
„ Serial Data Interface
The AK4366 interfaces with external system via the SDATA, BICK and LRCK pins. In serial mode (P/S pin = “L”), five
data formats are available and are selected by setting DIF2, DIF1 and DIF0 bits (Table 3). In parallel mode (P/S pin =
“H”), two data formats are available and are selected by setting DIF0 pin (Table 3). Mode 0 is compatible with existing
16bit DACs and digital filters. Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is
similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and
3 with BICK≥48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit
data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.
DIF2 bit
0
0
0
0
1
DIF1 bit
0
0
1
1
0
DIF0 bit
0
1
0
1
0
MODE
BICK
0: 16bit, LSB justified
32fs ≤ BICK ≤ 64fs
1: 20bit, LSB justified
40fs ≤ BICK ≤ 64fs
2: 24bit, MSB justified
48fs ≤ BICK ≤ 64fs
3: I2S Compatible
BICK=32fs or 48fs ≤ BICK ≤ 64fs
4: 24bit, LSB justified
48fs ≤ BICK ≤ 64fs
Table 3. Audio Data Format (Serial Mode)
DIF0 pin
L
H
MODE
BICK
2: 24bit, MSB justified
48fs ≤ BICK ≤ 64fs
3: I2S Compatible
BICK=32fs or 48fs ≤ BICK ≤ 64fs
Table 4. Audio Data Format (Parallel Mode)
Figure
Figure 9
Figure 10
Figure 11
Figure 12
Figure 10
Figure
Figure 11
Figure 12
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
15
14
1
0
15
14
BICK
SDATA
Mode 0
Don’t care
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 0 Timing
MS0248-E-01
2004/03
- 12 -
ASAHI KASEI
[AK4366]
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 1, 4 Timing
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 11. Mode 2 Timing
MS0248-E-01
2004/03
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ASAHI KASEI
[AK4366]
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
24bit
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
BICK
(32fs)
SDATA
16bit
0
1
0
0
15
Figure 12. Mode 3 Timing
MS0248-E-01
2004/03
- 14 -
ASAHI KASEI
[AK4366]
„ Digital Attenuator
The AK4366 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before
the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 5). At
DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control
the Lch level and ATTR7-0 bits control the Rch level. In parallel mode (P/S pin = “H”), digital attenuator is fixed to 0dB.
When HPM bit = “1”, (L+R)/2 summation is done after volume control.
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
Default
MUTE (−∞)
Table 5. Digital Volume ATT values
The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 6). When ATS
bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs ([email protected]=44.1kHz) from
FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs
fade to their current value. Digital attenuator is independent of the soft mute function.
ATT speed
0dB to MUTE
1 step
0
1061/fs
4/fs
Default
1
7424/fs
29/fs
Table 6. Transition time between set values of ATT7-0 bits
ATS
MS0248-E-01
2004/03
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ASAHI KASEI
[AK4366]
„ Soft Mute
Soft mute operation is performed at digital domain. In serial mode (P/S pin = “L”), when the SMUTE bit goes to “1”, the
output signal is attenuated by −∞ during ATT_DATA×ATT transition time (Table 6) from the current ATT level. When
the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level
during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to −∞ after starting the
operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission. In parallel mode (P/S pin = “H”), soft mute is not
available.
SMUTE bit
ATT Level
ATS bit
ATS bit
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 13. Soft Mute Function
Notes:
(1) ATT_DATA×ATT transition time (Table 6). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit =
“1” and ATT_DATA = “128”.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
MS0248-E-01
2004/03
- 16 -
ASAHI KASEI
[AK4366]
„ De-emphasis Filter
The AK4366 includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies
(32kHz, 44.1kHz and 48kHz). In serial mode (P/S pin = “L”), the de-emphasis filter is enabled by setting DEM1-0 bits
(Table 7).
DEM1 bit
DEM0 bit
De-emphasis
0
0
44.1kHz
0
1
OFF
Default
1
0
48kHz
1
1
32kHz
Table 7. De-emphasis Filter Frequency Select (Serial Mode)
In parallel mode (P/S pin = “H”), the de-emphasis filter corresponding to 44.1kHz is enabled by setting DEM pin “H”
(Table 8).
DEM pin
De-emphasis
L
OFF
H
44.1kHz
Table 8. De-emphasis Filter Frequency Select (Parallel Mode)
„ Bass Boost Function
In serial mode (P/S pin = “L”), the low frequency boost signal can be output from DAC by controlling BST1-0 bits (Table
9). The setting value is common in Lch and Rch.
BST1 bit
BST0 bit
BOOST
0
0
OFF
0
1
MIN
1
0
MID
1
1
MAX
Table 9. Low Frequency Boost Select
Default
„ System Reset
The AK4366 should be reset once by bringing PDN “L” upon power-up.
In serial mode (P/S pin = “L”), after exiting reset, VCOM, DAC, HPL and HPR switch to the power-down state. The
contents of the control register are maintained until the reset is done. DAC exits reset and power down state by MCLK
after PMDAC bit is changed to “1”, and then DAC is powered up and the internal timing starts clocking by LRCK “↑”.
DAC is in power-down mode until MCLK and LRCK are input.
In parallel mode (P/S pin = “H”), VCOM and DAC are powered up by PDN pin “H”. Headphone amp is powered up by
MUTEN pin “H”. DAC exits reset and power down state by MCLK after PDN pin goes to “H”, and then DAC is powered
up and the internal timing starts clocking by LRCK “↑”. DAC is in power-down mode until MCLK and LRCK are input.
MS0248-E-01
2004/03
- 17 -
ASAHI KASEI
[AK4366]
„ Headphone Output
Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the 0.45 x VDD voltage.
The Headphone-amp output load resistance is min.16Ω.
1) Parallel mode (P/S pin = “H”)
When MUTEN pin is set to “H” at PDN pin = “H”, common voltage goes to 0.45 x VDD. When MUTEN pin is set to “L”,
common voltage goes to VSS, and the outputs (HPL and HPR pins) are VSS. When PDN pin is “L”, headphone
amplifiers are powered-down perfectly, and the outputs (HPL and HPR pins) are VSS.
2) Serial mode (P/S pin = “L”)
When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the common voltage rises to 0.45 x VDD. When the MUTEN bit
is “0”, the common voltage of Headphone-amp falls and the outputs (HPL and HPR pins) go to VSS. When PMHPL and
PMHPR bits are “0”, the Headphone-amps are powered-down perfectly, and the outputs (HPL and HPR pins) are VSS.
A capacitor between the MUTET pin and ground reduces pop noise at power-up/down. It is
recommended that the capacitor with small variation of capacitance and low ESR (Equivalent Series
Resistance) over all temperature range, since the rise and fall time in Table 10 depend on the
capacitance and ESR of the external capacitor at MUTET pin.
tr: Rise Time up to VCOM/2
100k x C (typ)
tf: Fall Time down to 0V
200k x C (typ)
Table 10. Headphone-Amp Rise/Fall Time
[Example] : A capacitor between the MUTET pin and ground = 1.0µF:
Time constant of rise time: tr = 100kΩ x 1µF = 100ms(typ)
Time constant of fall time: tf = 200kΩ x 1µF = 200ms(typ)
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 14. Power-up/Power-down Timing for Headphone-amp
(1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still VSS.
(2) Headphone-amp common voltage rise up (MUTEN bit = “1”). Common voltage of Headphone-amp is rising. This rise
time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is tr = 100k x C(typ)
when the capacitor value on MUTET pin is “C”.
(3) Headphone-amp common voltage fall down (MUTEN bit = “0”). Common voltage of Headphone-amp is falling to
VSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to 0V is tf =
200k x C(typ) when the capacitor value on MUTET pin is “C”.
(4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are VSS. If the power supply is switched off
or Headphone-amp is powered-down before the common voltage goes to VSS, some pop noise occurs.
MS0248-E-01
2004/03
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ASAHI KASEI
[AK4366]
The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 11 shows the
cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 2.4, 3.0 and 3.3V. The output voltage of headphone is 0.47 x VDD (Vpp)
@−4.8dBFS.
HP-AMP
R
C
Headphone
16Ω
AK4366
Figure 15. External Circuit Example of Headphone
R [Ω]
0
6.8
16
Output Power [mW]
fc [Hz]
fc [Hz]
BOOST=OFF
BOOST=MIN
2.4V
3.0V
3.3V
220
45
17
15
24
28
100
100
43
100
70
28
7
12
14
47
149
78
100
50
19
4
6
7
47
106
47
Table 11. Relationship of external circuit, output power and frequency response
C [µF]
MS0248-E-01
2004/03
- 19 -
ASAHI KASEI
[AK4366]
„ Power-Up/Down Sequence
1) Parallel mode (P/S pin = “H”)
Power Supply
(7)
(1)
>150ns
PDN pin
Don’t care
(2)
Clock Input
DAC Internal
State
Don’t care
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
MUTEN pin
(3) >2ms
(3) >2ms
(4)
(6) GD
(6)
(5)
(4)
(6) GD
(6)
(5)
HPL/R pin
Figure 16. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PDN pin = “L”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(3) MUTEN pin should be set to “H” at least 2ms after PDN pin goes to “H”.
(4) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
tr = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(5) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is tf =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PDN pin should be set to “L” after HPL and HPR pins go to VSS.
(6) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs (=472µ[email protected]=44.1kHz).
(7) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
MS0248-E-01
2004/03
- 20 -
ASAHI KASEI
[AK4366]
2) Serial mode (P/S pin = “L”)
Power Supply
(9)
(1)
>150ns
PDN pin
Don’t care
(2) >0
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
Normal Operation
PD
PD
Normal Operation
PD
SDTI pin
DACL, DACR bit
(4) >0
PMHPL,
PMHPR bit
(4) >0
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bit
(8) GD
(6)
00H(MUTE)
FFH(0dB)
00H(MUTE)
(9) 1061/fs (8)
FFH(0dB)
(9)
(8)
(7)
(9)
(6)
00H(MUTE)
(8)
(9)
(7)
HPL/R pin
Figure 17. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes to “H”.
(3) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(4) DACL and DACR bits should be changed to “1” after PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2µF) after DACL and DACR bits are changed to “1”.
(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
tr = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is tf =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PMHPL, PMHPR, DACL and DACR bits should be changed to “0” after HPL and HPR pins go to VSS.
(8) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µ[email protected]=44.1kHz).
(9) ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
(10) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
MS0248-E-01
2004/03
- 21 -
ASAHI KASEI
[AK4366]
„ Mode Control Interface
Some function of AK4366 can be controlled by both pins (parallel control mode) and register (serial control mode) shown
in Table 12. The serial control interface is enabled by the P/S pin = “L”. Internal registers may be written by 3-wire µP
interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, fixed to “01”),
Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits).
AK4366 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data
becomes valid by 16th CCLK “↑”. The clock speed of CCLK is 5MHz (max).
Function
De-emphasis
SMUTE
Audio I/F Format
Digital Attenuator
Bass Boost
Power Management
Default State at PDN pin = “L” → “H”
Parallel mode
44.1kHz
Not Available
I2S, Left justified
Not Available
Not Available
Not Available
Power up
Serial mode
32kHz/44.1kHz/48kHz
Available
I2S, Left Justified, Right justified
Available
Available
Available
Power down
Table 12. Function List
PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, AK4366 should be reset
by PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 18. 3-wire Serial Control I/F Timing
MS0248-E-01
2004/03
- 22 -
ASAHI KASEI
[AK4366]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
Register Name
Power Management
Mode Control 0
Mode Control 1
Mode Control 2
DAC Lch ATT
DAC Rch ATT
Output Select
D7
0
0
0
0
ATTL7
ATTR7
0
D6
0
MCKAC
0
0
ATTL6
ATTR6
0
D5
0
HPM
0
0
ATTL5
ATTR5
0
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMHPL
PMDAC
PMVCM
DIF2
DIF1
BST1
ATS
ATTL3
ATTR3
0
DIF0
BST0
DFS1
DEM1
BCKP
ATTL1
ATTR1
DACR
DFS0
DEM0
LRP
ATTL0
ATTR0
DACL
SMUTE
0
ATTL4
ATTR4
0
DATTC
ATTL2
ATTR2
0
All registers inhibit writing at PDN pin = “L”.
PDN pin = “L” resets the registers to their default values.
For addresses from 07H to 1FH, data must not be written.
MS0248-E-01
2004/03
- 23 -
ASAHI KASEI
[AK4366]
„ Register Definitions
Addr
00H
Register Name
Power Management
Default
D7
0
0
D6
0
0
D5
0
0
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMHPL
PMDAC
PMVCM
0
0
0
0
0
PMVCM: Power Management for VCOM Block
0: Power OFF (Default)
1: Power ON
In parallel mode (P/S pin = “H”), PMVCM bit is fixed to “1”.
PMDAC: Power Management for DAC Blocks
0: Power OFF (Default)
1: Power ON
When PMDAC bit is changed from “0” to “1”, DAC is powered-up to the current register values (ATT
value, sampling rate, etc). In parallel mode (P/S pin = “H”), PMDAC bit is fixed to “1”.
PMHPL: Power Management for Lch of Headphone Amp
0: Power OFF (Default). HPL pin becomes VSS (0V).
1: Power ON
PMHPR: Power Management for Rch of Headphone Amp
0: Power OFF (Default). HPR pin becomes VSS (0V).
1: Power ON
MUTEN: Headphone Amp Mute Control
0: Mute (Default). HPL and HPR pins go to VSS(0V).
1: Normal operation. HPL and HPR pins go to 0.45 x VDD.
All blocks can be powered-down by setting the PDN pin to “L” regardless of register values setup. All blocks can be
also powered-down by setting all bits of this address to “0”. In this case, control register values are maintained.
MS0248-E-01
2004/03
- 24 -
ASAHI KASEI
Addr
01H
Register Name
Mode Control 0
Default
[AK4366]
D7
0
0
D6
MCKAC
0
D5
HPM
0
D4
DIF2
0
D3
DIF1
1
D2
DIF0
0
D1
DFS1
0
D0
DFS0
0
D1
DEM1
0
D0
DEM0
1
DFS1-0: Oversampling Speed Select (Table 2)
Default: “00” (64fs)
DIF2-0: Audio Data Interface Format Select (Table 3)
Default: “010” (Mode 2)
HPM: Mono Output Select of Headphone
0: Normal Operation (Default)
1: Mono. (L+R)/2 signals from the DAC are output to both Lch and Rch of headphone.
MCKAC: MCLK Input Mode Select
0: CMOS input (Default)
1: AC coupling input
Addr
02H
Register Name
Mode Control 1
Default
D7
0
0
D6
0
0
D5
0
0
D4
SMUTE
0
D3
BST1
0
D2
BST0
0
DEM1-0: De-emphasis Filter Frequency Select (Table 7)
Default: “01” (OFF)
BST1-0: Low Frequency Boost Function Select (Table 9)
Default: “00” (OFF)
SMUTE: Soft Mute Control
0: Normal operation (Default)
1: DAC outputs soft-muted
MS0248-E-01
2004/03
- 25 -
ASAHI KASEI
Addr
03H
Register Name
Mode Control 2
Default
[AK4366]
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
ATS
0
D2
DATTC
0
D1
BCKP
0
D0
LRP
0
LRP: LRCK Polarity Select
0: Normal (Default)
1: Invert
BCKP: BICK Polarity Select
0: Normal (Default)
1: Invert
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent (Default)
1: Dependent
At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of
ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = “0”, ATTL7-0 bits control Lch level and
ATTR7-0 bits control Rch level.
ATS: Digital attenuator transition time setting (Table 6)
0: 1061/fs (Default)
1: 7424/fs
Addr
04H
05H
Register Name
DAC Lch ATT
DAC Rch ATT
Default
D7
ATTL7
ATTR7
0
D6
ATTL6
ATTR6
0
D5
ATTL5
ATTR5
0
D4
ATTL4
ATTR4
0
D3
ATTL3
ATTR3
0
D2
ATTL2
ATTR2
0
D1
ATTL1
ATTR1
0
D0
ATTL0
ATTR0
0
ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 5)
ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 5)
Default: “00H” (MUTE)
The AK4366 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is
placed before D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) of each
channel. Digital attenuator is independent of soft mute function.
Addr
06H
Register Name
Output Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
DACR
0
D0
DACL
0
DACL: DAC Lch output signal is output to Lch of headphone amp.
0: OFF (Default)
1: ON
DACR: DAC Rch output signal is output to Rch of headphone amp.
0: OFF (Default)
1: ON
MS0248-E-01
2004/03
- 26 -
ASAHI KASEI
[AK4366]
SYSTEM DESIGN
Figure 19 and Figure 20 shows the system connection diagram. An evaluation board [AKD4366] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
R
C
R
C
16Ω
Mode
Setting
1
CDTI
HPL
16
2
CCLK
HPR
15
3
CSN
HVDD
14
4
SDATA
VSS
13
VDD
12
16Ω
Headphone
0.1u
10u
Analog Supply
2.2 ∼ 3.6V
Top View
Audio
Controller
5
LRCK
6
BICK
MUTET
11
7
MCLK
VCOM
10
8
PDN
P/S
9
0.1u
1u
0.1u 2.2u
1000p
Figure 19. Typical Connection Diagram (In case of AC coupling to MCLK)
(P/S pin = “L”: Serial mode)
R
C
R
C
16Ω
Mode
Setting
1
MUTEN
HPL
16
2
DEM
HPR
15
3
DIF0
HVDD
14
4
SDATA
VSS
13
VDD
12
16Ω
Headphone
0.1u
10u
Analog Supply
2.2 ∼ 3.6V
Top View
Audio
Controller
5
LRCK
6
BICK
MUTET
11
7
MCLK
VCOM
10
8
PDN
P/S
9
1000p
0.1u
1u
0.1u 2.2u
Figure 20. Typical Connection Diagram (In case of AC coupling to MCLK)
(P/S pin = “H”: Parallel mode)
MS0248-E-01
2004/03
- 27 -
ASAHI KASEI
[AK4366]
1. Grounding and Power Supply Decoupling
The AK4366 requires careful attention to power supply and grounding arrangements. VDD and HVDD are usually
supplied from the analog power supply in the system. When VDD and HVDD are supplied separately, VDD must be
powered-up at the same time or earlier than HVDD. When the AK4366 is powered-down, HVDD must be powered-down
at the same time or later than VDD. VSS must be connected to the analog ground plane. System analog ground and digital
ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as close to the AK4366 as possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference
The input voltage to VDD sets the analog output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor is
connected between VDD and VSS, normally. VCOM is a signal ground of this chip (0.45 x VDD). An electrolytic 2.2µF
in parallel with a 0.1µF ceramic capacitor attached between VCOM and VSS eliminates the effects of high frequency
noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from VDD and
VCOM in order to avoid unwanted coupling into the AK4366.
3. Analog Outputs
The analog outputs are single-ended outputs and 0.47xVDD Vpp(typ)@−4.8dBFS centered on the VCOM voltage. The
input data format is 2’s compliment. The output voltage is a positive full scale for 7FFFFFH(@24bit) and negative full
scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
MS0248-E-01
2004/03
- 28 -
ASAHI KASEI
[AK4366]
PACKAGE
16pin TSSOP (Unit: mm)
5.0
16
1.10max
9
4.4
6.4±0.2
A
1
0.22±0.1
8
0.17±0.05
0.65
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
0∼10°
„ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
MS0248-E-01
2004/03
- 29 -
ASAHI KASEI
[AK4366]
MARKING
AKM
4366VT
XXYYY
1)
2)
3)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4366VT
Revision History
Date (YY/MM/DD)
03/11/28
04/03/23
Revision
00
01
Reason
First Edition
Spec Change
Page
Contents
6
Analog Characteristics
Interchannel Gain Mismatch (max):
0.5dB Æ Removed.
MS0248-E-01
2004/03
- 30 -
ASAHI KASEI
[AK4366]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0248-E-01
2004/03
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