AKM AKD4341

ASAHI KASEI
[AK4341]
AK4341
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4341 is the 24bit DAC with 2Vrms line output for cost and performance based audio systems.
Using AKM's multi bit architecture for its modulator, the AK4341 delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4341 integrates a combination of SCF and
CTF filters increasing performance for systems with excessive clock jitter. The 24 Bit word length and
192kHz sampling rate make this part ideal for a wide range of applications such as digital STB, DVD,
AC-3 receiver system, etc. The AK4341 is offered in a space saving 16pin TSSOP package.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 128 times Oversampling (Normal Speed Mode)
† 64 times Oversampling (Double Speed Mode)
† 32 times Oversampling (Quad Speed Mode)
† 24-Bit 8 times FIR Digital Filter
† SCF with High Tolerance to Clock Jitter
† 2nd Order Analog LPF
† Single Ended Output Buffer
† Digital de-emphasis
† Soft mute
† I/F format: 24-Bit MSB justified or I2S
† Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
† THD+N: -86dB
† Dynamic Range: 100dB
† Power supply: 3.0 ∼ +3.6V (DAC), +8.55 ∼ +12.6V (Output Buffer)
† Ta = -20 to 85°C
† Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
PDN
GAIN
VDD
SMUTE
DEM
DIF
Control
Interface
De-emphasis
Control
HVDD
Clock
Divider
VCOM
ACKS
VSS
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTL
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTR
MS0558-E-01
2007/03
-1-
ASAHI KASEI
[AK4341]
■ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4341
AK4341ET
AKD4341
■ Pin Layout
MCLK
1
16
GAIN
BICK
2
15
VCOM
SDTI
3
14
VDD
LRCK
4
13
VSS
PDN
5
12
HVDD
SMUTE
6
11
AOUTL
ACKS
7
10
AOUTR
DIF
8
9
DEM
Top
View
MS0558-E-01
2007/03
-2-
ASAHI KASEI
[AK4341]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Master Clock Input Pin
1
MCLK
I
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
Power-Down Mode Pin
When at “L”, the AK4341 is in the power-down mode, held in reset and
5
PDN
I
AOUTL/R are held in VCOM. The AK4341 must be reset once upon
power-up.
Soft Mute Pin in parallel control mode
6
SMUTE
I
“H”: Enable, “L”: Disable
Auto Setting Mode Pin
7
ACKS
I
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Audio Data Interface Format Pin
8
DIF
I
“L”: 24bit MSB Justified, “H”: I2S
9
DEM
I
De-emphasis Enable Pin
“H”: Enable, “L”: Disable
Rch Analog Output Pin
10
AOUTR
O
When PDN pin = “L”, outputs VCOM voltage.
Lch Analog Output Pin
11
AOUTL
O
When PDN pin = “L”, outputs VCOM voltage.
Output Buffer Power Supply Pin
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
12
HVDD
10μF electrolytic cap.
13
VSS
Ground Pin
14
VDD
DAC Power Supply Pin
DAC Common Voltage Pin
15
VCOM
O
Normally connected to VSS with a 10μF electrolytic cap.
Outputs VCOM VDD voltage either PDN pin = “L” or “H”.
Gain Control Pin.
“H”: +6dB, “L”: 0dB, open: +12dB.
16
GAIN
I
When PDN=“H”, the Gain pin is connected to VDD and VSS with 50kΩ
resisters and held to VDD/2 when open. When PDN=“L”, connected to VSS
with 50kΩ resister.
Note: All input pins except for the GAIN pin should not be left floating.
MS0558-E-01
2007/03
-3-
ASAHI KASEI
[AK4341]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
DAC
Output Buffer
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Symbol
VDD
HVDD
IIN
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-20
-65
max
+6.0
+14
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
DAC
Output Buffer
Symbol
VDD
HVDD
min
+3.0
+8.55
typ
+3.3
+9.0
max
+3.6
+12.6
Units
V
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0558-E-01
2007/03
-4-
ASAHI KASEI
[AK4341]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD = +3.3V, HVDD = +9.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ, GAIN =0dB; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics (Note 2)
THD+N (0dBFS)
fs=44.1kHz, BW=20kHz
-86
-80
dB
fs=96kHz, BW=40kHz
-86
dB
fs=192kHz, BW=40kHz
-86
dB
Dynamic Range (-60dBFS with A-weighted. Note 3)
94
100
dB
S/N (A-weighted. Note 4)
94
100
dB
Interchannel Isolation (1kHz)
90
dB
Interchannel Gain Mismatch
0.3
dB
DC Accuracy
Gain Drift
100
ppm/°C
Output Voltage (Note 5)
1.85
2
2.15
Vrms
Load Capacitance (Note 6)
25
pF
Load Resistance
5
kΩ
Power Supplies
Power Supply Current: (Note 7)
Normal Operation (PDN pin = “H”, fs≤96kHz)
10
mA
VDD
7
mA
HVDD
Normal Operation (PDN pin = “H”, fs=192kHz)
12
18
mA
VDD
7
11
mA
HVDD
Power-Down Mode (PDN pin = “L”, Note 8)
10
100
VDD
μA
10
100
HVDD
μA
Note 2. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 3. 98dB at 16bit data
Note 4. S/N does not depend on input bit length.
Note 5. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT ([email protected], GAIN =0dB) = 2Vrms × VDD/3.3.
Note 6. In case of driving capacitive load, inset the resister between output pin and the capacitive load.
Note 7. The current into VDD pin or HVDD pin
Note 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD, and GAIN pin is
fixed to VSS or open.
MS0558-E-01
2007/03
-5-
ASAHI KASEI
[AK4341]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V; fs = 44.1kHz; DEM = OFF, GAIN =0dB)
Parameter
Symbol
min
typ
max
Units
Digital filter (DEM = OFF)
PB
0
20.0
kHz
Passband
±0.05dB (Note 9)
22.05
kHz
–6.0dB
Stopband (Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay (Note 10)
GD
19.3
1/fs
De-emphasis Filter (DEM = ON)
De-emphasis Error
fs = 32kHz
–1.5/0
dB
(Relative to 0Hz)
fs = 44.1kHz
–0.2/+0.2
dB
fs = 48kHz
0/+0.6
dB
Digital Filter + LPF (DEM = OFF)
Frequency Response 20.0kHz fs=44.1kHz
FR
dB
± 0.05
40.0kHz fs=96kHz
FR
dB
± 0.05
80.0kHz fs=192kHz
FR
dB
± 0.05
Note 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
DC CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V)
Parameter
Symbol
min
High-Level Input Voltage (except for GAIN pin)
VIH
70%VDD
Low-Level Input Voltage (except for GAIN pin)
VIL
High-Level Input Voltage (for GAIN pin)
VIH
90%VDD
Low-Level Input Voltage (for GAIN pin)
VIL
Open (for GAIN pin. Note 11)
open
Input Leakage Current (Note 12)
Iin
Note 11. GAIN pin is biased to VDD and VSS via50kΩ (typ) resisters internally.
Note 12. Except for the GAIN pin
MS0558-E-01
typ
VDD/2
-
max
30%VDD
10%VDD
± 10
Units
V
V
V
V
V
μA
2007/03
-6-
ASAHI KASEI
[AK4341]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V)
Parameter
Symbol
min
typ
fCLK
2.048
11.2896
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
32
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
tBCK
1/128fsn
Normal Speed Mode
tBCK
1/64fsd
Double Speed Mode
tBCK
1/64fsq
Quad Speed Mode
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK “↑” to LRCK Edge (Note 13)
tLRB
20
LRCK Edge to BICK “↑” (Note 13)
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Reset Timing
tRST
150
RSTN Pulse Width (Note 14)
Note 13. BICK rising edge must not occur at the same time as LRCK edge.
Note 14. The AK4341 can be reset by bringing PDN pin = “L”.
MS0558-E-01
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2007/03
-7-
ASAHI KASEI
[AK4341]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Serial Interface Timing
tPD
PDN
VIL
Power-down Timing
MS0558-E-01
2007/03
-8-
ASAHI KASEI
[AK4341]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4341, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS pin
= “L”, Normal Speed Mode), the frequency of MCLK is set automatically. In Auto Setting Mode (ACKS pin = “H”),
MCLK frequency is detected automatically and then the internal master clock becomes the appropriate frequency (Table
1).
The AK4341 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4341 is powered up. After
exiting reset at power-up etc., the AK4341 is in the power-down mode until MCLK and LRCK are input.
ACKS pin
H
L
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
32.0kHz
44.1kHz
48.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
256fs
22.5792
24.5760
-
-
-
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
512fs
16.3840
22.5792
24.5760
33.8688
36.8640
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
24.5760
33.8688
36.8640
36.8640
-
Sampling
Speed
Normal
Double
Quad
Normal
Table 1. ACKS pin setting and system clock example
■ Audio Serial Interface Format
The Audio data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF pin can selects two serial data
modes as shown in Table 2. In all modes the serial data is MSB-first, 2’s compliment format and latched on the rising edge
of BICK.
Mode
0
1
DIF
L
H
SDTI Format
24bit MSB justified
24bit I2S
BICK
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Table 2. Audio Data Formats
MS0558-E-01
2007/03
-9-
ASAHI KASEI
[AK4341]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
Mode 2
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
Mode 3
23
1
22
0
Don’t care
23
22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
■ De-emphasis Filter
A digital de-emphasis filter is built-in (tc = 50/15µs). DEM pin is internal pull-down pin. Setting DEM pin “H” enables
the digital de-emphasis filter. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain error when the
de-emphasis filter is enabled. De-emphasis filter is off when double/quad speed mode.
DEM pin
H
L
De-emphasis Filter
ON
OFF
Table 3. De-emphasis Filter Control (Normal Speed Mode)
MS0558-E-01
2007/03
- 10 -
ASAHI KASEI
[AK4341]
■ Output Gain Setting
Outputs level of AOUTL/AOUTR pin can be selected by GAIN pin.
GAIN pin
GAIN
Input Level
Output Level (VDD=3.3V)
L
0dB
0dBFS
2Vrms (typ)
H
+6.0dB
-6dBFS
2Vrms (typ)
open
+12dB
-12dBFS
2Vrms (typ)
Note 15. Output level of AOUTL/AOUTR pin clips if it exceeds 2Vrms.
The input data should be 2Vrms or less as the output level.
(Note 15)
(Note 15)
Table 4. Output Level Setting
■ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after
starting the operation, the attenuation is discontinued and returned to 0dB by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin
1024/fs
0dB
1024/fs
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
Notes:
(1) 1020LRCK cycles (1020/fs) at input data is attenuated to -∞.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
Figure 3. Soft Mute
■ System Reset
The AK4341 must be reset once by bringing PDN pin = “L” upon power-up. The AK4341 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4341 is in the
power-down mode until LRCK are input.
MS0558-E-01
2007/03
- 11 -
ASAHI KASEI
[AK4341]
■ Power-down
The AK4341 is placed in the power-down mode by bringing PDN pin “L” and the analog outputs are VCOM voltage
(VDD). Figure 4 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM level (VDD) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 4. Power-down/up Sequence Example
MS0558-E-01
2007/03
- 12 -
ASAHI KASEI
[AK4341]
■ Reset Function
When the MCLK or LRCK stops during the normal operation (PDN pin =”H”), the AK4341 is placed in the reset mode
and its analog outputs are set to VCOM voltage (VDD). When the MCLK and LRCK are restarted, the AK4341 return to
the normal operation mode. The BICK can be stopped when MCLK or LRCK is stopped but shouldn’t be stopped when
MCLK and LRCK are supplied.
PDN pin
(1)
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal Operation
Normal Operation
(3)
GD
D/A Out
(Analog)
Reset
(2)
GD
(4)
Hi-Z
VCOM
(2)
(4)
(4)
<Case1:MCLK Stop>
Clock In
(5) MCLK Stop
MCLK, BICK, LRCK
External
MUTE
(6)
(6)
(6)
<Case2:LRCK Stop>
Clock In
(5) (7) LRCK Stop
MCLK, BICK, LRCK
External
MUTE
(6)
(6)
(6)
Notes:
(1) PDN pin should be “L” for 150ns or more after power-on.
(2) The analog output corresponding to digital input has the group delay (GD).
(3) Digital data can be stopped. The click noise after the MCLK and LRCK are input again can be reduced by
inputting the “0” data during this period.
(4) Click noise occurs within 20usec and 20usec +(3∼4LRCK) after the edges(“↑ ↓”) of the PDN pin and MCLK
starting. The noises also occur when MCLK or LRCK is stopped and within 20usec after stopping.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(6) Mute externally if the click noises (4) cause problem.
(7) The AK4341 detects the stop of LRCK by the ratio MCLK/LRCK > 2048. If the LRCK is input, when LRCK is
stopping, then the AK4341 exits the reset mode.
Figure 5. Reset Timing Example
MS0558-E-01
2007/03
- 13 -
ASAHI KASEI
[AK4341]
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board (AKD4341) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
1
MCLK
GAIN
16
64fs
2
BICK
VCOM
15
24bit Audio Data
3
SDTI
VDD
14
+
10u
0.1u
fs
4
LRCK
Reset & Power down
5
PDN
6
ModeSetting
Digital Ground
+
10u
Analog
Supply 3.3V
VSS
13
HVDD
12
SMUTE
AOUTL
11
Lch Out
7
ACKS
AOUTR
10
Rch Out
8
DIF
DEM
9
AK4341
0.1u
+ 10u
Analog
Supply 9.0V
Analog Ground
Figure 6. Typical Connection Diagram (GAIN = 0dB)
MS0558-E-01
2007/03
- 14 -
ASAHI KASEI
[AK4341]
1. Grounding and Power Supply Decoupling
VDD, HVDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1μF ceramic capacitor for high frequency should be placed as near to VDD and HVDD as possible.
The differential voltage between VDD and VSS pins set the analog output range. The power-up sequence between
VDD and HVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VDD voltage. The output signal range is typically 2Vrms
(typ @VDD=3.3V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and
a negative full scale for 800000H (@24bit). The ideal output is VDD voltage for 000000H (@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VDD + a few mV.
Figure 7 shows an example of the external LPF with 2Vrms (typ) output.
AK4341
10u
470
Analog
Out
AOUT
2Vrms (typ)
22k
2.2nF
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 7. External 1st order LPF Circuit Example
MS0558-E-01
2007/03
- 15 -
ASAHI KASEI
[AK4341]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.1
9
A
8
1
0.13 M
6.4±0.2
*4.4±0.1
16
1.05±0.05
0.22±0.1
0.65
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0558-E-01
2007/03
- 16 -
ASAHI KASEI
[AK4341]
MARKING
AKM
4341ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4341ET
Asahi Kasei Logo
MS0558-E-01
2007/03
- 17 -
ASAHI KASEI
[AK4341]
Revision History
Date (YY/MM/DD)
06/10/30
07/03/26
Revision
00
01
Reason
First Edition
Error correction
Page
Contents
1
FEATURE
I/F format: 24bit MSB justified, 24/16 bit LSB
justified or I2S
Æ 24bit MSB justified or I2S
3
PIN/FUNCTION
No.8 “L”: Left Justified Æ 24 bit MSB Justified
9
AUDIO SERIAL INTERFACE
The DIF pin can select four serial data modes as
shown in Table 2
Æ The DIF pin can select two serial data modes as
shown in Table 2
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0558-E-01
2007/03
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