AKM AKD5700

ASAHI KASEI
[AK5700]
AK5700
16-Bit ΔΣ Mono ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto
Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports
base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a
24pin QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution: 16bits
2. Recording Function
- Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: [email protected]=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: [email protected]=0dB
S/(N+D): 77dB, DR, S/N: [email protected]=+15dB
S/(N+D): 72dB, DR, S/N: [email protected]=+30dB
- Digital HPF for DC-offset cancellation ([email protected]=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
3. Sampling Rate:
- PLL Slave Mode (EXLRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
4. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
- DSP Mode, 16bit MSB justified, I2S
7. μP I/F: 3-wire Serial
8. Power Supply:
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V
9. Power Supply Current: 6mA
10. Ta = −30 ∼ 85°C
11. Package: 24pin QFN (4mm x 4mm)
12. Pin and Register compatible with AK5701 Stereo Version
MS0569-E-01
2006/12
-1-
ASAHI KASEI
[AK5700]
„ Block Diagram
DVDD
DVSS
PDN
AIN1/AIN+
AIN−
S
E
L
ADC
HPF
ALC
or
IVOL
AIN2
LRCK
Audio I/F
Controller
BCLK
S
E
L
SDTO
MPWR
VCOM
AVDD
AVSS
VCOC
Control
Register
PLL
MCKO
MCKI
CSP
EXLRCK
EXBCLK
EXSDTI
CSN CCLK CDTI
Figure 1. Block Diagram
MS0569-E-01
2006/12
-2-
ASAHI KASEI
[AK5700]
„ Ordering Guide
24pin QFN (0.5mm pitch)
−30 ∼ +85°C
Evaluation board for AK5700
AK5700VN
AKD5700
PDN
CSN
CCLK
CDTI
MCKI
EXBCLK
18
17
16
15
14
13
„ Pin Layout
MCKO
AIN -
22
Top View
9
CSP
23
8
SDTO
24
7
LRCK
AIN1 / AIN+
VCOC
6
10
BCLK
AK5700VN
5
21
DVSS
AIN2
4
EXSDTI
DVDD
11
3
20
AVDD
TEST
2
EXLRCK
AVSS
12
1
19
VCOM
MPWR
„ Comparison with AK5701VN
Function
ADC channel Number
Input Selector
Audio I/F Format
AK5701VN
2 channel
2 Stereo Input Selector
DSP Mode 0, DSP Mode 1,
Left justified, I2S
MS0569-E-01
AK5700VN
1channel
2 Mono Input Selector
DSP Mode 0,
Left justified, I2S
2006/12
-3-
ASAHI KASEI
[AK5700]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Common Voltage Output Pin, 0.5 x AVDD
1 VCOM
O
Bias voltage of ADC inputs.
2 AVSS
Analog Ground Pin
3 AVDD
Analog Power Supply Pin
4 DVDD
Digital Power Supply Pin
5 DVSS
Digital Ground Pin
6 BCLK
O
Audio Serial Data Clock Pin
7 LRCK
O
Input / Output Channel Clock Pin
8 SDTO
O
Audio Serial Data Output Pin
Chip Select Polarity Pin
9 CSP
I
“H”: CSN pin = “H” active, C1-0 = “01”
“L”: CSN pin = “L” active, C1-0 = “10”
10 MCKO
O
Master Clock Output Pin
11 EXSDTI
I
External Audio Serial Data Input Pin
12 EXLRCK
I
External Input / Output Channel Clock Pin
13 EXBCLK
I
External Audio Serial Data Clock Pin
14 MCKI
I
External Master Clock Input Pin
15 CDTI
I
Control Data Input Pin
16 CCLK
I
Control Data Clock Pin (Internal Pull-down at CSP pin = “H”)
17 CSN
I
Chip Select Pin
Power-Down Mode Pin
18 PDN
I
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
19 MPWR
O
MIC Power Supply Pin
Test Pin
20 TEST
This pin should be left floating.
21 AIN2
I
Analog Input 2 Pin
22 AIN−
I
Negative Input Pin
AIN1
I
Analog Input 1 Pin
(MDIF1 bit = “0”: Single-ended Input)
23
AIN+
I
Positive Input Pin
(MDIF1 bit = “1”: Full-differential Input)
Output Pin for Loop Filter of PLL Circuit
24 VCOC
O
This pin should be connected to AVSS with one resistor and capacitor in series.
Note 1. All input pins except analog input pins (AIN1, AIN1−, AIN2) should not be left floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR, VCOC, AIN1/AIN+, AIN−, AIN2
BCLK, LRCK, SDTO, MCKO
MCKI, EXBCLK, EXLRCK, EXSDTI
MS0569-E-01
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
2006/12
-4-
ASAHI KASEI
[AK5700]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
−0.3
Digital
DVDD
−0.3
|AVSS – DVSS| (Note 3)
ΔGND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 4)
VINA
−0.3
Digital Input Voltage (Note 5)
VIND
−0.3
Ambient Temperature (powered applied)
Ta
−30
Storage Temperature
Tstg
−65
max
4.6
4.6
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. AIN1/AIN+, AIN−, AIN2 pins
Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 2)
Parameter
Power Supplies
Analog
(Note 6)
Digital
Symbol
AVDD
DVDD
min
2.4
1.6
typ
3.0
3.0
Max
3.6
AVDD
Units
V
V
Note 2. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF, the power
supply current of DVDD at power-down mode may be increased. DVDD should not be powerd OFF while AVDD
is powered ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0569-E-01
2006/12
-5-
ASAHI KASEI
[AK5700]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Min
Typ
max
Units
Parameter
MIC Amplifier: AIN1, AIN2 pins; MDIF1 bit = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
kΩ
Resistance MGAIN1-0 bits = “01” or “10”
20
30
40
kΩ
MGAIN1-0 bits = “00”
0
dB
Gain
MGAIN1-0 bits = “01”
+15
dB
MGAIN1-0 bits = “10”
+30
dB
MIC Amplifier: AIN+, AIN− pins; MDIF1 bit = “1” (Full-differential input)
Input Voltage (Note 7)
MGAIN1-0 bits = “01”
0.37
Vpp
MGAIN1-0 bits = “10”
0.066
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 8)
2.02
2.25
2.48
V
Load Resistance
1.0
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: AIN1/AIN2 pins (Single-ended inputs) → ADC → IVOL,
MGAIN=+15dB, IVOL=0dB, ALC=OFF
Resolution
16
Bits
MGAIN=+30dB
0.057
Vpp
Input Voltage (Note 9)
MGAIN=+15dB
0.27
0.32
0.37
Vpp
MGAIN=0dB
1.53
1.80
2.07
Vpp
67
77
dB
S/(N+D) (−0.5dBFS) (Note 10)
79
87
dB
D-Range (−60dBFS, A-weighted) (Note 11)
S/N (A-weighted) (Note 11)
79
87
dB
Power Supplies:
Power Supply Current: AVDD+DVDD
Power Up (PDN pin = “H”) (Note 12)
6
12
mA
Power Down (PDN pin = “L”) (Note 13)
1
20
μA
Note 7. The voltage difference between AIN+ and AIN− pins. AC coupling capacitor should be inserted in series at each
input pin. Full-differential input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of AIN+,
AIN− pins is proportional to AVDD voltage, respectively.
Vin = |(AIN+) − (AIN−)| = 0.123 x AVDD (max)@MGAIN1-0 bits = “01”, 0.022 x AVDD (max)@MGAIN1-0
bits = “10”.
When the signal larger than above value is input to AIN+, AIN− pin, ADC does not operate normally.
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ).
Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = “01” (+15dB),
Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB).
Note 10. 80dB(typ)@MGAIN=0dB, 70dB(typ)@MGAIN=+30dB
Note 11. 89dB(typ)@MGAIN=0dB, 75dB(typ)@MGAIN=+30dB
Note 12. PLL Master Mode (MCKI=12MHz), PMADC = PMVCM = PMPLL = PMMP = M/S bits = “1” and MCKO bit
= “0”. MPWR pin outputs 0mA. AVDD=4.5mA(typ), DVDD=1.5mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=3.8mA(typ), DVDD=1.2mA(typ).
Bypass Mode (THR bit = “1”, PMADC = M/S bits = “0”), fs=8kHz: AVDD=1μA(typ), DVDD=150μA(typ).
Note 13. All digital input pins are fixed to DVDD or DVSS.
MS0569-E-01
2006/12
-6-
ASAHI KASEI
[AK5700]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; fs=44.1kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
PB
0
Passband (Note 14)
±0.1dB
−1.0dB
−3.0dB
Stopband (Note 14)
SB
25.7
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay (Note 15)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF): HPF1-0 bits = “00”
Frequency Response (Note 14) −3.0dB
FR
−0.5dB
−0.1dB
typ
max
Units
20.0
21.1
18
0
17.4
±0.1
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
3.4
10
22
-
Hz
Hz
Hz
Note 14. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.454*fs (@−1.0dB). Each response refers to that of 1kHz.
Note 15. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data from the input register to the output register of the ADC. This time includes the group delay of the
HPF.
DC CHARACTERISTICS
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
Except CSP pin; 2.2V≤ DVDD ≤3.6V
VIH
70%DVDD
Except CSP pin; 1.6V≤ DVDD <2.2V
VIH
80%DVDD
CSP pin
VIH
90%DVDD
Low-Level Input Voltage
Except CSP pin; 2.2V≤ DVDD ≤3.6V
VIL
Except CSP pin; 1.6V≤ DVDD <2.2V
VIL
CSP pin
VIL
High-Level Output Voltage
(Iout= −200μA)
VOH
DVDD−0.2
Low-Level Output Voltage
(Iout= 200μA)
VOL
Input Leakage Current (Note 16)
Iin
-
typ
max
Units
-
-
V
V
V
-
30%DVDD
20%DVDD
10%DVDD
0.2
±10
V
V
V
V
V
μA
Note 16. When CSP pin is “H”, CCLK pin has internal pull-down device, normally 100kΩ.
MS0569-E-01
2006/12
-7-
ASAHI KASEI
[AK5700]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK
Except DSP Mode: Duty Cycle
Duty
50
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
1/(32fs)
BCKO1-0 bit = “10”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
EXLRCK Input Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
PLL Slave Mode (PLL Reference Clock = EXLRCK pin)
EXLRCK Input Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS0569-E-01
max
Units
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
-
kHz
ns
%
-
ns
ns
%
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
1/fs − tBCK
55
kHz
ns
%
1/(32fs)
-
ns
ns
ns
48
1/fs − tBCK
55
kHz
ns
%
1/(32fs)
-
ns
ns
ns
2006/12
-8-
ASAHI KASEI
[AK5700]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = EXBCLK pin)
EXLRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
EXLRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
BCKO1-0 bit = “10”
tBCK
Duty Cycle
dBCK
MS0569-E-01
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2006/12
-9-
ASAHI KASEI
Parameter
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BCLK “↑” (Note 17)
LRCK “↑” to BCLK “↓” (Note 18)
BCLK “↑” to SDTO (BCKP bit = “0”)
BCLK “↓” to SDTO (BCKP bit = “1”)
Slave Mode
EXLRCK “↑” to EXBCLK “↑” (Note 17)
EXLRCK “↑” to EXBCLK “↓” (Note 18)
EXBCLK “↑” to EXLRCK “↑” (Note 17)
EXBCLK “↓” to EXLRCK “↑” (Note 18)
EXBCLK “↑” to SDTO (BCKP bit = “0”)
EXBCLK “↓” to SDTO (BCKP bit = “1”)
Audio Interface Timing (Left justified & I2S)
Master Mode
BCLK “↓” to LRCK Edge (Note 19)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
BCLK “↓” to SDTO
Slave Mode
EXLRCK Edge to EXBCLK “↑” (Note 19)
EXBCLK “↑” to EXLRCK Edge (Note 19)
EXLRCK Edge to SDTO (MSB)
(Except I2S mode)
EXBCLK “↓” to SDTO
[AK5700]
Symbol
min
typ
Max
Units
tDBF
tDBF
tBSD
tBSD
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
ns
ns
ns
ns
tLRB
tLRB
tBLR
tBLR
tBSD
tBSD
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
-
-
80
80
ns
ns
ns
ns
ns
ns
tMBLR
tLRD
−40
−70
-
40
70
ns
ns
tBSD
−70
-
70
ns
tLRB
tBLR
tLRD
50
50
-
-
80
ns
ns
ns
tBSD
-
-
80
ns
Note 17. MSBS, BCKP bits = “00” or “11”
Note 18. MSBS, BCKP bits = “01” or “10”
Note 19. EXBCLK rising edge must not occur at the same time as EXLRCK edge.
MS0569-E-01
2006/12
- 10 -
ASAHI KASEI
Parameter
Control Interface Timing (CSP pin = “L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (CSP pin = “H”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “L” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↓”
Power-down & Reset Timing
PDN Pulse Width (Note 20)
PMADC “↑” to SDTO valid (Note 21)
HPF1-0 bits = “00”
HPF1-0 bits = “01”
HPF1-0 bits = “10”
[AK5700]
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
142
56
56
28
28
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
142
56
56
28
28
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
-
-
ns
tPDV
tPDV
tPDV
-
3088
1552
784
-
1/fs
1/fs
1/fs
Note 20. The AK5700 can be reset by the PDN pin = “L”.
Note 21. This is the count of LRCK “↑” from the PMADC bit = “1”.
MS0569-E-01
2006/12
- 11 -
ASAHI KASEI
[AK5700]
„ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
BCLK
tBCKH
tBCKL
1/fMCK
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
MCKO
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BCLK
(BCKP = "0")
50%DVDD
BCLK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS0569-E-01
2006/12
- 12 -
ASAHI KASEI
[AK5700]
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BCLK
(BCKP = "1")
50%DVDD
BCLK
(BCKP = "0")
50%DVDD
tBSD
SDTO
MSB
50%DVDD
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)
50%DVDD
LRCK
tMBLR
tBCKL
BCLK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
MS0569-E-01
2006/12
- 13 -
ASAHI KASEI
[AK5700]
1/fs
VIH
EXLRCK
VIL
tLRCKH
tBLR
tBCK
VIH
EXBCLK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
EXBCLK
(BCKP = "1")
VIL
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0)
1/fs
VIH
EXLRCK
VIL
tLRCKH
tBLR
tBCK
VIH
EXBCLK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
EXBCLK
(BCKP = "0")
VIL
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1)
MS0569-E-01
2006/12
- 14 -
ASAHI KASEI
[AK5700]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
EXLRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
EXBCLK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
tLRCKH
VIH
EXLRCK
VIL
tLRB
VIH
EXBCLK
VIL
(BCKP = "0")
VIH
EXBCLK
(BCKP = "1")
VIL
tBSD
SDTO
MSB
50%DVDD
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
MS0569-E-01
2006/12
- 15 -
ASAHI KASEI
[AK5700]
tLRCKH
VIH
EXLRCK
VIL
tLRB
VIH
EXBCLK
VIL
(BCKP = "1")
VIH
EXBCLK
(BCKP = "0")
VIL
tBSD
SDTO
50%DVDD
MSB
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
EXLRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
EXBCLK
VIL
tBCKH
tBCKL
Figure 11. Clock Timing (EXT Slave mode)
MS0569-E-01
2006/12
- 16 -
ASAHI KASEI
[AK5700]
VIH
EXLRCK
VIL
tBLR
tLRB
VIH
EXBCLK
VIL
tBSD
tLRD
SDTO
MSB
50%DVDD
Figure 12. Audio Interface Timing (PLL/EXT Slave mode)
MS0569-E-01
2006/12
- 17 -
ASAHI KASEI
[AK5700]
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 13. WRITE Command Input Timing (CSP pin = “L”)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 14. WRITE Data Input Timing (CSP pin = “L”)
MS0569-E-01
2006/12
- 18 -
ASAHI KASEI
[AK5700]
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 15. WRITE Command Input Timing (CSP pin = “H”)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 16. WRITE Data Input Timing (CSP pin = “H”)
MS0569-E-01
2006/12
- 19 -
ASAHI KASEI
[AK5700]
PMADC bit
tPDV
SDTO
50%DVDD
Figure 17. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 18. Power Down & Reset Timing 2
MS0569-E-01
2006/12
- 20 -
ASAHI KASEI
[AK5700]
OPERATION OVERVIEW
„ System Clock
There are the following five clock modes to interface with external devices (see Table 1 and Table 2.)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 22)
1
1
See Table 4
Figure 19
PLL Slave Mode 1
1
0
See Table 4
Figure 20
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
1
0
See Table 4
Figure 21
(PLL Reference Clock: EXLRCK or EXBCLK pin)
EXT Slave Mode
0
0
x
Figure 22
EXT Master Mode (Note 23)
0
0
x
Figure 23
Note 22. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Note 23. In case of EXT Master Mode, the register should be set as Figure 45.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
MCKO bit
MCKO pin
0
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
1
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
0
1
MCKI pin
BCLK pin,
LRCK pin,
EXBCLK pin EXLRCK pin
Selected by
PLL3-0 bits
BCLK pin
(Selected by
BCKO1-0 bits)
Selected by
PLL3-0 bits
EXBCLK pin EXLRCK pin
(1fs)
(≥ 32fs)
LRCK pin
(1fs)
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
0
“L”
GND
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
EXBCLK pin
EXLRCK pin
(Selected by
(1fs)
PLL3-0 bits)
EXBCLK pin EXLRCK pin
(1fs)
(≥ 32fs)
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin
(1fs)
Table 2. Clock pins state in Clock Mode
„ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5700 is power-down mode (PDN pin = “L”) and exits reset state, the AK5700 is slave mode. After exiting reset state,
the AK5700 goes to master mode by changing M/S bit = “1”.
M/S bit
0
1
Mode
Used pins
Slave Mode
EXBCLK, EXLRCK
Master Mode
BCLK, LRCK
Table 3. Select Master/Salve Mode
MS0569-E-01
Default
2006/12
- 21 -
ASAHI KASEI
[AK5700]
„ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5700 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
Bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input Frequency
0
2
0
0
0
0
0
1
0
0
EXLRCK pin
EXBCLK pin
1fs
32fs
3
0
0
1
1
EXBCLK pin
64fs
4
5
6
7
8
9
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
R and C of
VCOC pin
R[Ω] C[F]
6.8k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
220n
4.7n
10n
4.7n
10n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
10n
10n
220n
220n
PLL
Lock
Time
(max)
80ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
12MHz (Note24)
Default
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
Others
Others
N/A
Note 24. See Table 5 regarding the difference between PLL3-0 bits = “0110”(Mode 6) and “1001”(Mode 9).
Clock jitter is lower in Mode9 than Mode6 respectively.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
7.35kHz
4
0
1
0
0
7.349918kHz (Note25)
11.025kHz
5
0
1
0
1
11.024877kHz (Note25)
14.7kHz
6
0
1
1
0
14.69984kHz (Note25)
22.05kHz
7
0
1
1
1
22.04975kHz (Note25)
32kHz
10
1
0
1
0
48kHz
11
1
0
1
1
29.4kHz
14
1
1
1
0
29.39967kHz (Note25)
44.1kHz
15
1
1
1
1
Default
44.0995kHz (Note25)
Others
Others
N/A
Note 25. In case of PLL3-0 bits = “1001”
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” and Reference Clock=MCKI pin
MS0569-E-01
2006/12
- 22 -
ASAHI KASEI
[AK5700]
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(See Table 6).
FS3 bit
FS2 bit
Sampling Frequency
Mode
FS1 bit
FS0 bit
Range
0
0
Don’t care
Don’t care
7.35kHz ≤ fs ≤ 12kHz
0
0
1
Don’t care
Don’t care
1
12kHz < fs ≤ 24kHz
1
Don’t care
Don’t care
Don’t care
2
24kHz < fs ≤ 48kHz
Default
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
„ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 7).
In DSP Mode 0, BCLK and LRCK start to output corresponding to Ach data after PLL goes to lock state by setting
PMPLL bit = “0” Æ “1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0, BCLK “H” time of the first pulse
becomes shorter by 1/(256fs) than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BCLK pin
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
See Table 9
See Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC outputs invalid data when
the PLL is unlocked.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock (except above case)
“L” Output
Invalid
PLL Lock
“L” Output
See Table 9
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PLL State
MS0569-E-01
2006/12
- 23 -
ASAHI KASEI
[AK5700]
„ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated by an internal PLL circuit. The MCKO output
frequency is selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BCLK output frequency is
selected among 32fs or 64fs, by BCKO1-0 bits (see Table 10).
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or μP
AK5700
MCKI
MCKO
BCLK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 19. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCLK Output
Frequency
0
0
N/A
0
1
32fs
Default
1
0
64fs
1
1
N/A
Table 10. BCLK Output Frequency at Master Mode
BCKO1 bit
BCKO0 bit
MS0569-E-01
2006/12
- 24 -
ASAHI KASEI
[AK5700]
„ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, EXBCLK or EXLRCK pin. The required clock to
the AK5700 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).
a) PLL reference clock: MCKI pin
EXBCLK and EXLRCK inputs should be synchronized with MCKO output. The phase between MCKO and EXLRCK
dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by
MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5).
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5700
DSP or μP
MCKI
MCKO
EXBCLK
EXLRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation
(PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
should be in the power-down mode (PMADC bit = “0”).
b) PLL reference clock: EXBCLK or EXLRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).
AK5700
DSP or μP
MCKI
EXBCLK
EXLRCK
32fs, 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK pin)
MS0569-E-01
2006/12
- 25 -
ASAHI KASEI
[AK5700]
„ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK5700 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), EXLRCK (fs) and EXBCLK (≥32fs). The master clock (MCKI) should be synchronized with
EXLRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see
Table 11).
Mode
0
1
2
3
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
512fs
7.35kHz ∼ 26kHz
Don’t care
1
1
256fs
7.35kHz ∼ 48kHz
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
FS3-2 bits
FS1 bit
FS0 bit
Default
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation
(PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
should be in the power-down mode (PMADC bit = “0”).
AK5700
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
EXBCLK
EXLRCK
≥ 32fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 22. EXT Slave Mode
MS0569-E-01
2006/12
- 26 -
ASAHI KASEI
[AK5700]
„ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is
selected by FS1-0 bits (see Table 12).
Mode
FS3-2 bits
0
1
2
3
Don’t care
Don’t care
Don’t care
Don’t care
MCKI Input
Sampling Frequency
Frequency
Range
0
0
256fs
7.35kHz ∼ 48kHz
0
1
1024fs
7.35kHz ∼ 13kHz
1
0
512fs
7.35kHz ∼ 26kHz
1
1
256fs
7.35kHz ∼ 48kHz
Table 12. MCKI Frequency at EXT Master Mode
FS1 bit
FS0 bit
Default
MCKI should always be present whenever the ADC is in operation (PMADC bit = “1”). If MCKI is not provided, the
AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the ADC should be in the power-down mode (PMADC bits = “0”).
AK5700
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BCLK
MCLK
32fs or 64fs
1fs
LRCK
BCLK
LRCK
SDTI
SDTO
Figure 23. EXT Master Mode
BCLK Output
Frequency
0
0
N/A
0
1
32fs
Default
1
0
64fs
1
1
N/A
Table 13. BCLK Output Frequency at Master Mode
BCKO1 bit
BCKO0 bit
MS0569-E-01
2006/12
- 27 -
ASAHI KASEI
[AK5700]
„ Bypass Mode
When THR bit = “1”, M/S bit = “0” and PMADC bit = “0” input clocks and data of EXLRCK, EXBCLK and EXSDTI
pins are bypassed to LRCK, BCLK and SDTO pins, respectively.
When THR bit = “1”, M/S bit = “0” and PMADC bit = “1” input clocks of EXLRCK and EXBCLK pins are bypassed to
LRCK and BCLK pins, and ADC data is output from SDTO pin.
THR bit
M/S bit
0
0
1
0
1
1
PMADC bit
0
1
0
1
0
1
0
1
DSP or μP
BCLK/LRCK
SDTO
“L”
“L”
“L”
ADC data
Output
“L”
Output
ADC data
EXBCLK/EXLRCK
EXSDTI
EXBCLK/EXLRCK ADC data
N/A
N/A
Output
ADC data
Table 14. Bypass Mode Select
BCLK
1fs
SDTI
Figure
Default
Figure 24
Figure 25
DSP or μP
AK5700
≥ 32fs
LRCK
Mode
Power down
Slave mode
Power down
Master mode
Bypass mode
Slave & Bypass
N/A
Master mode
≥ 32fs
BCLK
EXBCLK
LRCK
EXLRCK
SDTO
EXSDTI
BCLK
1fs
LRCK
SDTO
Figure 24. Bypass Mode
DSP or μP
DSP or μP
AK5700
≥ 32fs
BCLK
LRCK
SDTI
1fs
≥ 32fs
BCLK
EXBCLK
LRCK
EXLRCK
SDTO
AIN
BCLK
1fs
LRCK
Analog In
Figure 25. Slave & Bypass Mode
MS0569-E-01
2006/12
- 28 -
ASAHI KASEI
[AK5700]
„ Audio Interface Format
Fore types of data format are available and are selected by setting the DIF1-0 bits (see Table 15). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK,
BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and SDTO pins are used in slave mode. In modes
2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BCLK/EXBCLK. SDTO pin outputs same data two times in
one period of EXLRCK/LRCK.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO
BCLK, EXBCLK
DSP Mode 0
32fs
Reserved
MSB justified
≥ 32fs
I2S compatible
≥ 32fs
Table 15. Audio Interface Format
Figure
See Table 16
Figure 30
Figure 31
Default
In Mode 0 (DSP mode 0), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“↑”) of BCLK/EXBCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“↓”) of BCLK/EXBCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK.
DIF1
0
DIF0
0
MSBS
BCKP
0
0
0
1
1
0
1
1
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the first BCLK/EXBCLK
after the rising edge (“↑”) of LRCK/EXLRCK (Figure 26).
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK (Figure 27).
MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”) of
the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 28).
MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”) of
the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 29).
Table 16. Audio Interface Format in Mode 0
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0569-E-01
2006/12
- 29 -
ASAHI KASEI
[AK5700]
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
8
15 14
2
1
0
2
15 14
1
0
8
15 14
2
1
0
1/fs
2
15 14
1
0
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
8
15 14
2
1
0
2
15 14
1
0
8
15 14
2
1
0
15 14
2
1
0
1/fs
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “0”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
15 14
8
2
1
2
15 14
0
1
0
15 14
8
2
1
0
1/fs
2
15 14
1
0
1/fs
15:MSB, 0:LSB
Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “1”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1/fs
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 29. Mode 0 Timing (BCKP = “1”, MSBS = “1”, M/S = “0” or “1”)
Note : The data from 0 to 15 bits is the same as from 16 to 31 bits at the Figure 26, Figure 27,
Figure 28, Figure 29
MS0569-E-01
2006/12
- 30 -
ASAHI KASEI
[AK5700]
EXLRCK
LRCK
0
1
2
8
3
9
10
11
12
13
14
15
0
1
2
8
3
9
10
11
12
13
14
15
0
1
EXBCLK(32fs)
BCLK(32fs)
15 14 13
SDTO(o)
0
1
2
8
7
3
6
14
5
15
4
16
3
17
2
1
18
0
31
15 14 13
0
1
2
8
7
3
6
14
5
15
4
16
3
17
2
1
18
0
31
15
0
1
EXBCLK(64fs)
BCLK(64fs)
15 14 13
SDTO(o)
13 2
1
0
15 14 13
1
2
2
1
0
15
15:MSB, 0:LSB
1/fs
Figure 30. Mode 2 Timing (MSB justified, M/S = “0” or “1”)
EXLRCK
LRCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
4
9
10
11
12
13
14
15
0
1
EXBCLK(32fs)
BCLK(32fs)
0
SDTO(o)
0
15
1
14 13
2
3
4
7
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1
2
3
7
4
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
1
EXBCLK(64fs)
BCLK(64fs)
SDTO(o)
15 14 13
2
1
0
15 14 13
2
2
1
0
15:MSB, 0:LSB
1/fs
Figure 31. Mode 3 Timing (I2S, M/S = “0” or “1”)
Note : The data from 0 to 15 bits is the same as when LRCK is “H” or “L” at the Figure 30, Figure 31
MS0569-E-01
2006/12
- 31 -
ASAHI KASEI
[AK5700]
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is selected by HPF1-0
bits (see Table 17) and scales with sampling rate (fs). The default value is 3.4Hz (@fs=44.1kHz).
HPF1 bit
HPF0 bit
0
0
1
1
0
1
0
1
fc
fs=44.1kHz
fs=22.05kHz
3.4Hz
1.7Hz
6.8Hz
3.4Hz
13.6Hz
6.8Hz
N/A
N/A
Table 17. Digital HPF Cut-off Frequency
fs=11.025kHz
0.85Hz
1.7Hz
3.4Hz
N/A
Default
„ MIC/LINE Input Selector
The AK5700 has input selector. When MDIF1 bit is “0”, AIN bit selects AIN1or AIN2. When MDIF1 bit is “1”, AIN1pin
become AIN+ pin . In this case, full-differential input is available (Figure 33). When full-differential input is used, the
signal should not be input to the pins marked by “X” in Table 19.
MDIF1 bit
0
1
AIN bit
Ach
AIN1
0
AIN1
AIN2
1
AIN2
0
AIN1
1
N/A
N/A
x
AIN+/−
x
AIN+/−
Table 18. MIC/Line In Path Select
Default
Register
Pin
AIN1
MDIF1 bit
AIN2
AIN1−
AIN1+
0
O
O
1
O
X
O
Table 19. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.)
AK5700
AIN1/AIN+ pin
AIN bit
ADC
AIN− pin
AIN2 pin
MDIF1 bit
Figure 32. Mic/Line Input Selector
MS0569-E-01
2006/12
- 32 -
ASAHI KASEI
[AK5700]
AK5700
MPWR pin
1k
MIC-Amp
AIN+ pin
AIN− pin
1k
Figure 33. Connection Example for Full-differential Mic Input (MDIF1bit = “1”)
„ MIC Gain Amplifier
The AK5700 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see
Table 20). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01” or
“10”.
MGAIN1 bit
0
0
1
1
MGAIN0 bit
Input Gain
0
0dB
1
+15dB
0
+30dB
1
N/A
Table 20. Mic Input Gain
Default
„ MIC Power
When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD
and the load resistance is minimum 1.0kΩ. In case of using two sets of mono mic, the load resistance is minimum 2.0kΩ
for each channel. No capacitor must not be connected directly to MPWR pin (see Figure 34).
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 21. MIC Power
Default
MIC Power
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
AIN1 pin
Microphone
AIN2 pin
Figure 34. MIC Block Circuit
MS0569-E-01
2006/12
- 33 -
ASAHI KASEI
[AK5700]
„ ALC Operation
The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”.
1.
ALC Limiter Operation
During the ALC limiter operation, when the output exceeds the ALC limiter detection level (Table 22), the IVL value is
attenuated automatically by the amount defined by the ALC limiter ATT step (Table 23).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL value is changed by ALC limiter operation at the
individual zero crossing point of zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC
limiter and recovery operation (Table 24).
When ZELMN bit = “1” (zero cross detection is disabled), IVL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 22)
or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
ZELMN
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
LMAT1
0
0
1
1
x
LMAT0
ALC Limiter ATT Step
0
1 step
0.375dB
1
2 step
0.750dB
0
4 step
1.500dB
1
8 step
3.000dB
x
1step
0.375dB
Table 23. ALC Limiter ATT Step
Default
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC Zero Crossing Timeout Period
MS0569-E-01
Default
Default
2006/12
- 34 -
ASAHI KASEI
2.
[AK5700]
ALC Recovery Operation
The ALC recovery operation waits for the WTM1-0 bits (Table 25) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 22) during the wait time, the ALC
recovery operation is done. The IVL value is automatically incremented by RGAIN1-0 bits (Table 26) up to the set
reference level (Table 27) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 24). The ALC
recovery operation is done at a period set by WTM1-0 bits. If ZTM1-0 is longer than WTM1-0 and no zero crossing
occurs, the ALC recovery operation is done at a period set by ZTM1-0 bits.
For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the
auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds
the reference level (REF7-0), the IVOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of
small level in the large noise can be improved by this fast recovery operation.
WTM1
WTM0
0
0
1
1
0
1
0
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 25. ALC Recovery Operation Waiting Period
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 26. ALC Recovery GAIN Step
Default
Default
REF7-0
GAIN(dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
0.375dB
E1H
+30.0
Default
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 27. Reference Level at ALC Recovery operation
MS0569-E-01
2006/12
- 35 -
ASAHI KASEI
3.
[AK5700]
Example of ALC Operation
Table 28 shows the examples of the ALC setting for mic recording.
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Register Name
Comment
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
00
16ms
as ZTM1-0 bits
Maximum gain at recovery operation
E1H
+30dB
Gain of IVOL
91H
0dB
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Table 28. Example of the ALC setting
WTM1-0
REF7-0
IVL7-0
LMAT1-0
RGAIN1-0
ALC
Data
01
0
00
Data
01
0
10
fs=44.1kHz
Operation
−4.1dBFS
Enable
11.6ms
10
11.6ms
E1H
91H
00
00
1
+30dB
0dB
1 step
1 step
Enable
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADC bit = “0”.
• LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
WR (IVL7-0)
ALC bit = “1”
* The value of IVOL should be
(1) Addr=18H, Data=91H
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(2) Addr=1AH, Data=00H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write
Figure 35. Registers set-up sequence at ALC operation
MS0569-E-01
2006/12
- 36 -
ASAHI KASEI
[AK5700]
„ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 bits set the gain of the volume control (Table 29). The IVOL value is changed at zero crossing or timeout. Zero
crossing timeout period is set by ZTM1-0 bits.
If IVL7-0 bits are written during PMADC bit = “0”, IVOL operation starts with the written values at the end of the ADC
initialization cycle after PMADC bit is changed to “1”.
IVL7-0
F1H
F0H
EFH
:
92H
91H
90H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+0.375
0.375dB
0.0
−0.375
:
−53.25
−53.625
−54
MUTE
Table 29. Input Digital Volume Setting
MS0569-E-01
Default
2006/12
- 37 -
ASAHI KASEI
[AK5700]
When writing to the IVL7-0 bits continuouslly, the control register should be written by an interval more than zero
crossing timeout. If not, IVL is not changed since zero crossing counter is reset at every write operation. If the same
register value as the previous write operation is written to IVL, this write operation is ignored and zero crossing counter is
not reset. Therefore, IVL can be written by an interval less than zero crossing timeout.
ALC bit
ALC Status
Disable
Enable
IVL7-0 bits
Disable
E1H(+30dB)
(1)
Internal IVL
E1H(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
Figure 36. IVOL value during ALC operation
(1) The wait time from ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus
zerocross timeout period (ZTM1-0 bits).
(2) Writing to IVL register (18H) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last
written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” by an interval
more than zero crossing timeout period after ALC bit = “0”.
„ System Reset
Upon power-up, the AK5700 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization
cycle time is [email protected]=44.1kHz when HPF1-0 bits are “00” (see Table 30). During the initialization cycle, the
ADC digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input
signal after the initialization cycle is complete.
Init Cycle
fs=44.1kHz
fs=22.05kHz
70.0ms
140.0ms
HPF1 bit
HPF0 bit
0
0
3088/fs
0
1
1552/fs
35.2ms
1
0
784/fs
17.8ms
1
1
Cycle
(Recommendation)
70.4ms
(Recommendation)
35.6ms
N/A
N/A
N/A
Table 30. ADC Initialization Cycle
MS0569-E-01
fs=11.025kHz
280.1ms
Default
140.8ms
71.1ms
(Recommendation)
N/A
2006/12
- 38 -
ASAHI KASEI
[AK5700]
„ Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). CSP pin selects the
polarity of CSN pin and chip address.
1) CSP pin = “L”
The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge(“↓”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 37. Serial Control I/F Timing (CSP pin = “L”)
2) CSP pin = “H”
The data on this interface consists of a 2-bit Chip address (Fixed to “01”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“↑”) after CSN rising edge(“↑”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“0” “1” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “0”, C0 = “1”); Fixed to “01”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 38. Serial Control I/F Timing (CSP pin = “H”)
MS0569-E-01
2006/12
- 39 -
ASAHI KASEI
[AK5700]
„ Register Map
Addr
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
Register Name
Power Management
PLL Control
Signal Select
Mic Gain Control
Audio Format Select
fs Select
Clock Output Select
Reserved
Input Volume Control
Reserved
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Mode Control 1
Mode Control 2
D7
0
0
0
0
0
HPF1
0
0
IVL7
1
0
REF7
ALC
TE3
0
D6
0
0
0
0
0
HPF0
0
0
IVL6
0
0
REF6
ZELMN
TE2
0
D5
0
PLL3
0
0
1
BCKO1
0
0
IVL5
0
0
REF5
LMAT1
TE1
0
D4
0
PLL2
PMMP
0
0
BCKO0
0
0
IVL4
1
0
REF4
LMAT0
TE0
0
D3
0
PLL1
0
0
MSBS
FS3
THR
0
IVL3
0
ZTM1
REF3
RGAIN1
0
0
D2
PMVCM
PLL0
MDIF1
0
BCKP
FS2
MCKO
0
IVL2
0
ZTM0
REF2
RGAIN0
0
0
D1
0
M/S
0
D0
PMADC
PMPLL
AIN
MGAIN1
MGAIN0
DIF1
FS1
PS1
0
IVL1
0
WTM1
REF1
LMTH1
0
DIF0
FS0
PS0
1
IVL0
1
WTM0
REF0
LMTH0
0
0
TMASTER
Note 26. PDN pin = “L” resets the registers to their default values.
Note 27. “0” must be sent to the register written as “0” and “1” must be sent to the register written as “1”. For addresses
except for 10H to 1EH, data must not be written.
MS0569-E-01
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ASAHI KASEI
[AK5700]
„ Register Definitions
Addr
10H
Register Name
Power Management
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
PMVCM
0
D1
0
0
D0
PMADC
0
PMADC: MIC-Amp and ADC Power Management
0: Power down (Default)
1: Power up
When the PMADC bit is changed from “0” to “1”, the initialization cycle ([email protected]= 44.1kHz,
HPF1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMVCM: VCOM Power Management
0: Power down (Default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when PMADC=PMPLL=PMMP=MCKO bits = “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When PMVCM, PMADC, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values remain
unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin should be “L”.
When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be
present.
Addr
11H
Register Name
PLL Control
Default
D7
0
0
D6
0
0
D5
PLL3
1
D4
PLL2
0
D3
PLL1
0
D2
PLL0
1
D1
M/S
0
D0
PMPLL
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (Default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (Default)
1: Master Mode
PLL3-0: PLL Reference Clock Select (See Table 4)
Default: “1001”(MCKI pin=12MHz)
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ASAHI KASEI
Addr
12H
Register Name
Signal Select
Default
[AK5700]
D7
0
0
D6
0
0
D5
0
0
D4
PMMP
0
D3
0
0
D2
MDIF1
0
D1
0
0
D0
AIN
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
D0
MGAIN1
MGAIN0
0
1
D1
DIF1
1
D0
DIF0
1
AIN: ADC Input Source Select
0: AIN1 pin (Default)
1: AIN2 pin
MDIF1: ADC Input Type Select
0: Single-ended input (AIN1/AIN2 pin: Default)
1: Full-differential input (AIN+/AIN− pin)
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (Default)
1: Power up
Addr
13H
Register Name
Mic Gain Control
Default
D7
0
0
D6
0
0
MGAIN1-0: MIC-Amp Gain Control (See Table 20)
Default: “01”(+15dB)
Addr
14H
Register Name
Audio Format Select
Default
D7
0
0
D6
0
0
D5
1
1
D4
0
0
D3
MSBS
0
D2
BCKP
0
DIF1-0: Audio Interface Format (See Table 15)
Default: “11” (I2S)
BCKP: BCLK/EXBCLK Polarity at DSP Mode (See Table 16)
“0”: SDTO is output by the rising edge (“↑”) of BCLK/EXBCLK. (Default)
“1”: SDTO is output by the falling edge (“↓”) of BCLK/EXBCLK.
MSBS: LRCK/EXLRCK Polarity at DSP Mode (See Table 16)
“0”: The rising edge (“↑”) of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change.
(Default)
“1”: The rising edge (“↑”) of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
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ASAHI KASEI
Addr
15H
Register Name
fs Select
Default
[AK5700]
D7
HPF1
0
D6
HPF0
0
D5
BCKO1
0
D4
BCKO0
1
D3
FS3
1
D2
FS2
1
D1
FS1
1
D0
FS0
1
FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (See Table 11)
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (See Table 10)
Default: “01” (32fs)
HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (See Table 17, Table 30)
Default: “00” ([email protected]=44.1kHz, Init Cycle=3088/fs)
Addr
16H
Register Name
Clock Output Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
THR
0
D2
MCKO
0
D1
PS1
0
D0
PS0
0
D5
IVL5
0
D4
IVL4
1
D3
IVL3
0
D2
IVL2
0
D1
IVL1
0
D0
IVL0
1
PS1-0: MCKO Output Frequency Select (See Table 9)
Default: “00”(256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (Default)
1: Enable: Output frequency is selected by PS1-0 bits.
THR: Bypass Mode (Table 14)
0: OFF (Default)
1: ON
Addr
18H
Register Name
Input Volume Control
Default
D7
IVL7
1
D6
IVL6
0
IVL7-0: Input Digital Volume; 0.375dB step, 242 Level (See Table 29)
Default: “91H” (0dB)
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ASAHI KASEI
Addr
1AH
Register Name
Timer Select
Default
[AK5700]
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
ZTM1
0
D2
ZTM0
0
D1
WTM1
0
D0
WTM0
0
D1
REF1
0
D0
REF0
1
D1
LMTH1
0
D0
LMTH0
0
WTM1-0: ALC Recovery Waiting Period (see Table 25)
Default: “00” (128/fs)
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 24)
Default: “00” (128/fs)
Addr
1BH
Register Name
ALC Mode Control 1
Default
D7
REF7
1
D6
REF6
1
D5
REF5
1
D4
REF4
0
D3
REF3
0
D2
REF2
0
REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (See Table 27)
Default: “E1H” (+30.0dB)
Addr
1CH
Register Name
ALC Mode Control 2
Default
D7
ALC
0
D6
ZELMN
0
D5
LMAT1
0
D4
LMAT0
0
D3
D2
RGAIN1
RGAIN0
0
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 22)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (see Table 26)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (see Table 23)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (Default)
1: Disable
ALC: ALC Enable
0: ALC Disable (Default)
1: ALC Enable
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ASAHI KASEI
Addr
1DH
Register Name
Mode Control 1
Default
[AK5700]
D7
TE3
1
D6
TE2
0
D5
TE1
1
D4
TE0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D1
D0
0
0
TE3-0: EXT Master Mode Enable
When TE3-0 bits is set to “0101”, the write operation to addr=1EH is enabled.
TE3-0 bits should be set to “1010” except for EXT Master Mode.
TE3-0 bits must not be set to the value except for “1010” and “0101”.
Default: “1010”
Addr
1EH
Register Name
Mode Control 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
TMASTER
0
TMASTER: EXT Master Mode
The write operation to TMASTER bit is enabled when TE3-0 bits = “0101”.
0: Except EXT Master Mode (Default)
1: EXT Master Mode
MS0569-E-01
2006/12
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ASAHI KASEI
[AK5700]
SYSTEM DESIGN
Figure 39 and Figure 40 shows the system connection diagram for the AK5700. An evaluation board [AKD5700] is
available which demonstrates the optimum layout, power supply arrangements and measurement results.
17
16
15
14
CSN
CCLK
CDTI
MCKI
Top View
11
MCKO 10
DVSS
BCLK
DSP
10u 0.1u
10u 0.1u
2.2u
Power Supply
2.4 ∼ 3.6V
6
7
5
8
LRCK
DVDD
SDTO
24 VCOC
AVDD
23 AIN1
4
9
3
CSP
Rp
Cp
EXBCLK 13
18
PDN
AK5700VN
22 AIN‐
0.1u
0.1 x Cp
(Note)
EXSDTI
21 AIN2
AVSS
≤ 1u
20 TEST
2
Internal MIC
EXLRCK 12
VCOM
≤ 1u
DSP
19 MPWR
1
External MIC
2.2k
2.2k
μP
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5700 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5700 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4.
0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
- Mic input AC coupling capacitor should be 1μF or less to start the recording within 100ms.
Figure 39. Typical Connection Diagram (MIC Input)
MS0569-E-01
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ASAHI KASEI
[AK5700]
17
16
15
14
CSN
CCLK
CDTI
MCKI
20 TEST
EXSDTI
21 AIN2
AK5700VN
22 AIN−
Top View
11
MCKO 10
DVSS
BCLK
6
DSP
10u 0.1u
10u 0.1u
2.2u
Power Supply
2.4 ∼ 3.6V
5
7
DVDD
LRCK
AVDD
24 VCOC
4
8
3
SDTO
AVSS
23 AIN1
2
9
VCOM
CSP
Rp
Cp
EXBCLK 13
18
EXLRCK 12
0.1u
0.1 x Cp
(Note)
DSP
19 MPWR
1
Line In
PDN
μP
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5700 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5700 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4.
0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
Figure 40. Typical Connection Diagram (Line Input)
MS0569-E-01
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ASAHI KASEI
[AK5700]
1. Grounding and Power Supply Decoupling
The AK5700 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not
critical. AVSS and DVSS of the AK5700 should be connected to the analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5700 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK5700.
3. Analog Inputs
The analog inputs are single-ended or full-differential and input resistance is 60kΩ (typ)@MGAIN1-0 bits = “00”, 30kΩ
(typ)@MGAIN1-0 bits = “01” or “10”. The input signal range scales with 0.6 x AVDD Vpp(typ)@MGAIN 1-0 bits =
“00” centered around the internal common voltage (0.5 x AVDD). Usually the input signal is AC coupled using a
capacitor. The cut-off frequency is fc = (1/2πRC). The ADC output data format is 2’s complement. The DC offset
including the ADC’s own DC offset is removed by the internal HPF (fc=3.4Hz@ HPF1-0 bits = “00”, fs=44.1kHz). The
AK5700 can accept input voltages from AVSS to AVDD at single-ended.
MS0569-E-01
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ASAHI KASEI
[AK5700]
CONTROL SEQUENCE
„ Clock Set up
When ADC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:10H, D2)
(1) Power Supply & PDN pin = “L” Æ “H”
(4)
MCKO bit
(Addr:16H, D2)
(2)Addr:11H, Data:12H
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
Input
(3)Addr:10H, Data:04H
M/S bit
(Addr:11H, D1)
40msec(max)
(6)
BCLK pin
LRCK pin
Output
(4)Addr:16H, Data:04H
Addr:11H, Data:13H
Output
MCKO, BCLK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 41. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows.
(2a) M/S bit = “1” and setting of PLL3-0, FS3-0, BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(3) Power UpVCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source.
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
(6) The AK5700 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
MS0569-E-01
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ASAHI KASEI
[AK5700]
2. PLL Slave Mode (EXLRCK or EXBCLK pin)
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:10H, D2)
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 42. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin) is
supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4).
(5) Normal operation stats after that the PLL is locked.
MS0569-E-01
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ASAHI KASEI
[AK5700]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2)Addr:11H, Data:10H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKO bit
(Addr:16H, D2)
(3)Addr:10H, Data:04H
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
(4)Addr:16H, Data:04H
Addr:11H, Data:11H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
EXBCLK pin
EXLRCK pin
Input
EXBCLK and EXLRCK input start
Figure 43. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) EXBCLK and EXLRCK clocks should be synchronized with MCKO clock.
MS0569-E-01
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ASAHI KASEI
[AK5700]
4. EXT Slave Mode
Example:
Audio I/F Format: I2S
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2)
(2) Addr:11H, Data:00H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKI pin
Input
(3) Addr:10H, Data:04H
(4)
EXLRCK pin
EXBCLK pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 44. Clock Set Up Sequence (4)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, EXLRCK and EXBCLK are supplied.
MS0569-E-01
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ASAHI KASEI
[AK5700]
5. EXT Master Mode
Power Supply
(1)
Example:
PDN pin
(2)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select: 256fs
Sampling Frequency: 44.1kHz
(3)
PMVCM bit
(Addr:10H, D2)
MCKI pin
(1) Power Supply & PDN pin = “L” Æ “H”
Input
M/S bit
(Addr:11H, D1)
TE3-0 bits
(Addr:1DH, D7-4)
"1010"
(2)Addr:11H, Data:26H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:1DH, Data:50H
Addr:1EH, Data:02H
BCLK and LRCK output
"0101"
TMASTER bit
(Addr:1EH, D1)
BCLK pin
LRCK pin
Output
(3)Addr:10H, Data:04H
Figure 45. Clock Set Up Sequence (5)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows.
(2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(2c) TE3-0 bits = “0101”
(2d) TMASTER bit = “1”: BCLK and LRCK start to output.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
When the clock mode is changed from EXT Master Mode to other modes, the register should be set as above table after
PDN pin = “L” to “H” or TE3-0 bits = “1010”.
MS0569-E-01
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ASAHI KASEI
[AK5700]
6. Slave & Bypass Mode
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:16H, Data:08H
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 46. Clock Set Up Sequence (6)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) THR bit should be set to “1” and DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin)
is supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4).
(5) Normal operation stats after that the PLL is locked.
MS0569-E-01
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ASAHI KASEI
[AK5700]
7. Bypass Mode
Power Supply
(1)
(1) Power Supply & PDN pin = “L” Æ “H”
PDN pin
(2)
THR bit
(2) Addr:16H, Data:08H
(Addr:16H, D3)
EXLRCK pin
EXBCLK pin
EXSDTI pin
(3)
Input
MCKI, EXBCLK and EXLRCK input
Figure 47. Clock Set Up Sequence (7)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) THR bit should be set to “1”.
(3) After EXLRCK, EXBCLK and EXSDTI are input, LRCK, BCLK and SDTO start to output.
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[AK5700]
„ MIC Input Recording
Example:
PLL Master Mode
Audio I/F Format:I2S
Sampling Frequency:44.1kHz
Pre MIC AMP:+15dB
MIC Power On
ALC setting:Refer to Figrure 37
ALC bit = “1”
(1) Addr:15H, Data:2FH
FS3-0 bits
(Addr:15H, D3-0)
X,XXX
1111
(2) Addr:12H, Data:10H
Addr:13H, Data:01H
(1)
MIC Control
(Addr:12H, D4
& Addr:13H, D1-0)
Timer Control
(Addr:1AH)
ALC Control 1
(Addr:1BH)
ALC Control 2
(Addr:1CH)
0, 01
1, 01
(3) Addr:1AH, Data:0AH
(2)
XXH
0AH
(4) Addr:1BH, Data:E1H
(3)
XXH
E1H
(5) Addr:1CH, Data:81H
(4)
XXH
81H
01H
ALC State
(6) Addr:10H, Data:05H
(8)
(5)
ALC Disable
ALC Enable
ALC Disable
Recording
PMADC bit
(Addr:10H, D0)
3088 / fs
(7) Addr:10H, Data:04H
(7)
(6)
ADC Internal
State
Power Down
Initialize Normal State Power Down
(8) Addr:1CH, Data:01H
Figure 48. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure 35. Registers set-up sequence at ALC operation”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK5700 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 12H&13H)
(3) Set up Timer Select for ALC (Addr: 1AH)
(4) Set up REF value for ALC (Addr: 1BH)
(5) Set up LMTH1-0, RGAIN1-0, LMAT1-0 and ALC bits (Addr: 1CH)
(6) Power Up MIC and ADC: PMADC bit = “0” → “1”
The initialization cycle time of ADC is [email protected]=44.1kHz, HPF1-0 bits = “00”.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (0dB).
To start the recording within 100ms, the following sequence is required.
(6a) PMVCM=PMMP bits = “1”.
(6b) Wait for 2ms, then PMPLL bit = “1”.
(6c) Wait for 6ms, then PMADC bit = “1”.
(7) Power Down MIC and ADC: PMADC bit = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK5700 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADC bit = “0”). IVOL gain is not reset when PMADC = “0”,
and then IVOL operation starts from the setting value when PMADC bit is changed to “1”.
(8) ALC Disable: ALC bit = “1” → “0”
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[AK5700]
„ Stop of Clock
Master clock can be stopped when ADC is not used.
1. PLL Master Mode
Example:
(1)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:11H, D0)
M/S bit
(Addr:11H, D1)
(1) Addr:11H, Data:10H
(2)
MCKO bit
"H" or "L"
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 49. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL=M/S bits = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (EXLRCK, EXBCLK pin)
Example
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
BCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:11H, D0)
(2)
EXBCLK
Input
(1) Addr:11H, Data:0CH
(2)
EXLRCK
Input
(2) Stop the external clocks
Figure 50. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external EXBCLK and EXLRCK clocks
* Clock stop sequence is the same for Slave&Bypass Mode.
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[AK5700]
3. PLL Slave Mode (MCKI pin)
Example
Audio I/F Format: I2S
PLL Reference clock: MCKI
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(1) Addr:11H, Data:10H
(Addr:11H, D0)
(2)
MCKO bit
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop the external clocks
Figure 51. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO output: MCKO bit = “1” → “0”
(3) Stop the external master clock.
4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
EXBCLK
Input
EXLRCK
Input
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 52. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, EXBCLK and EXLRCK clocks.
* Clock stop sequence is the same for Bypass Mode.
5. EXT Master Mode
(1)
External MCKI
Input
Example
BCLK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 53. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI. BCLK and LRCK are fixed to “H” or “L”.
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[AK5700]
„ Power down
Power supply current is typ. 20μA by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are
powered-down. Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PDN pin = “L”. When
PDN pin = “L”, the registers are initialized.
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[AK5700]
PACKAGE
24pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.15
13
18
19
2.4± 0.15
4.0 ± 0.1
12
A
Exposed
Pad
24
7
0.40 ± 0.1
6
1
B
0.5
0.2
0.08
0.10 M
PIN #1 ID
(0.35 x 45 )
0.75± 0.05
0.23 ± 0.05
Note) The exposed pad on the bottom surface of the package must be open or connected to the ground.
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK5700]
MARKING
5700
XXXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD)
06/11/16
06/12/25
Revision
00
01
Reason
First Edition
Error correct
Page
Contents
40
Register Map (Addr=17H)
Bit (D0) value was changed: 0 → 1
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for
and hold AKM harmless from any and all claims arising from the use of said product in the absence
of such notification.
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