ALSC AS7C31026C

September 2006
Advance Information
AS7C31026C
®
3.3 V 64K X 16 CMOS SRAM
Features
• Industrial (-40o to 85oC) temperature
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10 ns address access time
- 5 ns output enable access time
• Low power consumption via chip deselect
• Upper and Lower byte pin
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
Logic block diagram
Control circuit
Address decoder
A8
WE
I/O
buffer
UB
OE
LB
CE
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS7C31026C
I/O0–I/O7
I/O8–I/O15
44-Pin SOJ (400 mil), TSOP 2
GND
A15
A7
A14
A6
A13
A5
A11
A4
A12
A3
• ESD protection ≥ 2000 volts
VCC
65,536 × 16
Array
A9
A2
A10
A1
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
- 48-ball 6 × 8 mm BGA
Pin arrangement
Address decoder
A0
• JEDEC standard packaging
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
0000048 - BGA Ball-Grid-Array Package
1
A LB
B I/O8
C I/O9
D VSS
E VDD
F I/O14
G I/O15
H NC
9/20/06, v 1.0
Alliance Memory
2
3
OE
A0
UB A3
I/O10 A5
I/O11 NC
I/O12 NC
I/O13 A14
NC A12
A8
A9
4
A1
A4
A6
A7
NC
A15
A13
A10
5
A2
CE
I/O1
I/O3
I/O4
I/O5
WE
A11
6
NC
I/O0
I/O2
VDD
VSS
I/O6
I/O7
NC
P. 1 of 10
Copyright © Alliance Memory. All rights reserved.
AS7C31026C
®
Functional description
The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10 ns with output enable access times (tOE) of 5 ns are ideal for highperformance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in
common industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+4.60
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.25
W
Storage temperature (plastic)
Tstg
–55
+125
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
50
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB), ISBI)
L
H
L
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
H
L
H
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
L
L
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
L
X
L
L
DIN
DIN
Write I/O0–I/O15 (ICC)
L
L
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
L
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (ICC)
Key: H = high, L = low, X = don’t care.
9/20/06, v 1.0
Alliance Memory
P. 2 of 10
AS7C31026C
®
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Supply voltage
VCC
3.0
3.3
3.6
V
Input voltage
VIH
2.0
–
VCC + 0.5
V
VIL
–0.5
–
0.8
Ambient operating temperature (industrial)
TA
–40
Max
–
Unit
V
o
85
C
VIL = -2.0V for pulse width less than 5ns, once per cycle.
VIH = VCC +2.0V for pulse width less than 5ns, once per cycle.
DC operating characteristics (over the operating range)1
AS7C31026C-10
Parameter
Sym
Test conditions
Min
Max
Unit
Input leakage current
| ILI |
VCC = Max
VIN = GND to VCC
–
5
µA
Output leakage current
| ILO |
VCC = Max
CE = VIH,
VOUT = GND to VCC
–
5
µA
ICC
VCC = Max,
CE ≤ VIL, IOUT = 0mA
f = fMax
–
160
mA
ISB
VCC = Max,
CE ≥ VIH, f = fMax
–
45
mA
ISB1
VCC = Max, CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or
VIN ≥ VCC–0.2 V, f = 0
–
10
mA
VOL
IOL = 8 mA, VCC = Min
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
V
Operating power supply current
Standby power supply current
Output voltage
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter
Input capacitance
Symbol
Signals
Test conditions
Max
Unit
CIN
A, CE, WE, OE, LB, UB
VIN = 0 V
6
pF
VIN = VOUT = 0 V
7
pF
I/O capacitance
CI/O
I/O
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
9/20/06, v 1.0
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P. 3 of 10
AS7C31026C
®
Read cycle (over the operating range)3,9
AS7C31026C-10
Parameter
Symbol
Min
Max
Unit
tRC
10
–
ns
Address access time
tAA
–
10
ns
3
Chip enable (CE) access time
tACE
–
10
ns
3
Output enable (OE) access time
tOE
–
5
ns
Output hold from address change
tOH
4
–
ns
5
CE low to output in low Z
tCLZ
4
–
ns
4, 5
CE high to output in high Z
tCHZ
–
5
ns
4, 5
OE low to output in low Z
tOLZ
0
–
ns
4, 5
Byte select access time
tBA
–
5
ns
Byte select Low to low Z
tBLZ
0
–
ns
4, 5
Byte select High to high Z
tBHZ
–
5
ns
4, 5
OE high to output in high Z
tOHZ
–
5
ns
4, 5
Power up time
tPU
0
–
ns
4, 5
Power down time
tPD
–
10
ns
4, 5
Read cycle time
Notes
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
DataOUT
tAA
tOH
Previous data valid
tOH
Data valid
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
tRC
Address
tAA
OE
tOE
tOLZ
tOH
CE
tLZ
tOHZ
tHZ
tACE
LB, UB
tBLZ
tBA
DataIN
9/20/06, v 1.0
tBHZ
Data valid
Alliance Memory
P. 4 of 10
AS7C31026C
®
Write cycle (over the operating range) 11
AS7C31026C-10
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
tWC
10
–
ns
Chip enable (CE) to write end
tCW
7
–
ns
Address setup to write end
tAW
7
–
ns
Address setup time
tAS
0
–
ns
Write pulse width
tWP
7
–
ns
Write recovery time
tWR
0
–
ns
Address hold from end of write
tAH
0
–
ns
Data valid to write end
tDW
5
–
ns
Data hold time
tDH
0
–
ns
5
Write enable to output in high Z
tWZ
–
5
ns
4, 5
Output active from write end
tOW
3
–
ns
4, 5
Byte select low to end of write
tBW
7
–
ns
Write waveform 1 (WE controlled)10,11
tWC
tAH
Address
tWR
tCW
CE
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
DataIN
Data valid
tWZ
DataOUT
9/20/06, v 1.0
tDH
Data undefined
Alliance Memory
tOW
high Z
P. 5 of 10
AS7C31026C
®
Write waveform 2 (CE controlled)10,11
tWC
tAH
Address
tAS
tWR
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDH
tDW
Data valid
DataIN
tWZ
tCLZ
DataOUT
high Z
Data undefined
tOW
high Z
AC test conditions
–
–
–
–
Output load: see Figure B.
Input pulse level: GND to 3.0 V. See Figure A.
Input rise and fall times: 3 ns. See Figure A.
Input and output timing reference levels: 1.5
Thevenin Equivalent:
168 Ω
DOUT
+1.728 V
+3.3 V
320 Ω
DOUT
+3.0 V
GND
90%
10%
255 Ω
90%
3 ns
10%
C13
GND
Figure B: 3.3 V Output load
Figure A: Input pulse
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
N/A
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
9/20/06, v 1.0
Alliance Memory
P. 6 of 10
AS7C31026C
®
Package dimensions
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
E He
44-pin TSOP 2
D
l
A2
0–5°
A1
e
b
Min
(mm)
Max
(mm)
A1
0.05
0.15
A2
0.95
1.05
b
0.30
0.45
c
0.120
0.21
D
18.31
18.52
E
10.06
10.26
He
11.68
11.94
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22
A
44-pin TSOP 2
e
l
1.2
0.80 (typical)
0.40
0.60
44-pin SOJ
400 mil
D
e
Min (in) Max (in)
44-pin SOJ
E1 E2
Pin 1
c
B
A2
A
A1
b
Seating
plane
E
A
0.128
0.148
A1
0.025
–
A2
0.105
0.115
B
0.026
0.032
b
0.015
0.020
c
0.007
0.013
D
1.120
1.130
E
E1
0.395
0.405
E2
0.435
0.445
e
9/20/06, v 1.0
Alliance Memory
0.370 NOM
0.050 NOM
P. 7 of 10
AS7C31026C
®
48-ball BGA
Bottom View
6
5
4
3
Top View
2
1
B/4
Ball #A1 index (see note 7)
Ball A1
A
C/4
B
(see note 8)
C
D
SRAM DIE
C1
C
F
G
H
J
A
B
B1
*pin 1 indicator will show as
engraved circle and/or Inc. trade mark
Detail View
Side View
A
E2
D
E
E2
Y
E
Die
Die
E1
A
0.3/Tμp
Minimum
Typical
Maximum
–
0.75
–
B
B1
6.00 BSC
–
C
9/20/06, v 1.0
3.75
–
8.00 BSC
C1
–
5.25
–
D
0.25
0.30
0.40
E
0.14
1.24
1..34
E1
–
0.68
–
E2
0.15
0.20
0.25
Y
–
–
0.010
Notes
1 Bump counts: 48 (8 row x 6 column).
2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).
3 Units: millimeters.
4 All tolerance are +/- 0.050 unless otherwise specified.
5 Typ: typical.
6 Y is coplanarity: 0.010 (max).
7 “A1” ID corner must be identified by chamfer, ink mark,
metallized marking, indentation or other feature on the package body.
8 If “A1” ID corner is on the package body, it must be located
within the zone indicated.
Alliance Memory
P. 8 of 10
AS7C31026C
®
Ordering codes
Volt/Temp
10 ns
Plastic SOJ, 400 mil
Package
3.3V industrial
AS7C31026C-10JIN
TSOP 2, 10.2 x 18.4 mm
3.3V industrial
AS7C31026C-10TIN
BGA, 7 x 7 mm
3.3V industrial
AS7C31026C-10BIN
Part numbering system
AS7C
SRAM
prefix
9/20/06, v 1.0
X
Voltage:
3 = 3.3 V
CMOS
1026B
–XX
Device
Access
number
time
X
X
Package:
Temperature
J = SOJ 400 mil
I
=
industrial:
-40° C
T = TSOP 2, 10.2 x 18.4 mm
to 85° C
B=BGA, 7 x 7 mm
Alliance Memory
X
N = Lead Free Part
P. 9 of 10
AS7C31026C
®
®
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C31026C
Document Version: v 1.0
www.alliancememory.com
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance.
All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents
Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended
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