ANACHIP PEEL22CV10AZSI-25

PEEL™ 22CV10AZ -25
CMOS Programmable Electrically Erasable Logic Device
Architectural Flexibility
- 133 product terms x 44 input AND array
Features
Ultra Low Power Operation
- VCC = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- tPD = 25ns.
- Up to 22 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Synchronous preset, asynchronous clear
- Independent output enables
- Programmable clock source and polarity
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Ideal for power-sensitive systems
Development/Programmer Support
- Third party software and programmers
- Anachip PLACE Development Software
General Description
The PEEL™22CV10AZ is JEDEC file compatible with standard
22V10 PLDs. Eight additional configurations per macrocell (a
total of 12) are also available by using the “+” software/programming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional
macrocell configurations allow more logic to be put into every
device, potentially reducing the design's component count and
lowering the power requirements even further.
The PEEL™22CV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) device that provides a low power alternative to
ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin
DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A
“zero-power” (100µA max. ICC) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications such as
handheld meters, portable communication equipment and lap- top
computers/ peripherals. EE-reprogrammability provides the
convenience of instant reprogramming for development and a
reusable production inventory minimizing the impact of programming changes or errors. EE-reprogrammability also
improves factory testability, thus ensuring the highest quality
possible.
Development
and
programming
support
for
the
PEEL™22CV10AZ is provided by popular third-party programmers and development software. Anachip also offers free WinPLACE development software.
Figure 19 Block Diagram
Figure 19 Pin Configuration
DIP
PLCC
I/CLK
1
24
VCC
I
2
23
I/O
I
3
22
I/O
I
4
21
I/O
I
5
20
I/O
I
6
19
I/O
I
7
18
I/O
I
8
17
I/O
I
9
16
I/O
I
10
15
I/O
I
11
14
I/O
GND
12
13
I
TSSOP
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
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Figure 21 PEEL™22CV10AZ Logic Array Diagram
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Function Description
grammer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array.
The device is configured to perform the user-defined function by
programming selected connections in the AND array. (Note that
PEEL™ device programmers automatically program all of the
connections on unused product terms so that they will have no
effect on the output function).
The implements logic functions as sum-of-products expressions in
a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input
signals into the array. User-configurable output structures in the
form of I/O macrocells further increase logic flexibility.
Architecture Overview
Variable Product Term Distribution
The architecture is illustrated in the block diagram of Figure 19.
Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and
10 outputs for creating logic functions (see Figure 21). At the
core of the device is a programmable electrically-erasable AND
array that drives a fixed OR array. With this structure, the
PEEL™22CV10AZ can implement up to 10 sum-of-products
logic expressions.
The PEEL™22CV10AZ provides 120 product terms to drive the
10 OR functions. These product terms are distributed among the
outputs in groups of 8, 10, 12, 14, and 16 to form logical sums
(see Figure 21). This distribution allows optimum use of the
device resources.
Programmable I/O Macrocell
Associated with each of the ten OR functions is an I/O macrocell
that can be independently programmed to one of four different
configurations in standard 22V10 mode, or any one of 12 configurations using the special “Plus” mode. The programmable macrocells allow each I/O to be used to create sequential or
combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND
array.
The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the configuration of the PEEL™22CV10AZ to the precise requirements of
your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
the macrocell is determined by four EEPROM bits that control the
multiplexers. These bits determine the output polarity, output type
(registered or non-registered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1. for
details. Four of these macrocells duplicate the functionality of the
industry-standard PAL22V10. (See Figure 21 and Table 1.)
AND/OR Logic Array
The programmable AND array of the PEEL™22CV10AZ
(shown in Figure 21) is formed by input lines intersecting prod- uct
terms. The input lines and product terms are used as follows:
44 Input Lines:
– 24 input lines carry the true and complement of the signals
applied to the 12 input pins
– 20 additional lines carry the true and complement values of
feedback or input signals from the 10 I/Os
133 Product Terms:
Figure 20 Block Diagram of the
PEEL™22CV10A I/O Macrocell
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 44-input AND gate. A product term that is connected to both the true and complement of an input signal will
always be FALSE and therefore will not affect the OR function
that it drives. When all the connections on a product term are
opened, a “don’t care” state exists and that term will always be
TRUE.
When programming the PEEL™22CV10AZ, the device proAnachip Corp.
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In addition to emulating the four PAL-type output structures
(configurations 3, 4, 9, and 10), The macrocell provides eight
additional configurations. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 22. These structures
are accessed by specifying the PEEL™22CV10A+ or
PEEL™22CV10A++ option when assembling the equations.
Output Polarity
Figure 21 Equivalent Circuits for the Four Configurations of the I/O Macrocell
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will
always be logically false and the I/O will function as a dedicated
input.
Input/Feedback Select
When configuring an I/O macrocell to implement a registered
function (configurations 1 and 2 in Figure 21), the Q output of the
flip-flop drives the feedback term. When configuring an I/O macrocell to implement a combinatorial output (configurations 3 and
4 in Figure 21), the feedback term is taken from the I/O pin. In this
case, the pin can be used as a dedicated input or a bi-direc- tional
I/O (Refer also to Table 1.)
Table 1. PEEL™22CV10A Macrocell
Configuration Bits
Configuration
#
1
2
3
A
B
0
1
0
0
0
1
4
Input/Feedback
Select
Output Select
Register
Feedback
Register
A unique feature of the PEEL™22CV10AZ is a programmable
clock multiplexer that allows you to select true or complement
Active High
forms of either the input pin or a product-term clock source. This
feature can be accessed by specifying the PEEL™22CV10A++
option when assembling the equations.
Active Low
Bi-Directional
I/O
Programmable Clock Options
Active Low
Combinatorial
Active High
When creating a PEEL™ device design, the desired macrocell
configuration is generally specified explicitly in the design file.
When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q output of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
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Figure 22 Equivalent Circuits for the Twelve Configurations of the PEEL™22CV10AZ+ I/O Macrocell
Table 1. I/O Macrocell Equivalent Circuits
#
Configuration
A
B
C
D
1
2
3
4
5
6
7
8
9
10
11
12
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
Input/Feedback Select
Output Select
Register
Bi-directional I/O
Combinatorial
Register
Combinatorial Feedback
Combinatorial
Register
Register Feedback
Combinatorial
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Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
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Zero Power Feature
Design Security
The CMOS PEEL™22CV10AZ features “Zero-Power” standby
operation for ultra-low power consumption. With the “ZeroPower” feature, transition-detection circuitry monitors the inputs,
I/Os (including CLK) and feedbacks. If these signals do not
change for a period of time greater than approximately two tPDs,
the outputs are latched in their current state and the device automatically powers down. When the next signal transition is
detected, the device will “wake up” for active operation until the
signals stop switching long enough to trigger the next powerdown.
The PEEL™22CV10AZ provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a
separate step, after the device has been programmed. Once the
security bit is set it is impossible to verify (read) or program the
PEEL™ until the entire device has first been erased with the
bulk-erase function.
As a result of the “Zero-Power” feature, significant power savings can be realized for combinatorial or sequential operations
when the inputs or clock change at a modest rate (see Figure 23).
The signature word feature allows a 64-bit code to be prointo
the
PEEL™22CV10AZ
if
the
grammed
PEEL™22CV10AZ+ software option is used. The code can be
read back even after the security bit has been set. The signature
word can be used to identify the pattern programmed into the
device or to record the design revision, etc.
Signature Word
Figure 23 Typical ICC vs. Input Clock Frequency
for the 22CV10AZ.
Programming Support
Anachip’s JEDEC file translator allows easy conversion of existing 24 pin PLD designs to the PEEL™22CV10AZ, without the
need for redesign. Anachip supports a broad range of popular
third party design entry systems, including the Abel-to-PEEL
Arrays fitter software. Anachip also offers (for free) its proprietary WinPLACE software, an easy-to-use entry level PC-based
software development system.
22CV10AZ Frequency vs. ICC
100
10
Programming support includes all the popular third party programmers such as BP Microsystems, System General, Logical
Devices, and numerous others.
1
0.1
0.01
0.001
0.001
0.01
0.1
1
10
Frequency in MHz
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This device has been designed and tested for the specified
operating ranges. Improper operation outside of these
levels is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Table 1. Absolute Maximum Ratings
Symbol
VCC
V I, V O
IO
TST
TLT
Parameter
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Relative to Ground1
Per Pin (IOL, IOH)
Soldering 10 Seconds
Rating
Unit
-0.5 to +7.0
-0.5 to VCC +0.6
V
V
mA
o
C
o
C
±25
-65 to +150
+300
Table 2. Operating Range
Symbol
Parameter
VCC
Supply Voltage
TA
Ambient Temperature
TR
TF
Clock Rise Time
Clock Fall Time
VCC Rise Time
TRVCC
Conditions
Commercial
Industrial
Commercial
Industrial
See Note 3.
See Note 3.
See Note 3.
Min
Max
Unit
4.75
4.5
0
-40
5.25
5.5
+70
+85
20
20
250
V
V
o
C
o
C
ns
ns
ms
Table 3. D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)
Symbol
Parameter
VOH
VOHC
VOL
VOLC
VIH
VIL
IIL
ISC
ICCS
ICC10
CIN7
COUT7
Output HIGH Voltage – TTL
Output HIGH Voltage – CMOS
Output LOW Voltage – TTL
Output LOW Voltage – CMOS
Input HIGH Voltage
Input LOW Voltage
Input and I/O Leakage Current
Output Short Circuit Current
VCC Current, Standby
VCC Current, f=1MHz
Input Capacitance
Output Capacitance
Conditions
VCC = Min, IOH = -4.0 mA
VCC = Min, IOH = -10.0 µA
VCC = Min, IOL = 16.0 mA
VCC = Min, IOL = 10.0 µA
Min
2.4
VCC-0.3
2.0
-0.3
VCC = Max, GND ≤ VIN ≤ VCC, I/O=High Z
VCC = Max, VO = 0.5V, TA = 25oC
VIN = 0V or VCC, All Outputs disabled4
VIN = 0V or VCC, All Outputs disabled4
TA = 25oC, VCC=5.0V @ f = 1MHz
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Max
-30
10 (typ)
2 (typ)
0.5
0.15
VCC+0.3
0.8
±10
-135
100
5
6
12
Unit
V
V
V
V
V
V
µA
mA
µA
mA
pF
pF
Rev. 1.0 Dec 16, 2004
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Over the operating range 8
Table 10.
Symbol
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
-25
Parameter
Min
Input5 to non-registered output
Input5 to output enable6
Input5 to output disable6
Clock to Output
Clock to comb. Output delay via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1)
Internal feedback (1/tSC + tCF)11
External feedback (1/tCP)11
No feedback (1/tCL+tCH)11
Asynchronous Reset Pulse Width
Input to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers in clear state12
Max
25
25
25
15
35
9
15
0
13
30
41.6
33.3
38.4
25
25
25
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than 20 ns.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90%
levels.
4. I/O pins are 0V and VCC.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V, TOD is measured from
input transition to VOH-0.1V or VOL+0.1V; VREF=VL.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the 10% and
90% points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency.
12. All inputs at GND.
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PEEL™ Device and Array Test Loads
Technology
R1
R2
RL
VL
CL
CMOS
TTL
480kΩ
235Ω
480kΩ
159Ω
228kΩ
95Ω
2.375V
2.02V
33pF
33pF
Ordering Information
Part Number
Speed
Temperature
PEEL22CV10AZP-25 (L)
PEEL22CV10AZJ-25 (L)
PEEL22CV10AZS-25 (L)
PEEL22CV10AZT-25 (L)
PEEL22CV10AZPI-25 (L)
PEEL22CV10AZJI-25 (L)
PEEL22CV10AZSI-25 (L)
PEEL22CV10AZTI-25 (L)
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Package
24-pin Plastic DIP
28-pin PLCC
24-pin SOIC
24-pin TSSOP
24-pin Plastic DIP
28-pin PLCC
24-pin SOIC
24-pin TSSOP
Part Number
Device
Suffix
PEELTM22CV10AZ PI-25X
Lead Free
Package
Speed
P = 24-pin Plastic 300 mil DIP
J = 28-pin Plastic (J) Leaded Chip Carrier (PLCC)
S = 24-pin SOIC 300 mil Gullwing
T = 24-pin TSSOP 170 mil
Blank : Normal
L : Lead Free Package
-25 = 25ns tpd
Temperature Range
(Blank) = Commercial 0 to +70oC
I = Industrial -40 to +85oC
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Anachip Corp.
Head Office,
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Anachip USA
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The
information furnished by Anachip in this publication is believed to be accurate and reliable. However,
there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other
rights of third parties resulting from its use. No license is granted under any patents or patent rights of
Anachip. Anachip’s products are not authorized for use as critical components in life support devices
or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
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